From Mindspeed SDK v2.1: 000-mspd-uboot_c2k_1_00_1.patch

Change-Id: I524f9238ecf930a68a5ee78022ea21f910ddd6d6
diff --git a/MAKEALL b/MAKEALL
index 879a17f..3fd6eac 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -213,6 +213,14 @@
 "
 
 #########################################################################
+## Mindspeed Comcerto Systems
+#########################################################################
+LIST_COMCERTO100="	\
+        packet-iad      asic           router          ferouter         \
+        moca                                                            \
+"
+
+#########################################################################
 ## Xscale Systems
 #########################################################################
 
@@ -230,6 +238,7 @@
 	${LIST_SA}							\
 	${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11}		\
 	${LIST_pxa} ${LIST_ixp}						\
+        ${LIST_COMCERTO100}                                             \
 "
 
 #########################################################################
@@ -335,7 +344,7 @@
 do
 	case "$arg" in
 	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
-	arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
+	arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp|COMCERTO100| \
 	microblaze| \
 	mips|mips_el| \
 	nios|nios2| \
diff --git a/Makefile b/Makefile
index a282342..9cf7952 100644
--- a/Makefile
+++ b/Makefile
@@ -125,7 +125,7 @@
 CROSS_COMPILE = powerpc-linux-
 endif
 ifeq ($(ARCH),arm)
-CROSS_COMPILE = arm-linux-
+CROSS_COMPILE = arm-openwrt-linux-
 endif
 ifeq ($(ARCH),i386)
 ifeq ($(HOSTARCH),i386)
@@ -206,6 +206,7 @@
 LIBS += drivers/libdrivers.a
 LIBS += drivers/nand/libnand.a
 LIBS += drivers/nand_legacy/libnand_legacy.a
+LIBS += drivers/c2000_eth/libcomcerto_pfe.a
 LIBS += drivers/sk98lin/libsk98lin.a
 LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
@@ -215,7 +216,11 @@
 .PHONY : $(LIBS)
 
 # Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+#PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`)
+ifneq ($(ARCH),arm)
+PLATFORM_LIBS += -lgcc
+endif
 
 # The "tools" are needed early, so put this first
 # Don't include stuff already done in $(LIBS)
@@ -230,6 +235,27 @@
 U_BOOT_NAND = $(obj)u-boot-nand.bin
 endif
 
+#For c1k ARAM images no need to do address change
+CHANGE_ADDRESS=y
+ifeq ($(BOARD),c1kevm)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c1kasic)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c2kevm)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c2kasic)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c1kmfcn-evm)
+CHANGE_ADDRESS=n
+endif
+ifeq ($(BOARD),c1km83240)
+CHANGE_ADDRESS=n
+endif
+
 __OBJS := $(subst $(obj),,$(OBJS))
 __LIBS := $(subst $(obj),,$(LIBS))
 
@@ -259,6 +285,15 @@
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
+
+
+$(obj)u-boot_aram.elf:	$(obj)u-boot
+ifeq ($(CHANGE_ADDRESS),y)
+		$(OBJCOPY) ${OBJCFLAGS} --change-addresses -0x760ffe00 $< $@
+else
+		cp u-boot u-boot_aram.elf
+endif
+
 $(obj)u-boot:		depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
 		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
@@ -1775,6 +1810,44 @@
 mp2usb_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
 
+tsavo515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo515 mindspeed comcerto
+
+tsavo515_nor_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo515_nor mindspeed comcerto
+
+tsavo530_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo530 mindspeed comcerto
+
+tsavo530_nor_config     :       unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo530_nor mindspeed comcerto
+
+megamombasa515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t tsavo515 mindspeed comcerto
+
+megamombasa515_sdc1_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t megamombasa515_sdc1 mindspeed comcerto
+
+megamombasa515_256M_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t megamombasa515_256M mindspeed comcerto
+
+malindi_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t malindi mindspeed comcerto
+
+ipots48-800_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t ipots48-800 mindspeed comcerto
+
+ipots48-515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t ipots48-515 mindspeed comcerto
+
+udev515_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t udev515 mindspeed comcerto
+
+udev800_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t udev800 mindspeed comcerto
+
+nairobi_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t nairobi mindspeed comcerto
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -2037,6 +2110,419 @@
 omap2420h4_config :    unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
 
+supermombasa910_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 supermombasa910 mindspeed comcerto
+
+matisse_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 supermombasa910 mindspeed comcerto
+
+xtract_eb = $(subst -eb,,$(subst _config,,$1))
+
+packet-iad-eb_config \
+packet-iad_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for packet-iad-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 packet-iad mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+packet-iad-nand-eb_config \
+packet-iad-nand_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for packet-iad-nand-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 packet-iad mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+packet-iad-c50_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 packet-iad mindspeed comcerto
+
+asic-eb_config \
+asic_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for asic-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 asic mindspeed comcerto
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-eb_config \
+router_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for router-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 router mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-nand-eb_config \
+router-nand_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for router-nand-eb"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 router mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-c50_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 router mindspeed comcerto
+
+ferouter_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 ferouter mindspeed comcerto
+
+moca_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 moca mindspeed comcerto
+
+packet-iad-eb_aram_config \
+packet-iad_aram_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for packet-iad-eb_aram"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 packet-iad mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+asic-eb_aram_config \
+asic_aram_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for asic-eb_aram"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 asic mindspeed comcerto
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+router-eb_aram_config \
+router_aram_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "#define BE8_MODE 1" >> $(TOPDIR)/include/config.h ; \
+		echo "... configured for router-eb_aram"; \
+	fi;
+	@$(MKCONFIG) -a $(call xtract_eb,$@) arm arm1136 router mindspeed comcerto
+	@echo "#define CFG_ARM_CLOCK      450000000     /* 450 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	@if [ "$(findstring eb_, $@)" ] ; then \
+		echo "BE8_MODE = y" >> $(TOPDIR)/include/config.mk ; \
+	fi;
+
+ferouter_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 ferouter mindspeed comcerto
+
+moca_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 moca mindspeed comcerto
+
+packet-iad-c50_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 packet-iad mindspeed comcerto
+
+router-c50_aram_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm1136 router mindspeed comcerto
+
+M82134G:
+	sed -i '/CFG_ARM_CLOCK/d' $(TOPDIR)/include/config.h
+	echo "#define CFG_ARM_CLOCK      400000000     /* 400 MHz, must be multiple of 25MHz */" >>$(TOPDIR)/include/config.h
+	echo "#define M82134G            1" >>$(TOPDIR)/include/config.h
+
+packet-iad-eb-M82134G_config : packet-iad-eb_config M82134G
+packet-iad-M82134G_config : packet-iad_config M82134G
+packet-iad-nand-eb-M82134G_config : packet-iad-nand-eb_config M82134G
+packet-iad-nand-M82134G_config : packet-iad-nand_config M82134G
+packet-iad-eb_aram-M82134G_config : packet-iad-eb_aram_config M82134G
+packet-iad_aram-M82134G_config	:  packet-iad_aram_config M82134G
+router-eb-M82134G_config : router-eb_config M82134G
+router-M82134G_config : router_config M82134G
+router-nand-eb-M82134G_config : router-nand-eb_config M82134G
+router-nand-M82134G_config : router-nand_config M82134G
+router-eb_aram-M82134G_config : router-eb_aram_config M82134G
+router_aram-M82134G_config : router_aram_config M82134G
+
+
+M83263G:
+	echo "#include <configs/m8326XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83263G\"" >> $(obj)include/config.h;
+
+M83262G:
+	echo "#include <configs/m8326XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83262G\"" >> $(obj)include/config.h;
+
+M83261G:
+	echo "#include <configs/m8326XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83261G\"" >> $(obj)include/config.h;
+
+M83160G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_600_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83160G\"" >> $(obj)include/config.h;
+
+M83252G:
+	echo "#include <configs/m8325XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83252G\"" >> $(obj)include/config.h;
+
+M83251G:
+	echo "#include <configs/m8325XG.h>" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83251G\"" >> $(obj)include/config.h;
+
+M83242G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_450_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83242G\"" >> $(obj)include/config.h;
+
+M83241G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_450_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83241G\"" >> $(obj)include/config.h;
+
+M83240G:
+	echo "#include <configs/m8324XG.h>" >> $(obj)include/config.h;
+	echo "#define CFG_CLK CFG_CLK_400_165_330" >> $(obj)include/config.h;
+	echo "#define COMCERTO_PART_NO \"M83240G\"" >> $(obj)include/config.h;
+
+nofpp:
+	echo "#define CONFIG_NOFPP_MODE 1" >> $(obj)include/config.h;
+
+eb:
+	@mkdir -p $(obj)include
+	@echo "#define BE8_MODE 1" >> $(obj)include/config.h ;
+	@echo "... configured for c1kevm-eb";
+	@echo "BE8_MODE = y" >> $(obj)include/config.mk ;
+
+_c1kevm_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kevm/config.mk;
+	@$(MKCONFIG) -a c1kevm arm arm1136 c1kevm mindspeed comcerto
+
+_c1kevm-nand_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kevm/config.mk;
+	@$(MKCONFIG) -a c1kevm-nand arm arm1136 c1kevm mindspeed comcerto
+
+_c1kevm_aram_config:
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1kevm/config.mk;
+	@$(MKCONFIG) -a c1kevm_aram arm arm1136 c1kevm mindspeed comcerto
+
+c1kevm_config: unconfig M83263G _c1kevm_config
+c1kevm-M83263G_config: unconfig M83263G _c1kevm_config
+c1kevm-M83262G_config: unconfig M83262G _c1kevm_config
+c1kevm-M83261G_config: unconfig M83261G _c1kevm_config
+c1kevm-M83160G_config: unconfig M83160G _c1kevm_config
+c1kevm-M83252G_config: unconfig M83252G _c1kevm_config
+c1kevm-M83251G_config: unconfig M83251G _c1kevm_config
+c1kevm-M83242G_config: unconfig M83242G _c1kevm_config
+c1kevm-M83241G_config: unconfig M83241G _c1kevm_config
+c1kevm-M83240G_config: unconfig M83240G _c1kevm_config
+
+c1kevm-nand_config: unconfig M83263G _c1kevm-nand_config
+
+c1kevm_aram_config: unconfig M83263G _c1kevm_aram_config
+c1kevm-M83263G_aram_config: unconfig M83263G _c1kevm_aram_config
+c1kevm-M83262G_aram_config: unconfig M83262G _c1kevm_aram_config
+c1kevm-M83261G_aram_config: unconfig M83261G _c1kevm_aram_config
+c1kevm-M83160G_aram_config: unconfig M83160G _c1kevm_aram_config
+c1kevm-M83252G_aram_config: unconfig M83252G _c1kevm_aram_config
+c1kevm-M83251G_aram_config: unconfig M83251G _c1kevm_aram_config
+c1kevm-M83242G_aram_config: unconfig M83242G _c1kevm_aram_config
+c1kevm-M83241G_aram_config: unconfig M83241G _c1kevm_aram_config
+c1kevm-M83240G_aram_config: unconfig M83240G _c1kevm_aram_config
+
+c1kevm-nofpp_config: unconfig M83263G nofpp _c1kevm_config
+c1kevm-M83263G-nofpp_config: unconfig M83263G nofpp _c1kevm_config
+c1kevm-M83262G-nofpp_config: unconfig M83262G nofpp _c1kevm_config
+c1kevm-M83261G-nofpp_config: unconfig M83261G nofpp _c1kevm_config
+c1kevm-M83160G-nofpp_config: unconfig M83160G nofpp _c1kevm_config
+c1kevm-M83252G-nofpp_config: unconfig M83252G nofpp _c1kevm_config
+c1kevm-M83251G-nofpp_config: unconfig M83251G nofpp _c1kevm_config
+c1kevm-M83242G-nofpp_config: unconfig M83242G nofpp _c1kevm_config
+c1kevm-M83241G-nofpp_config: unconfig M83241G nofpp _c1kevm_config
+c1kevm-M83240G-nofpp_config: unconfig M83240G nofpp _c1kevm_config
+
+c1kevm-nand-nofpp_config: unconfig M83263G nofpp _c1kevm-nand_config
+
+c1kevm-eb_config: unconfig M83263G _c1kevm_config eb
+c1kevm-M83263G-eb_config: unconfig M83263G _c1kevm_config eb
+c1kevm-M83262G-eb_config: unconfig M83262G _c1kevm_config eb
+c1kevm-M83261G-eb_config: unconfig M83261G _c1kevm_config eb
+c1kevm-M83160G-eb_config: unconfig M83160G _c1kevm_config eb
+c1kevm-M83252G-eb_config: unconfig M83252G _c1kevm_config eb
+c1kevm-M83251G-eb_config: unconfig M83251G _c1kevm_config eb
+c1kevm-M83242G-eb_config: unconfig M83242G _c1kevm_config eb
+c1kevm-M83241G-eb_config: unconfig M83241G _c1kevm_config eb
+c1kevm-M83240G-eb_config: unconfig M83240G _c1kevm_config eb
+
+c1kevm-eb_aram_config: unconfig M83263G _c1kevm_aram_config eb
+c1kevm-M83263G-eb_aram_config: unconfig M83263G _c1kevm_aram_config eb
+c1kevm-M83262G-eb_aram_config: unconfig M83262G _c1kevm_aram_config eb
+c1kevm-M83261G-eb_aram_config: unconfig M83261G _c1kevm_aram_config eb
+c1kevm-M83160G-eb_aram_config: unconfig M83160G _c1kevm_aram_config eb
+c1kevm-M83252G-eb_aram_config: unconfig M83252G _c1kevm_aram_config eb
+c1kevm-M83251G-eb_aram_config: unconfig M83251G _c1kevm_aram_config eb
+c1kevm-M83242G-eb_aram_config: unconfig M83242G _c1kevm_aram_config eb
+c1kevm-M83241G-eb_aram_config: unconfig M83241G _c1kevm_aram_config eb
+c1kevm-M83240G-eb_aram_config: unconfig M83240G _c1kevm_aram_config eb
+
+c1kevm-nand-eb_config: unconfig M83263G _c1kevm-nand_config eb
+
+c1kasic_config	:	unconfig
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kasic/config.mk;
+	@$(MKCONFIG) -a c1kasic arm arm1136 c1kasic mindspeed comcerto
+
+c1kasic-nand_config	:	unconfig
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kasic/config.mk;
+	@$(MKCONFIG) -a c1kasic arm arm1136 c1kasic mindspeed comcerto
+
+c1kasic_aram_config	:	unconfig
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1kasic/config.mk;
+	@$(MKCONFIG) -a c1kasic arm arm1136 c1kasic mindspeed comcerto
+
+_c1kmfcn-evm_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kmfcn-evm/config.mk;
+	@$(MKCONFIG) -a c1kmfcn-evm arm arm1136 c1kmfcn-evm mindspeed comcerto
+
+_c1kmfcn-evm-nand_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1kmfcn-evm/config.mk;
+	@$(MKCONFIG) -a c1kmfcn-evm-nand arm arm1136 c1kmfcn-evm mindspeed comcerto
+
+_c1kmfcn-evm_aram_config:
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1kmfcn-evm/config.mk;
+	@$(MKCONFIG) -a c1kmfcn-evm_aram arm arm1136 c1kmfcn-evm mindspeed comcerto
+
+c1kmfcn-evm_config: unconfig M83263G _c1kmfcn-evm_config
+c1kmfcn-evm-M83263G_config: unconfig M83263G _c1kmfcn-evm_config
+c1kmfcn-evm-M83262G_config: unconfig M83262G _c1kmfcn-evm_config
+c1kmfcn-evm-M83261G_config: unconfig M83261G _c1kmfcn-evm_config
+c1kmfcn-evm-M83160G_config: unconfig M83160G _c1kmfcn-evm_config
+c1kmfcn-evm-M83252G_config: unconfig M83252G _c1kmfcn-evm_config
+c1kmfcn-evm-M83251G_config: unconfig M83251G _c1kmfcn-evm_config
+c1kmfcn-evm-M83242G_config: unconfig M83242G _c1kmfcn-evm_config
+c1kmfcn-evm-M83241G_config: unconfig M83241G _c1kmfcn-evm_config
+c1kmfcn-evm-M83240G_config: unconfig M83240G _c1kmfcn-evm_config
+
+c1kmfcn-evm-nand_config: unconfig M83263G _c1kmfcn-evm-nand_config
+
+c1kmfcn-evm_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83263G_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83262G_aram_config: unconfig M83262G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83261G_aram_config: unconfig M83261G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83160G_aram_config: unconfig M83160G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83252G_aram_config: unconfig M83252G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83251G_aram_config: unconfig M83251G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83242G_aram_config: unconfig M83242G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83241G_aram_config: unconfig M83241G _c1kmfcn-evm_aram_config
+c1kmfcn-evm-M83240G_aram_config: unconfig M83240G _c1kmfcn-evm_aram_config
+
+c1kmfcn-evm-nofpp_config: unconfig M83263G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83263G-nofpp_config: unconfig M83263G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83262G-nofpp_config: unconfig M83262G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83261G-nofpp_config: unconfig M83261G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83160G-nofpp_config: unconfig M83160G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83252G-nofpp_config: unconfig M83252G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83251G-nofpp_config: unconfig M83251G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83242G-nofpp_config: unconfig M83242G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83241G-nofpp_config: unconfig M83241G nofpp _c1kmfcn-evm_config
+c1kmfcn-evm-M83240G-nofpp_config: unconfig M83240G nofpp _c1kmfcn-evm_config
+
+c1kmfcn-evm-eb_config: unconfig M83263G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83263G-eb_config: unconfig M83263G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83262G-eb_config: unconfig M83262G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83261G-eb_config: unconfig M83261G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83160G-eb_config: unconfig M83160G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83252G-eb_config: unconfig M83252G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83251G-eb_config: unconfig M83251G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83242G-eb_config: unconfig M83242G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83241G-eb_config: unconfig M83241G _c1kmfcn-evm_config eb
+c1kmfcn-evm-M83240G-eb_config: unconfig M83240G _c1kmfcn-evm_config eb
+
+c1kmfcn-evm-nand-nofpp_config: unconfig M83263G nofpp _c1kmfcn-evm-nand_config
+
+c1kmfcn-evm-eb_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83263G-eb_aram_config: unconfig M83263G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83262G-eb_aram_config: unconfig M83262G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83261G-eb_aram_config: unconfig M83261G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83160G-eb_aram_config: unconfig M83160G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83252G-eb_aram_config: unconfig M83252G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83251G-eb_aram_config: unconfig M83251G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83242G-eb_aram_config: unconfig M83242G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83241G-eb_aram_config: unconfig M83241G _c1kmfcn-evm_aram_config eb
+c1kmfcn-evm-M83240G-eb_aram_config: unconfig M83240G _c1kmfcn-evm_aram_config eb
+
+_c1km83240_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1km83240/config.mk;
+	@$(MKCONFIG) -a c1km83240 arm arm1136 c1km83240 mindspeed comcerto
+
+_c1km83240-nand_config:
+	@echo "TEXT_BASE = 0x84000000" >$(obj)board/mindspeed/c1km83240/config.mk;
+	@$(MKCONFIG) -a c1km83240-nand arm arm1136 c1km83240 mindspeed comcerto
+
+_c1km83240_aram_config:
+	@echo "TEXT_BASE = 0x0A006000" >$(obj)board/mindspeed/c1km83240/config.mk;
+	@$(MKCONFIG) -a c1km83240_aram arm arm1136 c1km83240 mindspeed comcerto
+
+
+c1km83240_config: unconfig M83240G _c1km83240_config
+c1km83240-M83160G_config: unconfig M83160G _c1km83240_config
+c1km83240-M83240G_config: unconfig M83240G _c1km83240_config
+
+c1km83240-nand_config: unconfig M83240G _c1km83240-nand_config
+
+c1km83240-nofpp_config: unconfig M83240G nofpp _c1km83240_config
+c1km83240-M83240G-nofpp_config: unconfig M83240G nofpp _c1km83240_config
+c1km83240-M83160G-nofpp_config: unconfig M83160G nofpp _c1km83240_config
+
+c1km83240-nand-nofpp_config: unconfig M83240G nofpp _c1km83240-nand_config
+
+c1km83240_aram_config: unconfig M83240G _c1km83240_aram_config
+c1km83240-M83160G_aram_config: unconfig M83160G _c1km83240_aram_config
+c1km83240-M83240G_aram_config: unconfig M83240G _c1km83240_aram_config
+
+
+_c2kevm_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kevm/config.mk;
+	@$(MKCONFIG) -a c2kevm arm arm_cortexa9 c2kevm mindspeed comcerto
+
+c2kevm_config: unconfig _c2kevm_config
+
+_c2kevm-nand_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kevm/config.mk;
+	@$(MKCONFIG) -a c2kevm-nand arm arm_cortexa9 c2kevm mindspeed comcerto
+
+c2kevm-nand_config: unconfig _c2kevm-nand_config
+
+_c2kasic_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kasic/config.mk;
+	@$(MKCONFIG) -a c2kasic arm arm_cortexa9 c2kasic mindspeed comcerto
+
+c2kasic_config: unconfig _c2kasic_config
+
+_c2kasic-nand_config:
+	@echo "TEXT_BASE = 0x1000000" >$(obj)board/mindspeed/c2kasic/config.mk;
+	@$(MKCONFIG) -a c2kasic-nand arm arm_cortexa9 c2kasic mindspeed comcerto
+
+c2kasic-nand_config: unconfig _c2kasic-nand_config
+
+
 #========================================================================
 # i386
 #========================================================================
diff --git a/README b/README
index b78ea61..9172e7d 100644
--- a/README
+++ b/README
@@ -1,4 +1,4 @@
-#
+#    
 # (C) Copyright 2000 - 2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
diff --git a/board/mindspeed/asic/Makefile b/board/mindspeed/asic/Makefile
new file mode 100644
index 0000000..606ed43
--- /dev/null
+++ b/board/mindspeed/asic/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/asic/board.c b/board/mindspeed/asic/board.c
new file mode 100644
index 0000000..3566c6b
--- /dev/null
+++ b/board/mindspeed/asic/board.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+static int board_detect(void)
+{
+	u32 gpbt;
+	gpbt = (__le32_to_cpu(*(volatile u32*)(GPIO_BOOTSTRAP_REG)) & 0x1C00) >> 10 ;
+	return(gpbt);
+}
+
+u32 get_ddr_size(void)
+{
+	u32 ddr_size = 0;
+	u32 board_config;
+
+	board_config = board_detect();
+
+	switch (board_config) {
+	case BOARD_CFG_1:
+	case BOARD_CFG_6:
+	default:
+		ddr_size = (256 * 1024 * 1024); /* 256MB */
+		break;
+
+	case BOARD_CFG_2:
+	case BOARD_CFG_3:
+		ddr_size = (1024 * 1024 * 1024); /* 1024MB */
+		break;
+	}
+
+	return ddr_size;
+}
+
+void bsp_init(void)
+{
+	u32 board_config;
+
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	board_config = board_detect();
+	if ((board_config != BOARD_CFG_1) && (board_config != BOARD_CFG_2) && (board_config != BOARD_CFG_3) && (board_config != BOARD_CFG_6)) {
+
+		while(1);
+	}
+
+	icache_enable();
+	SoC_mem_init(board_config);
+//	SoC_nand_init();
+}
+
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif	
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/asic/config.mk b/board/mindspeed/asic/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/asic/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000
diff --git a/board/mindspeed/asic/reset.c b/board/mindspeed/asic/reset.c
new file mode 100644
index 0000000..6766d64
--- /dev/null
+++ b/board/mindspeed/asic/reset.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the lan interface
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the wan interface
+}
+
diff --git a/board/mindspeed/asic/u-boot.lds b/board/mindspeed/asic/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/asic/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}
diff --git a/board/mindspeed/c1kasic/Makefile b/board/mindspeed/c1kasic/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1kasic/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/c1kasic/board.c b/board/mindspeed/c1kasic/board.c
new file mode 100644
index 0000000..f283968
--- /dev/null
+++ b/board/mindspeed/c1kasic/board.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{  
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2;
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = ((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40);
+
+}
+
+static void config_board3(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG3);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG3);
+	arm_write64(DENALI_CTL_35_VAL_CFG3,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG3);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG3);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG3);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG3 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG3 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board4(void)
+{
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG4);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG4);
+	arm_write64(DENALI_CTL_35_VAL_CFG4,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG4);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG4);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG4);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG4 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG4 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void apply_ddr_setting(void)
+{
+	u32 boot_option = __le32_to_cpu(*(volatile u32*)(GPIO_BOOTSTRAP_STATUS_REG)) & 0xC00;
+
+	switch (boot_option) {
+	case 0x000:
+		// rate case 1 ARM pll 650MHz, AHB pll 800, PHY pll 250  => FCLK=650 AHB=200 DDR=325
+		config_board4();
+		break;
+
+	default:
+	case 0x400:
+		// rate case 1 ARM pll 650MHz, AHB pll 750, PHY pll 250  => FCLK=650 AHB=187.5 DDR=375
+		config_board1();
+
+		break;
+
+	case 0x800:
+		// rate case 2 ARM pll 650MHz, AHB pll 800, PHY pll 250  => FCLK=650 AHB=200 DDR=200
+		config_board2();
+		break;
+
+	case 0xC00:
+		// rate case 3 ARM pll 610MHz, AHB pll 744, PHY pll 250  => FCLK=610 AHB=186 DDR=372
+		config_board3();		
+		break;
+	}
+
+#if defined(DDR_TRAINING)
+	/* Do training */
+	start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+// Reset the exp bus before configuring
+	*(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0xFFF);
+// AHB runs at 187.5MHz , and EXP at 31.25MHz
+	*(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+// Optimized settings for the C1kEVM
+	*(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x1A1A401F); 
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x06060A04);
+}
+
+void bsp_init(void)
+{
+	u32 boot_option;
+	int config;
+
+	/* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	// read bootstrap
+	boot_option = __le32_to_cpu(*(volatile u32*)(GPIO_BOOTSTRAP_STATUS_REG)) & 0xC00;
+	
+	switch (boot_option) {
+	case 0x000:
+		config = CFG_CLK_650_187_325;
+		break;
+
+	default:
+	case 0x400:
+		config = CFG_CLK;
+		break;
+
+	case 0x800:
+		config = CFG_CLK_650_200_200;
+		break;
+
+	case 0xC00:
+		config = CFG_CLK_610_186_372;
+		break;
+	}
+
+	SoC_PLL_init(config);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32(1 << 6);
+}
+
+void i2c_hw_init(void)
+{
+	*(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+	/* Call nor_hw_init() only when low level initialization is not done */
+	/* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/c1kasic/config.mk b/board/mindspeed/c1kasic/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1kasic/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000
diff --git a/board/mindspeed/c1kasic/reset.c b/board/mindspeed/c1kasic/reset.c
new file mode 100644
index 0000000..e220846
--- /dev/null
+++ b/board/mindspeed/c1kasic/reset.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the lan interface
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the asic board for the wan interface
+}
+
diff --git a/board/mindspeed/c1kasic/u-boot.lds b/board/mindspeed/c1kasic/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1kasic/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/c1kevm/Makefile b/board/mindspeed/c1kevm/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1kevm/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/c1kevm/board.c b/board/mindspeed/c1kevm/board.c
new file mode 100644
index 0000000..14fa0f4
--- /dev/null
+++ b/board/mindspeed/c1kevm/board.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+	//*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2);
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA); //should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+
+void apply_ddr_setting(void)
+{
+	switch (CFG_CLK) {
+	default:
+	case CFG_CLK_650_187_375:
+	case CFG_CLK_534_178_330:
+	case CFG_CLK_450_165_330:
+	        config_board1();
+		break;
+
+	case CFG_CLK_650_200_200:
+		config_board2();
+		break;
+	}
+	
+	/* training is required for 375MHz only,
+         * but nice to have for 200MHz also */
+#if defined(DDR_TRAINING)
+		/* Do training */
+		start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+/* Reset the exp bus before configuring */
+        *(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+/* Setting size */
+        *(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x7FF);
+/* AHB runs at 200MHz , and EXP at 40MHz */
+        /* *(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x5); */
+/* AHB runs at 187.5MHz , and EXP at 31.25MHz */
+        *(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+/* Optimized settings */
+        *(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+}
+
+void bsp_init(void)
+{
+	/* If MAGIC Number is present, low level initialization is done */
+	if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+		return;
+
+	SoC_PLL_init(CFG_CLK);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32(1 << 6);
+}
+
+void i2c_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+	/* Call nor_hw_init() only when low level initialization is not done */
+	/* If MAGIC Number is present, low level initialization is done */
+	if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+		nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+
+#endif
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/c1kevm/config.mk b/board/mindspeed/c1kevm/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1kevm/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000
diff --git a/board/mindspeed/c1kevm/reset.c b/board/mindspeed/c1kevm/reset.c
new file mode 100644
index 0000000..769cb01
--- /dev/null
+++ b/board/mindspeed/c1kevm/reset.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+}
+
+void reset_emac1_phy(u32 enable)
+{
+}
+
diff --git a/board/mindspeed/c1kevm/u-boot.lds b/board/mindspeed/c1kevm/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1kevm/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/c1km83240/Makefile b/board/mindspeed/c1km83240/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1km83240/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/c1km83240/board.c b/board/mindspeed/c1km83240/board.c
new file mode 100644
index 0000000..b249fbd
--- /dev/null
+++ b/board/mindspeed/c1km83240/board.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+#ifdef CFG_DDR_16BIT
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1 | (1ULL << 24));
+#else
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+#endif
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+#ifdef CFG_DDR_16BIT
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2 | (1ULL << 24));
+#else
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+#endif
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2);
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+
+void apply_ddr_setting(void)
+{		
+	switch (CFG_CLK) {
+	default:
+	case CFG_CLK_650_187_375:
+	case CFG_CLK_534_178_330:
+	case CFG_CLK_450_165_330:
+	        config_board1();
+		break;
+
+	case CFG_CLK_650_200_200:
+		config_board2();
+		break;
+	}
+	
+	/* training is required for 375MHz only,
+         * but nice to have for 200MHz also */
+#if defined(DDR_TRAINING)
+		/* Do training */
+		start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+// Reset the exp bus before configuring
+	*(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+	while (*(volatile u32 *)EX_SWRST_REG) ;
+// Set size
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0xFFF);
+// Force NOR CS to 16 bits bus size (needed for recovery with u-boot_aram in some cases)
+	*(volatile u32 *)EX_CS0_CFG_REG |= (__cpu_to_le32(CSx_CFG_BUS_SZ_16));
+// AHB runs at 187.5MHz , and EXP at 31.25MHz
+	*(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+// Optimized settings
+	*(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done 
+ 	*  in eeprom. Just return*/
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_PLL_init(CFG_CLK);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32(1 << 6);
+}
+
+void i2c_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+void spi_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 27)|(1 << 26)|(1 << 25)|(1 << 24)|(1 << 13)|(1 << 12)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	spi_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+
+#endif
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/c1km83240/config.mk b/board/mindspeed/c1km83240/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1km83240/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000
diff --git a/board/mindspeed/c1km83240/reset.c b/board/mindspeed/c1km83240/reset.c
new file mode 100644
index 0000000..769cb01
--- /dev/null
+++ b/board/mindspeed/c1km83240/reset.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+}
+
+void reset_emac1_phy(u32 enable)
+{
+}
+
diff --git a/board/mindspeed/c1km83240/u-boot.lds b/board/mindspeed/c1km83240/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1km83240/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/c1kmfcn-evm/Makefile b/board/mindspeed/c1kmfcn-evm/Makefile
new file mode 100644
index 0000000..51c4325
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/Makefile
@@ -0,0 +1,63 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/i2c.o ../common/cmd_bootcomcerto.o
+		
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/c1kmfcn-evm/board.c b/board/mindspeed/c1kmfcn-evm/board.c
new file mode 100644
index 0000000..f291582
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/board.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+extern void arm_write64(u64 data,volatile u64 *p);
+
+static void config_board1(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG1);
+	arm_write64(DENALI_CTL_35_VAL_CFG1,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG1);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG1);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG1);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG1 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG1 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+static void config_board2(void)
+{
+  // Configure DDR
+	*(volatile u64*)(DENALI_CTL_00_DATA) = __cpu_to_le64((u64)DENALI_CTL_00_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_01_DATA) = __cpu_to_le64((u64)DENALI_CTL_01_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_03_DATA) = __cpu_to_le64((u64)DENALI_CTL_03_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_04_DATA) = __cpu_to_le64((u64)DENALI_CTL_04_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_05_DATA) = __cpu_to_le64((u64)DENALI_CTL_05_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_06_DATA) = __cpu_to_le64((u64)DENALI_CTL_06_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_07_DATA) = __cpu_to_le64((u64)DENALI_CTL_07_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_08_DATA) = __cpu_to_le64((u64)DENALI_CTL_08_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_09_DATA) = __cpu_to_le64((u64)DENALI_CTL_09_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_10_DATA) = __cpu_to_le64((u64)DENALI_CTL_10_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64((u64)DENALI_CTL_11_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_12_DATA) = __cpu_to_le64((u64)DENALI_CTL_12_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_13_DATA) = __cpu_to_le64((u64)DENALI_CTL_13_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_14_DATA) = __cpu_to_le64((u64)DENALI_CTL_14_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_15_DATA) = __cpu_to_le64((u64)DENALI_CTL_15_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_16_DATA) = __cpu_to_le64((u64)DENALI_CTL_16_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_17_DATA) = __cpu_to_le64((u64)DENALI_CTL_17_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_18_DATA) = __cpu_to_le64((u64)DENALI_CTL_18_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_19_DATA) = __cpu_to_le64((u64)DENALI_CTL_19_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_20_DATA) = __cpu_to_le64((u64)DENALI_CTL_20_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_21_DATA) = __cpu_to_le64((u64)DENALI_CTL_21_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_22_DATA) = __cpu_to_le64((u64)DENALI_CTL_22_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_23_DATA) = __cpu_to_le64((u64)DENALI_CTL_23_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_24_DATA) = __cpu_to_le64((u64)DENALI_CTL_24_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_25_DATA) = __cpu_to_le64((u64)DENALI_CTL_25_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_26_DATA) = __cpu_to_le64((u64)DENALI_CTL_26_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_27_DATA) = __cpu_to_le64((u64)DENALI_CTL_27_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_28_DATA) = __cpu_to_le64((u64)DENALI_CTL_28_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_29_DATA) = __cpu_to_le64((u64)DENALI_CTL_29_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_30_DATA) = __cpu_to_le64((u64)DENALI_CTL_30_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_31_DATA) = __cpu_to_le64((u64)DENALI_CTL_31_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_32_DATA) = __cpu_to_le64((u64)DENALI_CTL_32_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_33_DATA) = __cpu_to_le64((u64)DENALI_CTL_33_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_34_DATA) = __cpu_to_le64((u64)DENALI_CTL_34_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_35_DATA) = __cpu_to_le64((u64)DENALI_CTL_35_VAL_CFG2);
+	arm_write64(DENALI_CTL_35_VAL_CFG2,DENALI_CTL_35_DATA);//should be 64bit write
+	*(volatile u64*)(DENALI_CTL_36_DATA) = __cpu_to_le64((u64)DENALI_CTL_36_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_37_DATA) = __cpu_to_le64((u64)DENALI_CTL_37_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_38_DATA) = __cpu_to_le64((u64)DENALI_CTL_38_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_39_DATA) = __cpu_to_le64((u64)DENALI_CTL_39_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_40_DATA) = __cpu_to_le64((u64)DENALI_CTL_40_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_41_DATA) = __cpu_to_le64((u64)DENALI_CTL_41_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_42_DATA) = __cpu_to_le64((u64)DENALI_CTL_42_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_43_DATA) = __cpu_to_le64((u64)DENALI_CTL_43_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_44_DATA) = __cpu_to_le64((u64)DENALI_CTL_44_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_45_DATA) = __cpu_to_le64((u64)DENALI_CTL_45_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_46_DATA) = __cpu_to_le64((u64)DENALI_CTL_46_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_47_DATA) = __cpu_to_le64((u64)DENALI_CTL_47_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_48_DATA) = __cpu_to_le64((u64)DENALI_CTL_48_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_49_DATA) = __cpu_to_le64((u64)DENALI_CTL_49_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_50_DATA) = __cpu_to_le64((u64)DENALI_CTL_50_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_51_DATA) = __cpu_to_le64((u64)DENALI_CTL_51_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_52_DATA) = __cpu_to_le64((u64)DENALI_CTL_52_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_53_DATA) = __cpu_to_le64((u64)DENALI_CTL_53_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_54_DATA) = __cpu_to_le64((u64)DENALI_CTL_54_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_55_DATA) = __cpu_to_le64((u64)DENALI_CTL_55_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_56_DATA) = __cpu_to_le64((u64)DENALI_CTL_56_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_57_DATA) = __cpu_to_le64((u64)DENALI_CTL_57_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_58_DATA) = __cpu_to_le64((u64)DENALI_CTL_58_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_59_DATA) = __cpu_to_le64((u64)DENALI_CTL_59_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_60_DATA) = __cpu_to_le64((u64)DENALI_CTL_60_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_61_DATA) = __cpu_to_le64((u64)DENALI_CTL_61_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_62_DATA) = __cpu_to_le64((u64)DENALI_CTL_62_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_63_DATA) = __cpu_to_le64((u64)DENALI_CTL_63_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_64_DATA) = __cpu_to_le64((u64)DENALI_CTL_64_VAL_CFG2);
+//	*(volatile u64*)(DENALI_CTL_65_DATA) = __cpu_to_le64((u64)DENALI_CTL_65_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_66_DATA) = __cpu_to_le64((u64)DENALI_CTL_66_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_67_DATA) = __cpu_to_le64((u64)DENALI_CTL_67_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_68_DATA) = __cpu_to_le64((u64)DENALI_CTL_68_VAL_CFG2);
+	*(volatile u64*)(DENALI_CTL_69_DATA) = __cpu_to_le64((u64)DENALI_CTL_69_VAL_CFG2);
+
+	// start DDRC
+	*(volatile u64*)(DENALI_CTL_02_DATA) = __cpu_to_le64((u64)DENALI_CTL_02_VAL_CFG2 | (1LL << 32));
+	//wait int_status[2] (DRAM init complete)
+	while(( __le32_to_cpu(*(volatile u32*)(DENALI_CTL_36_DATA+4)) & 0x4) == 0);
+//	*(volatile u64*)(DENALI_CTL_11_DATA) = __cpu_to_le64(((u64)DENALI_CTL_11_VAL_CFG2 & ~(0x00007F0000000000LL)) | (wr_dqs_shift << 40));
+
+}
+
+
+
+void apply_ddr_setting(void)
+{			
+	switch (CFG_CLK) {
+	default:
+	case CFG_CLK_650_187_375:
+	case CFG_CLK_534_178_330:
+	case CFG_CLK_450_165_330:
+	        config_board1();
+		break;
+
+	case CFG_CLK_650_200_200:
+		config_board2();
+		break;
+	}
+	
+	/* training is required for 375MHz only,
+         * but nice to have for 200MHz also */
+#if defined(DDR_TRAINING)
+		/* Do training */
+		start_training();
+#endif
+}
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+
+static void nor_hw_init(void)
+{
+// Reset the exp bus before configuring
+	*(volatile u32 *)EX_SWRST_REG = __cpu_to_le32(0x1);
+	while (*(volatile u32 *)EX_SWRST_REG) ;
+// Set size
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0xFFF);
+// Force NOR CS to 16 bits bus size (needed for recovery with u-boot_aram in some cases)
+	*(volatile u32 *)EX_CS0_CFG_REG |= (__cpu_to_le32(CSx_CFG_BUS_SZ_16));
+// AHB runs at 187.5MHz , and EXP at 31.25MHz
+	*(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x6);
+// Optimized settings
+	*(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_PLL_init(CFG_CLK);
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	icache_enable();
+
+	//Apply DENALI DDR configuration
+	apply_ddr_setting();
+//	SoC_nand_init();
+}
+
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+        SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 31)|(1 << 30)|(1 << 29)|(1 << 21)|(1 << 20)|(1 << 5)));
+        *(volatile u32 *) GPIO_PIN_SELECT_REG |= __cpu_to_le32((1 << 6));
+}
+
+void i2c_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 19)|(1 << 18)));
+}
+
+void spi_hw_init(void)
+{
+        *(volatile u32 *) GPIO_PIN_SELECT_REG &= __cpu_to_le32(~((1 << 27)|(1 << 26)|(1 << 25)|(1 << 24)|(1 << 13)|(1 << 12)));
+}
+
+int board_init(void)
+{
+	CFG_HZ_CLOCK = HAL_get_ahb_clk();
+
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x10000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+	i2c_hw_init();
+
+	spi_hw_init();
+
+	/* Setup External reset*/
+	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+	udelay(10);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* Enable ARM0 hardware support for non aligned accesses */
+        *(volatile u32 *) GPIO_UP_ALIGN_ACCESS_LOGIC |= __cpu_to_le32(1);
+
+	*(volatile u32 *) USB_PHY_CONF_REG = __cpu_to_le32(0x002D64C2);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 dll_adj0 = 0;
+	u8 dll_adj1 = 0;
+	u8 dll_adj2 = 0;
+	u8 dll_adj3 = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	dll_adj0 = DENALI_DLL_ADJ1_DS0_L;
+	dll_adj1 = DENALI_DLL_ADJ1_DS1_H;
+	dll_adj2 = DENALI_DLL_ADJ1_DS2_L;
+	dll_adj3 = DENALI_DLL_ADJ1_DS3_H;
+	dqs_delay0 = DENALI_WR_DQS_DELAY0;
+	dqs_delay1 = DENALI_WR_DQS_DELAY1;
+	dqs_delay2 = DENALI_WR_DQS_DELAY2;
+	dqs_delay3 = DENALI_WR_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+#else
+	printf("DDR default settings : ");
+#endif
+
+	printf("\nDLL_ADJ(0,1,2,3): 0x%x,0x%x,0x%x,0x%x\n", dll_adj0,dll_adj1,dll_adj2,dll_adj3);
+	printf("WR_DQS:delay0 0x%x, delay1 0x%x, delay2 0x%x, delay3 0x%x\n", dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+
+#endif
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/c1kmfcn-evm/config.mk b/board/mindspeed/c1kmfcn-evm/config.mk
new file mode 100644
index 0000000..bc4e959
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x84000000
diff --git a/board/mindspeed/c1kmfcn-evm/reset.c b/board/mindspeed/c1kmfcn-evm/reset.c
new file mode 100644
index 0000000..769cb01
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/reset.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+}
+
+void reset_emac1_phy(u32 enable)
+{
+}
+
diff --git a/board/mindspeed/c1kmfcn-evm/u-boot.lds b/board/mindspeed/c1kmfcn-evm/u-boot.lds
new file mode 100644
index 0000000..1e8319d
--- /dev/null
+++ b/board/mindspeed/c1kmfcn-evm/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/c2kasic/Makefile b/board/mindspeed/c2kasic/Makefile
new file mode 100644
index 0000000..3b38d14
--- /dev/null
+++ b/board/mindspeed/c2kasic/Makefile
@@ -0,0 +1,62 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o pad_config.o ../common/flash.o i2c.o nand.o
+
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/c2kasic/board.c b/board/mindspeed/c2kasic/board.c
new file mode 100644
index 0000000..968442e
--- /dev/null
+++ b/board/mindspeed/c2kasic/board.c
@@ -0,0 +1,91 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio_c2000.h>
+#include <asm/arch/exp-bus_c2000.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EXP_CS0_SEG_SIZE_VAL  0x7FFF
+
+#define A9_TIMER_LOAD           0x0
+#define A9_TIMER_COUNTER 0x4
+#define A9_TIMER_CNTRL          0x8
+#define A9_TIMER_ENABLE         (1<<0)
+#define A9_TIMER_RELOAD         (1<<1)
+
+#define MAX_TIMER_COUNT 0xffffffff
+
+void comcerto_pad_config();
+
+void nor_hw_init(void)
+{
+	*(volatile u32*) EXP_CS0_SEG_REG = EXP_CS0_SEG_SIZE_VAL;
+	*(volatile u32*) EXP_CS0_TMG1_REG = 0x03034007;
+	*(volatile u32*) EXP_CS0_TMG2_REG = 0x04040502;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(28, GPIO_TYPE_OUTPUT); /* NAND CE */
+        SoC_gpio_cfg(29, GPIO_TYPE_INPUT);  /* NAND BR */
+}
+#endif
+
+
+#if 0
+void a9_timer_init(void)
+{
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_LOAD) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_COUNTER) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_CNTRL) = A9_TIMER_ENABLE | A9_TIMER_RELOAD;
+}
+#endif
+
+void bsp_init(void)
+{
+	int val;
+
+	comcerto_pad_config();
+
+	//DDRC ODT Source Select
+	*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG = ( (1 << 6) | (*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG));
+
+	nor_hw_init();
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	SoC_nand_init();
+#endif
+#if 0
+	a9_timer_init();
+#endif
+}
+
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+
+int board_init(void)
+{
+        /* arch number of Mindspeed Comcerto */
+        gd->bd->bi_arch_number = MACH_TYPE_COMCERTO;
+
+        /* adress of boot parameters */
+        gd->bd->bi_boot_params = 0x100;
+
+
+        gd->bd->bi_dram[0].start = 0x0;
+        gd->bd->bi_dram[0].size = 0x20000000; //512 MB
+
+#if 0
+	c2k_zds_init();
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+
+        return 0;
+}
+
diff --git a/board/mindspeed/c2kasic/config.mk b/board/mindspeed/c2kasic/config.mk
new file mode 100644
index 0000000..99443b1
--- /dev/null
+++ b/board/mindspeed/c2kasic/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x1000000
diff --git a/board/mindspeed/c2kasic/i2c.c b/board/mindspeed/c2kasic/i2c.c
new file mode 100644
index 0000000..db029cb
--- /dev/null
+++ b/board/mindspeed/c2kasic/i2c.c
@@ -0,0 +1,562 @@
+/*
+ * (C) Copyright 2007
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#define COMCERTO_AXI_APB_CFG_BASE       0x90400000
+#define	I2C_BASEADDR	(COMCERTO_AXI_APB_CFG_BASE + 0x09C000)
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+
+#define I2C_ADDR                        (I2C_BASEADDR + 0x00)
+#define I2C_DATA                        (I2C_BASEADDR + 0x04)
+#define I2C_CNTR                        (I2C_BASEADDR + 0x08)
+#define I2C_STAT                        (I2C_BASEADDR + 0x0c)
+#define I2C_CCRFS                       (I2C_BASEADDR + 0x0c)
+#define I2C_XADDR                       (I2C_BASEADDR + 0x10)
+#define I2C_CCRH                        (I2C_BASEADDR + 0x14)
+#define I2C_SOFT_RESET                  (I2C_BASEADDR + 0x1c)
+
+/* CNTR - Control register bits */
+#define I2C_IEN				(1<<7)
+#define I2C_ENAB			(1<<6)
+#define I2C_STA				(1<<5)
+#define I2C_STP				(1<<4)
+#define I2C_IFLG			(1<<3)
+#define I2C_AAK				(1<<2)
+
+/* STAT - Status codes */
+#define I2C_BUS_ERROR			0x00	/* Bus error in master mode only */
+#define I2C_START_TRANSMIT		0x08	/* Start condition transmitted */
+#define I2C_REPEAT_START_TRANSMIT	0x10	/* Repeated Start condition transmited */
+#define I2C_ADDRESS_W_ACK		0x18	/* Address + Write bit transmitted, ACK received */
+#define I2C_ADDRESS_W_NACK		0x20	/* Address + Write bit transmitted, NACK received */
+#define I2C_DATA_TRANSMIT_ACK		0x28	/* Data byte transmitted in master mode , ACK received */
+#define I2C_DATA_TRANSMIT_NACK		0x30	/* Data byte transmitted in master mode , NACK received */
+#define I2C_ARBIT_LOST			0x38	/* Arbitration lost in address or data byte */
+#define I2C_ADDRESS_R_ACK		0x40	/* Address + Read bit transmitted, ACK received  */
+#define I2C_ADDRESS_R_NACK		0x48	/* Address + Read bit transmitted, NACK received  */
+#define I2C_DATA_RECEIVE_ACK		0x50	/* Data byte received in master mode, ACK transmitted  */
+#define I2C_DATA_RECEIVE_NACK		0x58	/* Data byte received in master mode, NACK transmitted*/
+#define I2C_ARBIT_LOST_ADDRESS		0x68	/* Arbitration lost in address  */
+#define I2C_GENERAL_CALL		0x70	/* General Call, ACK transmitted */
+#define I2C_NO_RELEVANT_INFO		0xF8	/* No relevant status information, IFLF=0 */
+
+#define I2C_READ_REG(reg)	        *(volatile u32*)(reg)
+#define I2C_WRITE_REG(reg, val)	        *(volatile u32*)(reg) = val
+#define RESET_REG_BITS(reg, val)        I2C_WRITE_REG(reg, I2C_READ_REG(reg) & ~(val))
+
+#undef	DEBUG_I2C
+//#define DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 1 << n;	/* power = 2^(n) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+        I2C_WRITE_REG(I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	I2C_WRITE_REG(I2C_STAT, (actualM << 3) | actualN);
+	I2C_WRITE_REG(I2C_CNTR, I2C_AAK | I2C_ENAB);
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	status = I2C_READ_REG(I2C_STAT);
+	control = I2C_READ_REG(I2C_CNTR);
+}
+
+static uchar i2c_start (void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+	control = I2C_READ_REG(I2C_CNTR);
+	control |= I2C_STA;	/* generate the I2C_START_BIT */
+	I2C_WRITE_REG(I2C_CNTR, control);
+
+	status = I2C_READ_REG(I2C_STAT);
+
+	count = 0;
+	while ((status & 0xff) != I2C_START_TRANSMIT) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	I2C_WRITE_REG(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+	udelay (I2C_DELAY);
+
+	status = I2C_READ_REG(I2C_STAT);
+	count = 0;
+	while (((status & 0xff) != I2C_ADDRESS_R_ACK) && ((status & 0xff) != I2C_ADDRESS_W_ACK)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY * 5);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_RECEIVE_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return 0;
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		data = I2C_READ_REG(I2C_DATA);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CNTR, I2C_AAK | I2C_IFLG);
+	while ((status & 0xff) != I2C_DATA_RECEIVE_NACK) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY*2);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY*2);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG | I2C_STP);
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP); */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	I2C_WRITE_REG(I2C_CNTR, (0x1 << 4));
+}
+
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	i2c_status = I2C_READ_REG(I2C_STAT);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */
diff --git a/board/mindspeed/c2kasic/nand.c b/board/mindspeed/c2kasic/nand.c
new file mode 100644
index 0000000..fbc6bc4
--- /dev/null
+++ b/board/mindspeed/c2kasic/nand.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <config.h>
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm-arm/arch-comcerto/exp-bus_c2000.h>
+#include <asm-arm/io.h>
+
+
+/** Hardware specific access to NAND control-lines
+ **
+ ** @param[in] mtd       MTD device structure
+ ** @param[in] cmd       NAND command to the controller
+ ** @param[in] ctrl      control address/command latch
+ **
+ **/
+static void comcerto_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+                                                unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                if (ctrl & NAND_NCE)
+			SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+                else
+			SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+        }
+
+        if (cmd == NAND_CMD_NONE) {
+	 return;
+        }
+
+	if (ctrl & NAND_CLE)
+		writeb(cmd, chip->IO_ADDR_W + COMCERTO_NAND_CLE);
+        else if (ctrl & NAND_ALE)
+                writeb(cmd,  chip->IO_ADDR_W + COMCERTO_NAND_ALE);
+        else
+		return;
+}
+
+
+int comcerto_nand_ready(struct mtd_info *mtd)
+{
+	return SoC_gpio_read(SoC_gpio_mask(CFG_NAND_BR_GPIO)) ? 1 : 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	printf("board_nand_init nand->IO_ADDR_R =%x\n", nand->IO_ADDR_R);
+
+	nand->options = 0;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = comcerto_nand_hwcontrol;
+	nand->dev_ready = comcerto_nand_ready;
+	nand->chip_delay = 20;
+}
+#else
+int board_nand_init(struct nand_chip *nand)
+{
+}
+#endif
diff --git a/board/mindspeed/c2kasic/pad_config.c b/board/mindspeed/c2kasic/pad_config.c
new file mode 100644
index 0000000..16d9104
--- /dev/null
+++ b/board/mindspeed/c2kasic/pad_config.c
@@ -0,0 +1,81 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/ddr_c2000.h>
+#include <asm/arch/gpio_c2000.h>
+
+#define CONFIG_GEM_RGMII_2_5V
+//#define CONFIG_GEM_RGMII_3_3V
+#define CONFIG_HFE_OVERDRIVE
+
+/* Initialize pad config according to C2K_ChipDef_spec_010.doc */
+void comcerto_pad_config()
+{
+	u32 val;
+
+	/* HFE configurations */
+
+	/* Memories EMA Config 1 */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~((0x3 << 6)|(0x3 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+
+#if defined(CONFIG_GEM_RGMII_3_3V)
+	/*  Driving Strength of IO Pads */
+	/*In case GEMX operates in RMII or RGMII @3.3V mode then need to adjust
+	 *the driving strength of its IO pad (default value is for 2.5V) */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val &= ~((0x3 << 6)| (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#elif defined(CONFIG_GEM_RGMII_2_5V)
+	/* RGMII Pad Compensation Logic (Tx side only)*/
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CTRL);
+	val &= ~((0x3 << 22) | (0x3 << 26) | (0x3 << 30));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CTRL) = val;
+#else
+#error "Either CONFIG_GEM_RGMII_3_3V or CONFIG_GEM_RGMII_2_5V should be selected"
+#endif
+	/* Slew Rate Control of IO Pads */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#if defined (CONFIG_HFE_OVERDRIVE)
+	/* Memory Margin Bit setting */
+	/* In case HFE block operates in overdrive (1.2V) mode then need to
+	* modify few EMA fields related to HFE memories. The configuration
+	* registers are in GPIO block */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0);
+	val &= ~(0xFFF << 18);
+	val |= (0x38E << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~(0x3F << 19);
+	val |= (0x8 << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+#endif
+
+	/*TODO Add rest of the configurations here*/
+
+}
diff --git a/board/mindspeed/c2kasic/reset.c b/board/mindspeed/c2kasic/reset.c
new file mode 100644
index 0000000..fdd065f
--- /dev/null
+++ b/board/mindspeed/c2kasic/reset.c
@@ -0,0 +1,10 @@
+#include <common.h>
+
+/*
+ *  * Reset the cpu through the reset controller
+ *   */
+void __noreturn reset_cpu (unsigned long addr)
+{
+        while (1);
+}
+
diff --git a/board/mindspeed/c2kasic/u-boot.lds b/board/mindspeed/c2kasic/u-boot.lds
new file mode 100644
index 0000000..83b87a0
--- /dev/null
+++ b/board/mindspeed/c2kasic/u-boot.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm_cortexa9/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
+
diff --git a/board/mindspeed/c2kevm/Makefile b/board/mindspeed/c2kevm/Makefile
new file mode 100644
index 0000000..3b38d14
--- /dev/null
+++ b/board/mindspeed/c2kevm/Makefile
@@ -0,0 +1,62 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o pad_config.o ../common/flash.o i2c.o nand.o
+
+SOBJS	:=
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/c2kevm/board.c b/board/mindspeed/c2kevm/board.c
new file mode 100644
index 0000000..fa16b54
--- /dev/null
+++ b/board/mindspeed/c2kevm/board.c
@@ -0,0 +1,90 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio_c2000.h>
+#include <asm/arch/exp-bus_c2000.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EXP_CS0_SEG_SIZE_VAL  0x7FFF
+
+#define A9_TIMER_LOAD           0x0
+#define A9_TIMER_COUNTER 0x4
+#define A9_TIMER_CNTRL          0x8
+#define A9_TIMER_ENABLE         (1<<0)
+#define A9_TIMER_RELOAD         (1<<1)
+
+#define MAX_TIMER_COUNT 0xffffffff
+
+void comcerto_pad_config();
+
+void nor_hw_init(void)
+{
+	*(volatile u32*) EXP_CS0_SEG_REG = EXP_CS0_SEG_SIZE_VAL;
+	*(volatile u32*) EXP_CS0_TMG1_REG = 0x03034007;
+	*(volatile u32*) EXP_CS0_TMG2_REG = 0x04040502;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_hw_init(void)
+{
+        SoC_gpio_cfg(28, GPIO_TYPE_OUTPUT); /* NAND CE */
+        SoC_gpio_cfg(29, GPIO_TYPE_INPUT);  /* NAND BR */
+}
+#endif
+
+#if 0
+void a9_timer_init(void)
+{
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_LOAD) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_COUNTER) = MAX_TIMER_COUNT;
+	*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_CNTRL) = A9_TIMER_ENABLE | A9_TIMER_RELOAD;
+}
+#endif
+
+void bsp_init(void)
+{
+	int val;
+
+	comcerto_pad_config();
+
+	//DDRC ODT Source Select
+	*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG = ( (1 << 6) | (*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG));
+
+	nor_hw_init();
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	SoC_nand_init();
+#endif
+#if 0
+	a9_timer_init();
+#endif
+}
+
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+
+int board_init(void)
+{
+        /* arch number of Mindspeed Comcerto */
+        gd->bd->bi_arch_number = MACH_TYPE_COMCERTO;
+
+        /* adress of boot parameters */
+        gd->bd->bi_boot_params = 0x100;
+
+
+        gd->bd->bi_dram[0].start = 0x0;
+        gd->bd->bi_dram[0].size = 0x20000000; //512 MB
+
+#if 0
+        c2k_zds_init();
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	nand_hw_init();
+#endif
+
+        return 0;
+}
+
diff --git a/board/mindspeed/c2kevm/config.mk b/board/mindspeed/c2kevm/config.mk
new file mode 100644
index 0000000..99443b1
--- /dev/null
+++ b/board/mindspeed/c2kevm/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x1000000
diff --git a/board/mindspeed/c2kevm/i2c.c b/board/mindspeed/c2kevm/i2c.c
new file mode 100644
index 0000000..db029cb
--- /dev/null
+++ b/board/mindspeed/c2kevm/i2c.c
@@ -0,0 +1,562 @@
+/*
+ * (C) Copyright 2007
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#define COMCERTO_AXI_APB_CFG_BASE       0x90400000
+#define	I2C_BASEADDR	(COMCERTO_AXI_APB_CFG_BASE + 0x09C000)
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+
+#define I2C_ADDR                        (I2C_BASEADDR + 0x00)
+#define I2C_DATA                        (I2C_BASEADDR + 0x04)
+#define I2C_CNTR                        (I2C_BASEADDR + 0x08)
+#define I2C_STAT                        (I2C_BASEADDR + 0x0c)
+#define I2C_CCRFS                       (I2C_BASEADDR + 0x0c)
+#define I2C_XADDR                       (I2C_BASEADDR + 0x10)
+#define I2C_CCRH                        (I2C_BASEADDR + 0x14)
+#define I2C_SOFT_RESET                  (I2C_BASEADDR + 0x1c)
+
+/* CNTR - Control register bits */
+#define I2C_IEN				(1<<7)
+#define I2C_ENAB			(1<<6)
+#define I2C_STA				(1<<5)
+#define I2C_STP				(1<<4)
+#define I2C_IFLG			(1<<3)
+#define I2C_AAK				(1<<2)
+
+/* STAT - Status codes */
+#define I2C_BUS_ERROR			0x00	/* Bus error in master mode only */
+#define I2C_START_TRANSMIT		0x08	/* Start condition transmitted */
+#define I2C_REPEAT_START_TRANSMIT	0x10	/* Repeated Start condition transmited */
+#define I2C_ADDRESS_W_ACK		0x18	/* Address + Write bit transmitted, ACK received */
+#define I2C_ADDRESS_W_NACK		0x20	/* Address + Write bit transmitted, NACK received */
+#define I2C_DATA_TRANSMIT_ACK		0x28	/* Data byte transmitted in master mode , ACK received */
+#define I2C_DATA_TRANSMIT_NACK		0x30	/* Data byte transmitted in master mode , NACK received */
+#define I2C_ARBIT_LOST			0x38	/* Arbitration lost in address or data byte */
+#define I2C_ADDRESS_R_ACK		0x40	/* Address + Read bit transmitted, ACK received  */
+#define I2C_ADDRESS_R_NACK		0x48	/* Address + Read bit transmitted, NACK received  */
+#define I2C_DATA_RECEIVE_ACK		0x50	/* Data byte received in master mode, ACK transmitted  */
+#define I2C_DATA_RECEIVE_NACK		0x58	/* Data byte received in master mode, NACK transmitted*/
+#define I2C_ARBIT_LOST_ADDRESS		0x68	/* Arbitration lost in address  */
+#define I2C_GENERAL_CALL		0x70	/* General Call, ACK transmitted */
+#define I2C_NO_RELEVANT_INFO		0xF8	/* No relevant status information, IFLF=0 */
+
+#define I2C_READ_REG(reg)	        *(volatile u32*)(reg)
+#define I2C_WRITE_REG(reg, val)	        *(volatile u32*)(reg) = val
+#define RESET_REG_BITS(reg, val)        I2C_WRITE_REG(reg, I2C_READ_REG(reg) & ~(val))
+
+#undef	DEBUG_I2C
+//#define DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 1 << n;	/* power = 2^(n) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+        I2C_WRITE_REG(I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	I2C_WRITE_REG(I2C_STAT, (actualM << 3) | actualN);
+	I2C_WRITE_REG(I2C_CNTR, I2C_AAK | I2C_ENAB);
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	status = I2C_READ_REG(I2C_STAT);
+	control = I2C_READ_REG(I2C_CNTR);
+}
+
+static uchar i2c_start (void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+	control = I2C_READ_REG(I2C_CNTR);
+	control |= I2C_STA;	/* generate the I2C_START_BIT */
+	I2C_WRITE_REG(I2C_CNTR, control);
+
+	status = I2C_READ_REG(I2C_STAT);
+
+	count = 0;
+	while ((status & 0xff) != I2C_START_TRANSMIT) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	I2C_WRITE_REG(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+	udelay (I2C_DELAY);
+
+	status = I2C_READ_REG(I2C_STAT);
+	count = 0;
+	while (((status & 0xff) != I2C_ADDRESS_R_ACK) && ((status & 0xff) != I2C_ADDRESS_W_ACK)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY * 5);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_RECEIVE_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return 0;
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		data = I2C_READ_REG(I2C_DATA);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CNTR, I2C_AAK | I2C_IFLG);
+	while ((status & 0xff) != I2C_DATA_RECEIVE_NACK) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY*2);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY*2);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG | I2C_STP);
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP); */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	I2C_WRITE_REG(I2C_CNTR, (0x1 << 4));
+}
+
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	i2c_status = I2C_READ_REG(I2C_STAT);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */
diff --git a/board/mindspeed/c2kevm/nand.c b/board/mindspeed/c2kevm/nand.c
new file mode 100644
index 0000000..fbc6bc4
--- /dev/null
+++ b/board/mindspeed/c2kevm/nand.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <config.h>
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+#include <asm-arm/arch-comcerto/exp-bus_c2000.h>
+#include <asm-arm/io.h>
+
+
+/** Hardware specific access to NAND control-lines
+ **
+ ** @param[in] mtd       MTD device structure
+ ** @param[in] cmd       NAND command to the controller
+ ** @param[in] ctrl      control address/command latch
+ **
+ **/
+static void comcerto_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+                                                unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                if (ctrl & NAND_NCE)
+			SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+                else
+			SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+        }
+
+        if (cmd == NAND_CMD_NONE) {
+	 return;
+        }
+
+	if (ctrl & NAND_CLE)
+		writeb(cmd, chip->IO_ADDR_W + COMCERTO_NAND_CLE);
+        else if (ctrl & NAND_ALE)
+                writeb(cmd,  chip->IO_ADDR_W + COMCERTO_NAND_ALE);
+        else
+		return;
+}
+
+
+int comcerto_nand_ready(struct mtd_info *mtd)
+{
+	return SoC_gpio_read(SoC_gpio_mask(CFG_NAND_BR_GPIO)) ? 1 : 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	printf("board_nand_init nand->IO_ADDR_R =%x\n", nand->IO_ADDR_R);
+
+	nand->options = 0;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = comcerto_nand_hwcontrol;
+	nand->dev_ready = comcerto_nand_ready;
+	nand->chip_delay = 20;
+}
+#else
+int board_nand_init(struct nand_chip *nand)
+{
+}
+#endif
diff --git a/board/mindspeed/c2kevm/pad_config.c b/board/mindspeed/c2kevm/pad_config.c
new file mode 100644
index 0000000..16d9104
--- /dev/null
+++ b/board/mindspeed/c2kevm/pad_config.c
@@ -0,0 +1,81 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clkcore_c2000.h>
+#include <asm/arch/ddr_c2000.h>
+#include <asm/arch/gpio_c2000.h>
+
+#define CONFIG_GEM_RGMII_2_5V
+//#define CONFIG_GEM_RGMII_3_3V
+#define CONFIG_HFE_OVERDRIVE
+
+/* Initialize pad config according to C2K_ChipDef_spec_010.doc */
+void comcerto_pad_config()
+{
+	u32 val;
+
+	/* HFE configurations */
+
+	/* Memories EMA Config 1 */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~((0x3 << 6)|(0x3 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+
+#if defined(CONFIG_GEM_RGMII_3_3V)
+	/*  Driving Strength of IO Pads */
+	/*In case GEMX operates in RMII or RGMII @3.3V mode then need to adjust
+	 *the driving strength of its IO pad (default value is for 2.5V) */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val &= ~((0x3 << 6)| (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val &= ~((0x3 << 6) | (0x3 << 12));
+	val |= ((0x2 << 6) | (0x2 << 12));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#elif defined(CONFIG_GEM_RGMII_2_5V)
+	/* RGMII Pad Compensation Logic (Tx side only)*/
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CTRL);
+	val &= ~((0x3 << 22) | (0x3 << 26) | (0x3 << 30));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CTRL) = val;
+#else
+#error "Either CONFIG_GEM_RGMII_3_3V or CONFIG_GEM_RGMII_2_5V should be selected"
+#endif
+	/* Slew Rate Control of IO Pads */
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG3) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG4) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5);
+	val |= ((0x1 << 11) | (0x1 << 17));
+	*(volatile u32*)(COMCERTO_GPIO_PAD_CONFIG5) = val;
+
+#if defined (CONFIG_HFE_OVERDRIVE)
+	/* Memory Margin Bit setting */
+	/* In case HFE block operates in overdrive (1.2V) mode then need to
+	* modify few EMA fields related to HFE memories. The configuration
+	* registers are in GPIO block */
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0);
+	val &= ~(0xFFF << 18);
+	val |= (0x38E << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG0) = val;
+
+	val = *(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1);
+	val &= ~(0x3F << 19);
+	val |= (0x8 << 18);
+	*(volatile u32*)(COMCERTO_GPIO_MEM_EMA_CONFIG1) = val;
+#endif
+
+	/*TODO Add rest of the configurations here*/
+
+}
diff --git a/board/mindspeed/c2kevm/reset.c b/board/mindspeed/c2kevm/reset.c
new file mode 100644
index 0000000..fdd065f
--- /dev/null
+++ b/board/mindspeed/c2kevm/reset.c
@@ -0,0 +1,10 @@
+#include <common.h>
+
+/*
+ *  * Reset the cpu through the reset controller
+ *   */
+void __noreturn reset_cpu (unsigned long addr)
+{
+        while (1);
+}
+
diff --git a/board/mindspeed/c2kevm/u-boot.lds b/board/mindspeed/c2kevm/u-boot.lds
new file mode 100644
index 0000000..83b87a0
--- /dev/null
+++ b/board/mindspeed/c2kevm/u-boot.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm_cortexa9/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
+
diff --git a/board/mindspeed/common/am29lv040b.c b/board/mindspeed/common/am29lv040b.c
new file mode 100644
index 0000000..4ff2532
--- /dev/null
+++ b/board/mindspeed/common/am29lv040b.c
@@ -0,0 +1,237 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+
+#ifdef CFG_FLASH_AM040_DRIVER
+
+#define AM29LV040B_SIZE		(512 * 1024)
+#define AM29LV040B_SECTOR_SIZE	(64 * 1024)
+
+#define AM29LV040B_SECTORS	(AM29LV040B_SIZE / AM29LV040B_SECTOR_SIZE)
+
+
+/* Am29LV040B Codes */
+#define CMD_RESET		0xF0
+#define CMD_AUTO_SELECT		0x90
+#define CMD_UNLOCK1		0xAA
+#define CMD_UNLOCK2		0x55
+#define CMD_ERASE_SETUP		0x80
+#define CMD_ERASE_CONFIRM	0x30
+#define CMD_PROGRAM		0xA0
+#define CMD_UNLOCK_BYPASS	0x20
+#define CMD_SECTOR_UNLOCK	0x70
+
+#define MEM_FLASH_ADDR1		0x555
+#define MEM_FLASH_ADDR2		0x2AA
+
+#define BIT_ERASE_DONE		0x80
+#define BIT_RDY_MASK		0x80
+
+
+#if defined(CFG_FLASH_PROTECTION)
+int am29lv040b_flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	/* do nothing for now */
+	return ERR_INVAL;
+}
+#endif
+
+int am29lv040b_flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	volatile u8 *base = (u8 *)info->start[0];
+	volatile u8 *addr = base;
+	int flag, erased, prot, sect;
+	ulong start, now, last;
+
+	/* first look for protection bits */
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	erased = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+	base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+	base[MEM_FLASH_ADDR1] = CMD_ERASE_SETUP;
+	base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+	base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr = (u8 *)(info->start[sect]);
+
+			addr[0] = CMD_ERASE_CONFIRM;
+			erased++;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 50us - let's wait 100 us */
+	udelay (100);
+
+	if (erased == 0)
+		goto out;
+
+	printf ("Erasing %d sectors... ", erased);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & BIT_ERASE_DONE) != BIT_ERASE_DONE) {
+		now = get_timer(start);
+		if (now > (erased * CFG_FLASH_ERASE_TOUT)) {
+			printf ("timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+	printf ("ok\n");
+
+out:
+	/* reset to read mode */
+	base[0] = CMD_RESET;
+
+	return ERR_OK;
+}
+
+int am29lv040b_write_buff(flash_info_t *info, uchar *src, ulong dest, ulong cnt)
+{
+	volatile u8 *base = (u8 *)(info->start[0]);
+	volatile u8 *addr = (u8 *)dest;
+	u8 *wbuf = src;
+	ulong last, now, start;
+
+	last = get_timer(0);
+	for (; (cnt > 0); cnt--, addr++, wbuf++) {
+		if (*addr != *wbuf) {
+			base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+			base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+			base[MEM_FLASH_ADDR1] = CMD_PROGRAM;
+			*addr = *wbuf;
+
+			start = get_timer (0);
+			while ((*addr & BIT_RDY_MASK) != (*wbuf & BIT_RDY_MASK)) {
+				now = get_timer(0);
+				if ((now - start) > CFG_FLASH_WRITE_TOUT) {
+					printf ("timeout ");
+					break;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			if (*addr != *wbuf) {
+				printf("write failed, address %08lx -> %x(%x)\n",
+						(unsigned long)addr, *wbuf, *addr);
+
+				base[0] = CMD_RESET;   /* Reset */
+
+				return ERR_TIMOUT;
+			}
+		}
+	}
+
+	printf("ok\n");
+
+	return ERR_OK;
+}
+
+
+static ulong am29lv040b_get_size(flash_info_t *info, ulong base_addr)
+{
+	volatile u8 *base = (u8 *)base_addr;
+	volatile u8 *addr;
+	u8 manuf_id, device_id;
+	int i;
+
+	base[MEM_FLASH_ADDR1] = CMD_UNLOCK1;
+	base[MEM_FLASH_ADDR2] = CMD_UNLOCK2;
+	base[MEM_FLASH_ADDR1] = CMD_AUTO_SELECT;
+
+	manuf_id = base[0];
+	device_id = base[1];
+
+	if (manuf_id != (AMD_MANUFACT & 0xff))
+		return 0;
+
+	if (device_id != AMD_ID_LV040B)
+		return 0;
+
+	printf("found AM29LV040B flash at %08X\n", base_addr);
+
+	info->flash_id = FLASH_MAN_AMD | FLASH_AM040;
+	info->size = AM29LV040B_SIZE;
+	info->sector_count = AM29LV040B_SECTORS;
+
+	memset(info->protect, 0, info->sector_count);
+
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base_addr + i * AM29LV040B_SECTOR_SIZE;
+
+		addr = (u8 *)info->start[i];
+		info->protect[i] = addr[2] & 0x1;
+	}
+
+	/* Reset flash */
+	base[0] = CMD_RESET;
+
+	return info->size;
+}
+
+ulong am29lv040b_flash_init(flash_info_t * info)
+{
+	ulong base_addr[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+	ulong size = 0;
+	int i;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		if (info[i].flash_id == FLASH_UNKNOWN)
+			size += am29lv040b_get_size(&info[i], base_addr[i]);
+	}
+
+	return size;
+}
+#endif
diff --git a/board/mindspeed/common/amlv640u.c b/board/mindspeed/common/amlv640u.c
new file mode 100644
index 0000000..116ac16
--- /dev/null
+++ b/board/mindspeed/common/amlv640u.c
@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+
+#define AMLV640U_SECTOR_SIZE	0x00010000      /* 64 KB sectors */
+#define AMLV640U_SECTORS	(CFG_FLASH_AMLV640U_SIZE / AMLV640U_SECTOR_SIZE)
+
+#define FTIMEOUT		16000000
+
+/* Functions */
+int amlv640u_flash_erase (flash_info_t *info, int s_first, int s_last);
+int amlv640u_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+#if defined(CFG_FLASH_PROTECTION)
+int amlv640u_flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	/* do nothing for now */
+	return ERR_INVAL;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int amlv640u_flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile u16 *base = (u16 *)info->start[0];
+	volatile u16 *addr = base;
+	int flag, prot, sect, erased;
+	ulong start, now, last;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	erased = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x555] = 0xAA;
+	base[0x2AA] = 0x55;
+	base[0x555] = 0x80;
+	base[0x555] = 0xAA;
+	base[0x2AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (u16 *)info->start[sect];
+			addr[0] = 0x30;
+			erased++;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 50us - let's wait 100 us */
+	udelay (100);
+
+	if (erased == 0)
+		goto out;
+
+	printf ("Erasing %d sectors... ", erased);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & 0x80) != 0x80) {
+		now = get_timer(start);
+		if (now > (erased * CFG_FLASH_ERASE_TOUT)) {
+			printf ("timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+	printf ("ok\n");
+
+out:
+	/* reset to read mode */
+	base[0] = 0xF0;
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int amlv640u_write_buff (flash_info_t *info, uchar *src, ulong dest, ulong cnt)
+{
+	volatile u16 *base = (u16 *)(info->start[0]);
+	volatile u16 *addr = (u16 *)dest;
+	u16 *wbuf = (u16 *)src;
+	ulong last, now, start;
+
+	last = get_timer(0);
+	for (cnt >>= 1; (cnt > 0); cnt--, addr++, wbuf++) {
+		if (*addr != *wbuf) {
+			base[0x555] = 0xAA;
+			base[0x2AA] = 0x55;
+			base[0x555] = 0xA0;
+			*addr = *wbuf;
+
+			start = get_timer (0);
+			while ((*addr & 0x80) != (*wbuf & 0x80)) {
+				now = get_timer(0);
+				if ((now - start) > CFG_FLASH_WRITE_TOUT) {
+					printf ("timeout ");
+					break;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > (1 * CFG_HZ)) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			if (*addr != *wbuf) {
+				printf("write failed, address %08lx -> %x(%x)\n",
+						(unsigned long)addr, *wbuf, *addr);
+
+				base[0] = 0xF0;   /* Reset */
+
+				return ERR_TIMOUT;
+			}
+		}
+	}
+
+	printf("ok\n");
+
+	return ERR_OK;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong amlv640u_get_size (flash_info_t *info, ulong base_addr)
+{
+	volatile u16 *base = (u16 *)base_addr;
+	volatile u16 *addr;
+	u16 manuf_id, device_id1, device_id2, device_id3;
+	int i;
+
+        /* Write auto select command: read Manufacturer ID */
+	base[0x555] = 0xAA;
+        base[0x2AA] = 0x55;
+	base[0x555] = 0x90;
+
+	manuf_id = base[0];
+	device_id1 = base[1];
+	device_id2 = base[14];
+	device_id3 = base[15];
+
+	if (manuf_id != (AMD_MANUFACT & 0xffff))
+		return 0;
+
+	if (device_id1 != (AMD_ID_MIRROR & 0xffff) ||
+	    device_id2 != (AMD_ID_LV640U_2 & 0xffff) ||
+	    device_id3 != (AMD_ID_LV640U_3 & 0xffff))
+		return 0;
+
+	printf("found AMLV640U flash at %08X\n", base_addr);
+
+	info->flash_id = FLASH_MAN_AMD | FLASH_AMLV640U;
+	info->size = CFG_FLASH_AMLV640U_SIZE;
+	info->sector_count = AMLV640U_SECTORS;
+
+	memset (info->protect, 0, info->sector_count);
+
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base_addr + i * AMLV640U_SECTOR_SIZE;
+
+		addr = (u16 *)info->start[i];
+		info->protect[i] = addr[2] & 0x1;
+	}
+
+	/* Reset flash */
+	base[0] = 0xF0;
+
+	return info->size;
+}
+
+
+ulong amlv640u_flash_init (flash_info_t * info)
+{
+	ulong base_addr[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+	ulong size = 0;
+	int i;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		if (info[i].flash_id == FLASH_UNKNOWN) {
+			size += amlv640u_get_size(&info[i], base_addr[i]);
+		}
+	}
+
+	return size;
+}
+#endif
diff --git a/board/mindspeed/common/arm1_init.S b/board/mindspeed/common/arm1_init.S
new file mode 100644
index 0000000..5eca981
--- /dev/null
+++ b/board/mindspeed/common/arm1_init.S
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This code runs from ARM1 and setups the CPU before jumping to
+the beginning of the ARM1 image (usually a Linux zImage).
+It must be copied to 0x00000000 before releasing ARM1.
+Linker script variables (in u-boot.lds) are used to find the
+start and end address of this bit of code */
+
+.globl _arm1_start_addr
+.globl _arm1_r0
+.globl _arm1_r1
+.globl _arm1_r2
+
+
+	ldr	r0, _arm1_r0
+	ldr	r1, _arm1_r1
+	ldr	r2, _arm1_r2
+	ldr	pc, _arm1_start_addr
+
+_arm1_start_addr:
+	.word 0x00000000
+
+_arm1_r0:
+	.word 0x00000000
+
+_arm1_r1:
+	.word 0x00000000
+
+_arm1_r2:
+	.word 0x00000000
+
diff --git a/board/mindspeed/common/cmd_bootcomcerto.c b/board/mindspeed/common/cmd_bootcomcerto.c
new file mode 100644
index 0000000..6dc1544
--- /dev/null
+++ b/board/mindspeed/common/cmd_bootcomcerto.c
@@ -0,0 +1,595 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/byteorder.h>
+#include <asm/hardware.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+extern int valid_elf_image (unsigned long addr);
+extern unsigned long load_elf_image (unsigned long addr);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct _AIF_HEADER {
+	u32 BL_DecompressCode;
+	u32 BL_SelfRelocCode;
+	u32 BL_DbgInitZeroInit;
+	u32 EntryPointOffset;
+	u32 ProgramExitInstr;
+	u32 ImageReadOnlySize;
+	u32 ImageReadWriteSize;
+	u32 ImageDebugSize;
+	u32 ImageZeroInitSize;
+	u32 ImageDebugType;
+	u32 ImageBase;
+	u32 WorkSpace;
+	u32 AddressMode;
+	u32 DataBase;
+	u32 FirstFatOffset;
+	u32 Reserved2;
+	u32 DebugInitInstr;
+	u32 ZeroInitCode[15];
+};
+
+struct _FAT_AIF_HEADER {
+	u32 NextFatOffset;
+	u32 LoadAddress;
+	u32 Size;
+	u8 region_name[32];
+};
+
+/**
+ * print_axf_hdr -
+ *
+ */
+static void print_axf_hdr(ulong addr)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+
+	/* we assume that MSP image in memory is not less than the header size (_AIF_HEADER) */
+
+	printf("code_offset=0x80\n");
+	printf("code_base=%lx\n", aif_hdr->ImageBase);
+	printf("data_offset=%lx\n", 0x80 + aif_hdr->ImageReadOnlySize);
+	printf("code_size=%lx\n", aif_hdr->ImageReadOnlySize);
+	printf("data_base=%lx\n", aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize);
+	printf("data_size=%lx\n", aif_hdr->ImageReadWriteSize);
+	printf("zeroinit_base=%lx\n",
+	       aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize);
+	printf("prog_entry=%lx\n", aif_hdr->ImageBase + aif_hdr->EntryPointOffset);
+
+	printf(" \n");
+	printf("AIFHEADER:\n");
+	printf("BL_DecompressCode=%lx\n", aif_hdr->BL_DecompressCode);
+	printf("BL_SelfRelocCode=%lx\n", aif_hdr->BL_SelfRelocCode);
+	printf("BL_DbgInitZeroInit=%lx\n", aif_hdr->BL_DbgInitZeroInit);
+	printf("EntryPointOffset=%lx\n", aif_hdr->EntryPointOffset);
+	printf("ProgramExitInstr=%lx\n", aif_hdr->ProgramExitInstr);
+	printf("ImageReadOnlySize=%lx\n", aif_hdr->ImageReadOnlySize);
+	printf("ImageReadWriteSize=%lx\n", aif_hdr->ImageReadWriteSize);
+	printf("ImageDebugSize=%lx\n", aif_hdr->ImageDebugSize);
+	printf("ImageZeroInitSize=%lx\n", aif_hdr->ImageZeroInitSize);
+	printf("ImageDebugType=%lx\n", aif_hdr->ImageDebugType);
+	printf("ImageBase=%lx\n", aif_hdr->ImageBase);
+	printf("WorkSpace=%lx\n", aif_hdr->WorkSpace);
+	printf("AddressMode=%lx\n", aif_hdr->AddressMode);
+	printf("DataBase=%lx\n", aif_hdr->DataBase);
+	printf("FirstFatOffset=%lx\n", aif_hdr->FirstFatOffset);
+	printf("Reserved2=%lx\n", aif_hdr->Reserved2);
+	printf("DebugInitInstr=%lx\n", aif_hdr->DebugInitInstr);
+	printf("ZeroInitCode[0]=%lx\n", aif_hdr->ZeroInitCode[0]);
+}
+
+/**
+ * check_load_addr -
+ *
+ */
+static int check_load_addr(ulong addr)
+{
+	if ((addr > MSP_BOTTOM_MEMORY_RESERVED_SIZE) &&
+#if defined(CONFIG_COMCERTO_530)
+	    ((addr < ERAM_BASEADDR) || (addr >= IRAM_BASEADDR + IRAM_SIZE))
+#elif defined(CONFIG_COMCERTO_515) || defined(CONFIG_COMCERTO_800)
+	    ((addr < ERAM_BASEADDR) || (addr >= ARAM_BASEADDR + ARAM_SIZE))
+#elif defined(CONFIG_COMCERTO_900)
+	    ((addr < ERAM_BASEADDR) || (addr >= CRAM_BASEADDR + CRAM_SIZE))
+#else
+	    (1)
+#endif
+	)
+		return -1;
+
+	return 0;
+}
+
+/**
+ * load_axf_zero -
+ *
+ */
+static int load_axf_zero(ulong addr)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+	u32 m_data_base;
+	u32 bytes_to_load;
+
+	if (aif_hdr->DataBase)
+		m_data_base = aif_hdr->DataBase;
+	else
+		m_data_base = aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize;
+
+	m_data_base = m_data_base + aif_hdr->ImageReadWriteSize;
+	bytes_to_load = aif_hdr->ImageZeroInitSize / 2;
+
+	if (check_load_addr(m_data_base + bytes_to_load) < 0) {
+		printf("data section load address %x outside range\n", m_data_base + bytes_to_load);
+		goto err;
+	}
+
+	memset((void *)m_data_base, 0, bytes_to_load);
+
+	return 0;
+
+err:
+	return -1;
+}
+
+/**
+ * load_axf_fat -
+ */
+static int load_axf_fat(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+	struct _FAT_AIF_HEADER *fat_aif_hdr;
+	u32 fat_offset;
+
+	fat_offset = aif_hdr->FirstFatOffset;
+
+	while (fat_offset > 0) {
+
+		if ((fat_offset + sizeof(struct _FAT_AIF_HEADER)) > size) {
+			printf("fat section header at %x outside image %x\n", fat_offset, size);
+			goto err;
+		}
+
+		fat_aif_hdr = (struct _FAT_AIF_HEADER *)(addr + fat_offset);
+
+		if ((fat_offset + sizeof(struct _FAT_AIF_HEADER) + fat_aif_hdr->Size) > size) {
+			printf("fat section size %x bigger than image size %x\n", fat_offset + sizeof(struct _FAT_AIF_HEADER) + fat_aif_hdr->Size, size);
+			goto err;
+		}
+
+		if (check_load_addr(fat_aif_hdr->LoadAddress + fat_aif_hdr->Size) < 0) {
+			printf("fat section load address %x outside range\n", fat_aif_hdr->LoadAddress + fat_aif_hdr->Size);
+			goto err;
+		}
+
+		memcpy((void *)fat_aif_hdr->LoadAddress,
+		       (void *)(addr + fat_offset + sizeof(struct _FAT_AIF_HEADER)), fat_aif_hdr->Size);
+
+		fat_offset = fat_aif_hdr->NextFatOffset;
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+
+/**
+ * load_axf_data -
+ */
+static int load_axf_data(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+
+	if (aif_hdr->ImageReadWriteSize) {
+
+		if ((sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize) > size) {
+			printf("data section size %x bigger than image size %x\n", aif_hdr->ImageReadWriteSize, size);
+			goto err;
+		}
+
+		if (aif_hdr->DataBase == 0) {
+			if (check_load_addr(aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize) < 0) {
+				printf("data section load address %x outside range\n", aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize + aif_hdr->ImageReadWriteSize);
+				goto err;
+			}
+
+			memcpy((void *)(aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize),
+			       (void *)(addr + sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize),
+			       aif_hdr->ImageReadWriteSize);
+		} else {
+			if (check_load_addr(aif_hdr->DataBase + aif_hdr->ImageReadWriteSize) < 0) {
+				printf("data section load address %x outside range\n", aif_hdr->DataBase + aif_hdr->ImageReadWriteSize);
+				goto err;
+			}
+
+			memcpy((void *)aif_hdr->DataBase,
+			       (void *)(addr + sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize),
+			       aif_hdr->ImageReadWriteSize);
+		}
+
+	} else {
+		printf("data section size 0\n");
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+
+/**
+ * load_axf_code -
+ *
+ */
+static int load_axf_code(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *)(addr);
+
+	if (aif_hdr->ImageReadOnlySize) {
+		if ((sizeof(struct _AIF_HEADER) + aif_hdr->ImageReadOnlySize) > size) {
+			printf("code section size %x bigger than image size %x\n", aif_hdr->ImageReadOnlySize, size);
+			goto err;
+		}
+
+		if (check_load_addr(aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize) < 0) {
+			printf("code section load address %x outside range\n", aif_hdr->ImageBase + aif_hdr->ImageReadOnlySize);
+			goto err;
+		}
+
+		memcpy((void *)aif_hdr->ImageBase, (void *)(addr + sizeof(struct _AIF_HEADER)), aif_hdr->ImageReadOnlySize);
+	} else {
+		printf("code section size 0\n");
+	}
+
+	return 0;
+
+err:
+	return -1;
+}
+
+/**
+ * load_axf_image -
+ *
+ */
+static ulong load_axf_image(ulong addr, ulong size)
+{
+	struct _AIF_HEADER *aif_hdr = (struct _AIF_HEADER *) addr;
+
+	printf ("## Downloading image at %08lx ...\n", addr);
+
+	if (sizeof (struct _AIF_HEADER) > size) {
+		printf("AXF header %x bigger than image size %x\n", sizeof (struct _AIF_HEADER), size);
+		goto err;
+	}
+
+	print_axf_hdr(addr);
+
+	if (load_axf_code(addr, size)) {
+		printf("download code failed\n");
+		goto err;
+	}
+
+	if (load_axf_data(addr, size)) {
+		printf("download data failed\n");
+		goto err;
+	}
+
+	if (load_axf_fat(addr, size)) {
+		printf("download fat failed\n");
+		goto err;
+	}
+
+	if (load_axf_zero(addr)) {
+		printf("zero init failed\n");
+		goto err;
+	}
+
+//	printf ("## Booting image at %08lx ...\n", aif_hdr->ImageBase + aif_hdr->EntryPointOffset);
+
+	return aif_hdr->ImageBase + aif_hdr->EntryPointOffset;
+
+err:
+	return (ulong)-1;
+}
+
+/**
+ * strtoul_with_check - reads unsigned long hex value from string with checking
+ *
+ * ARGUMENTS:
+ *    str:    the string to scan value from
+ *    pvalue: pointer to the value location (if be NULL just checking will be
+ *            performed)
+ *    label:  optinal label for the typical error message (if NULL no message
+ *            will be printed)
+ *
+ * RETURNS:
+ *    0 success, -1 otherwise
+ */
+static int strtoul_with_check(const char *str, ulong *pvalue, const char *label)
+{
+	ulong value;
+	char *end = NULL;
+
+	value = simple_strtoul(str, &end, 16);
+	if (str == end || *end != 0) {
+		if (label)
+			printf("Invalid %s given, please provide correct hex value.\n", label);
+		return -1;
+	}
+
+	if (pvalue)
+		*pvalue = value;
+
+	return 0;
+}
+
+/**
+ * do_loadmsp - loads MSP image, it may be in either ELF or AXF format. If image
+ *    is successfully loaded, stores MSP entry in "msp_start_addr" env. variable.
+ *
+ * ARGUMENTS:
+ *    standard set of U-Boot command arguments, user must pass image address
+ *    and size (all in hex).
+ *
+ * RETURNS:
+ *    0 - success, -1 otherwise
+ */
+static int do_loadmsp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr, size;
+	char buf[32];
+
+	if (argc < 3) {
+		goto err;
+	}
+
+	if (strtoul_with_check(argv[1], &addr, "image address"))
+		goto err;
+
+	if (strtoul_with_check(argv[2], &size, "image size"))
+		goto err;
+
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+	if (valid_elf_image(addr))
+		addr = load_elf_image(addr);
+	else
+		addr = load_axf_image(addr, size);
+#else
+	addr = load_axf_image(addr, size);
+#endif
+
+	if (addr == (ulong)-1)
+		goto err;
+
+	/* store MSP start addr in environment (we will need it do_bootcomcerto) */
+	sprintf(buf, "%lx", addr);
+	setenv("msp_start_addr", buf);
+	printf("image loaded at %lx\n", addr);
+	return 0;
+
+err:
+	printf("error loading image\n");
+	return -1;
+}
+
+
+U_BOOT_CMD(
+	loadmsp,  3, 0, do_loadmsp,
+	"loadmsp - load MSP image (AXF or ELF format) and save MSP start address\n",
+	"address size\n"
+	"    - 'address' (hex) points to MSP image location.\n"
+	"      'size' (hex) specifies image size.\n"
+	"      See also 'bootcomcerto' command.\n"
+);
+
+
+extern char __arm1_init_start, __arm1_init_end;
+extern u32 _arm1_start_addr, _arm1_r0, _arm1_r1, _arm1_r2;
+
+/**
+ * set_arm1_init - copies ARM1 startup code to reset location and sets CSP
+ *    image startup address
+ *
+ * ARGUMENTS:
+ *    addr:     CSP entry point
+ *    r0,r1,r2: values for the corresponding ARM1 registers
+ */
+static void set_arm1_init(ulong addr, ulong r0, ulong r1, ulong r2)
+{
+	_arm1_start_addr = addr;
+	_arm1_r0 = r0;
+	_arm1_r1 = r1;
+	_arm1_r2 = r2;
+
+	printf("Copying ARM1 startup code from %08x, start address %08x\n",
+		&__arm1_init_start, addr);
+
+	memcpy(0, &__arm1_init_start, &__arm1_init_end - &__arm1_init_start);
+}
+
+#if !defined(CONFIG_COMCERTO_1000) && !defined(CONFIG_COMCERTO_100)
+/* This code only applies to Carrier/Access platforms, where ARM0 is running
+ * the MSP and ARM1 the CSP
+ */
+extern image_header_t header;
+extern void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+		     ulong addr, ulong *len_ptr, int verify);
+
+#define BOOT_ETH_BASE_ADDRESS	(IRAM_BASEADDR + 0x1250)
+#define MAGIC_NUM_ADDRESS_IRAM	(BOOT_ETH_BASE_ADDRESS + 0x10)
+#define FLAGS_ADDRESS_IRAM	(BOOT_ETH_BASE_ADDRESS + 0x14)
+#define M1_ADDRESS_IRAM		(BOOT_ETH_BASE_ADDRESS + 0x18)
+#define M5_ADDRESS_IRAM		(BOOT_ETH_BASE_ADDRESS + 0x24)
+
+#define MAGIC_NUM_IRAM		0x98765432
+#define ETHADDR_IRAM_MASK	(1 << 0)
+
+static void msp_boot_eth_hdr_setup(bd_t * bd)
+{
+	struct eth_hdr {
+		u8 hostmac[6];
+		u8 mspmac[6];
+		u8 padding;
+		u16 packet_type;
+	} __attribute__((packed)) *hdr;
+
+	/* The MSP expects an ethernet header at this IRAM address */
+	/* at boot time */
+
+	hdr = (struct eth_hdr *)(BOOT_ETH_BASE_ADDRESS + 1);
+	
+	hdr->hostmac[0] = 0x00;
+	hdr->hostmac[1] = 0x11;
+	hdr->hostmac[2] = 0x22;
+	hdr->hostmac[3] = 0x33;
+	hdr->hostmac[4] = 0x44;
+	hdr->hostmac[5] = 0x55;
+
+	hdr->mspmac[0] = 0x00;
+	hdr->mspmac[1] = 0x1a;
+	hdr->mspmac[2] = 0x1b;
+	hdr->mspmac[3] = 0x1c;
+	hdr->mspmac[4] = 0x1d;
+	hdr->mspmac[5] = 0x1e;
+
+	hdr->packet_type = 0x889b;
+}
+
+static void msp_iram_flags_setup(bd_t * bd)
+{
+	int i;
+	ulong reg;
+	char *s, *e;
+	char tmp[64];
+				
+	/* pass miscellaneous params to the MSP via IRAM
+	   Since these are not passed by all boot loaders use a magic number
+	   to tell the MSP that if parameters are present */
+	*(u32 *)MAGIC_NUM_ADDRESS_IRAM = MAGIC_NUM_IRAM;
+
+	/* the next word is a bit-map that tells the MSP which parameters are present,
+           this allows params to be added and different versions of bootloader and MSP
+           to inter-operate */
+
+	/* always have ethaddr; even if user does not specify it (which is an error), we have a default */
+	*(u32 *)FLAGS_ADDRESS_IRAM = ETHADDR_IRAM_MASK;
+
+	/* write ethernet address */
+	memcpy((u8 *)M1_ADDRESS_IRAM, bd->bi_enetaddr, 6);
+
+	i = getenv_r ("eth1addr", tmp, sizeof (tmp));
+	s = (i > 0) ? tmp : NULL;
+	for (reg = 0; reg < 6; ++reg) {
+		*(u8 *) (M5_ADDRESS_IRAM + reg) = s ? simple_strtoul (s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e + 1 : e;
+	}
+}
+
+/**
+ * do_bootcomcerto - checks if MSP image was loaded, then loads CSP image which
+ *    may be in either binary or ELF format and boots MSP.
+ *
+ * ARGUMENTS:
+ *    standard set of U-Boot command arguments, user must pass CSP image address
+ *
+ * RETURNS:
+ *    doesn't return on success
+ */
+static int do_bootcomcerto (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong csp_start_addr, msp_start_addr;
+	int csp_is_elf = 0;
+	bd_t *bd = gd->bd;
+	char *str;
+
+	if (argc < 2) {
+		return -1;
+	}
+
+	str = getenv("msp_start_addr");
+	if (!str) {
+		printf("MSP start address is not set, see 'loadmsp' command\n");
+		return -1;
+	}
+
+	if (strtoul_with_check(str, &msp_start_addr, NULL)) {
+		printf("Invalid MSP address, aborting\n");
+		return -1;
+	}
+
+	if (strtoul_with_check(argv[1], &csp_start_addr, "image address"))
+		return -1;
+
+#if (CONFIG_COMMANDS & CFG_CMD_ELF)
+	if ((csp_is_elf = valid_elf_image(csp_start_addr)) != 0)
+		csp_start_addr = load_elf_image(csp_start_addr);
+#endif
+
+	/* Setup MSP boot args in IRAM */
+	msp_boot_eth_hdr_setup(bd);
+	msp_iram_flags_setup(bd);
+
+	if (csp_is_elf == 0) {
+		/* CSP image is in binary format, assuming Linux */
+
+		/* Fake header to keep do_bootm_linux() happy
+		 * No ramdisk support for now
+		 */
+		header.ih_ep = htonl(msp_start_addr);	/* This is actually the MSP entry point */
+		header.ih_type = IH_TYPE_KERNEL;
+#if 0
+		hdr->ih_magic = htonl(IH_MAGIC);
+		hdr->ih_hcrc = htonl(0);	/* FIXME calculate the checksum */
+		hdr->ih_size = htonl(0);
+#endif
+
+		set_arm1_init(csp_start_addr, 0, bd->bi_arch_number, bd->bi_boot_params);
+		do_bootm_linux(cmdtp, 0, argc, argv, 0, NULL, 0);
+	}
+	else {
+		/* CSP image is in ELF, assuming VxWorks */
+
+		set_arm1_init(csp_start_addr, (unsigned int)getenv("bootargs"), 0, 0);
+		((void(*)(void))msp_start_addr)();
+	}
+
+	printf("Unexpected return to bootloader!\n");
+
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	bootcomcerto, 2, 0, do_bootcomcerto,
+	"bootcomcerto - load CSP image (binary or ELF format) and start Comcerto device\n",
+	"address\n"
+	"    - 'address'(hex) points to CSP image location.\n"
+	"      See also 'loadmsp' command, which must be run before this one.\n"
+);
+#endif
diff --git a/board/mindspeed/common/flash.c b/board/mindspeed/common/flash.c
new file mode 100644
index 0000000..dd35783
--- /dev/null
+++ b/board/mindspeed/common/flash.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#ifdef CFG_FLASH_CFI_DRIVER
+
+#define FLASH_MAN_CFI		0x01000000
+
+#ifdef CFG_FLASH_PROTECTION
+extern int cfi_flash_real_protect(flash_info_t *info, long sector, int prot);
+#endif
+
+extern int cfi_flash_erase(flash_info_t * info, int s_first, int s_last);
+extern int cfi_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+extern void cfi_flash_print_info(flash_info_t *info);
+extern unsigned long cfi_flash_init(void);
+#endif
+
+
+#ifdef CFG_FLASH_AM040_DRIVER
+#ifdef CFG_FLASH_PROTECTION
+int am29lv040b_flash_real_protect(flash_info_t *info, long sector, int prot);
+#endif
+int am29lv040b_flash_erase(flash_info_t * info, int s_first, int s_last);
+int am29lv040b_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+ulong am29lv040b_flash_init(flash_info_t * info);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+int amlv640u_flash_erase (flash_info_t *info, int s_first, int s_last);
+int amlv640u_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+ulong amlv640u_flash_init(flash_info_t * info);
+#endif
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	if ((s_first < 0) || (s_first > s_last) || (s_last >= info->sector_count)) {
+		return ERR_INVAL;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI)
+		return cfi_flash_erase(info, s_first, s_last);
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+		return am29lv040b_flash_erase(info, s_first, s_last);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV640U)
+		return amlv640u_flash_erase(info, s_first, s_last);
+#endif
+
+	return ERR_UNKNOWN_FLASH_TYPE;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	if ((sector < 0) || (sector >= info->sector_count)) {
+		return ERR_INVAL;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI)
+		return cfi_flash_real_protect(info, sector, prot);
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+		return am29lv040b_flash_real_protect(info, sector, prot);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV640U)
+		return amlv640u_flash_real_protect(info, sector, prot);
+#endif
+
+	return ERR_UNKNOWN_FLASH_TYPE;
+}
+#endif
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI)
+		return cfi_write_buff(info, src, addr, cnt);
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+		return am29lv040b_write_buff(info, src, addr, cnt);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV640U)
+		return amlv640u_write_buff(info, src, addr, cnt);
+#endif
+
+	return ERR_UNKNOWN_FLASH_TYPE;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	if (info->flash_id == FLASH_MAN_CFI) {
+		cfi_flash_print_info(info);
+		return;
+	}
+#endif
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+
+	/* Add other supported flash vendors here */
+
+	default:
+		printf ("Unknown Vendor ");
+		return;
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4Mbit, uniform sector size)\n");
+		break;
+
+	case FLASH_AMLV640U:
+		printf ("AM29LV640ML/S29GL064M (64Mbit, uniform sector size)\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		return;
+		break;
+	}
+
+	if ((info->size >> 20) > 0)
+		printf ("  Size: %ld MiB in %d Sectors\n", info->size >> 20, info->sector_count);
+	else
+		printf ("  Size: %ld KiB in %d Sectors\n", info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+
+	printf ("\n");
+
+	return;
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i;
+
+	printf("Comcerto Flash Subsystem Initialization\n");
+
+	/* Init: no Flashes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+#ifdef CFG_FLASH_CFI_DRIVER
+	/* CFI compatible flash detection */
+	/* must be done first */
+	size += cfi_flash_init();
+#endif
+
+#ifdef CFG_FLASH_AM040_DRIVER
+	size += am29lv040b_flash_init(flash_info);
+#endif
+
+#ifdef CFG_FLASH_AMLV640U_DRIVER
+	size += amlv640u_flash_init(flash_info);
+#endif
+
+	return size;
+}
diff --git a/board/mindspeed/common/i2c.c b/board/mindspeed/common/i2c.c
new file mode 100644
index 0000000..37ac1ed
--- /dev/null
+++ b/board/mindspeed/common/i2c.c
@@ -0,0 +1,559 @@
+/*
+ * (C) Copyright 2007
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+
+#define I2C_ADDR                        (I2C_BASEADDR + 0x00)
+#define I2C_DATA                        (I2C_BASEADDR + 0x04)
+#define I2C_CNTR                        (I2C_BASEADDR + 0x08)
+#define I2C_STAT                        (I2C_BASEADDR + 0x0c)
+#define I2C_CCRFS                       (I2C_BASEADDR + 0x0c)
+#define I2C_XADDR                       (I2C_BASEADDR + 0x10)
+#define I2C_CCRH                        (I2C_BASEADDR + 0x14)
+#define I2C_SOFT_RESET                  (I2C_BASEADDR + 0x1c)
+
+/* CNTR - Control register bits */
+#define I2C_IEN				(1<<7)
+#define I2C_ENAB			(1<<6)
+#define I2C_STA				(1<<5)
+#define I2C_STP				(1<<4)
+#define I2C_IFLG			(1<<3)
+#define I2C_AAK				(1<<2)
+
+/* STAT - Status codes */
+#define I2C_BUS_ERROR			0x00	/* Bus error in master mode only */
+#define I2C_START_TRANSMIT		0x08	/* Start condition transmitted */
+#define I2C_REPEAT_START_TRANSMIT	0x10	/* Repeated Start condition transmited */
+#define I2C_ADDRESS_W_ACK		0x18	/* Address + Write bit transmitted, ACK received */
+#define I2C_ADDRESS_W_NACK		0x20	/* Address + Write bit transmitted, NACK received */
+#define I2C_DATA_TRANSMIT_ACK		0x28	/* Data byte transmitted in master mode , ACK received */
+#define I2C_DATA_TRANSMIT_NACK		0x30	/* Data byte transmitted in master mode , NACK received */
+#define I2C_ARBIT_LOST			0x38	/* Arbitration lost in address or data byte */
+#define I2C_ADDRESS_R_ACK		0x40	/* Address + Read bit transmitted, ACK received  */
+#define I2C_ADDRESS_R_NACK		0x48	/* Address + Read bit transmitted, NACK received  */
+#define I2C_DATA_RECEIVE_ACK		0x50	/* Data byte received in master mode, ACK transmitted  */
+#define I2C_DATA_RECEIVE_NACK		0x58	/* Data byte received in master mode, NACK transmitted*/
+#define I2C_ARBIT_LOST_ADDRESS		0x68	/* Arbitration lost in address  */
+#define I2C_GENERAL_CALL		0x70	/* General Call, ACK transmitted */
+#define I2C_NO_RELEVANT_INFO		0xF8	/* No relevant status information, IFLF=0 */
+
+#define I2C_READ_REG(reg)	        *(volatile u32*)(reg)
+#define I2C_WRITE_REG(reg, val)	        *(volatile u32*)(reg) = val
+#define RESET_REG_BITS(reg, val)        I2C_WRITE_REG(reg, I2C_READ_REG(reg) & ~(val))
+
+#undef	DEBUG_I2C
+//#define DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 1 << n;	/* power = 2^(n) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+        I2C_WRITE_REG(I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	I2C_WRITE_REG(I2C_STAT, (actualM << 3) | actualN);
+	I2C_WRITE_REG(I2C_CNTR, I2C_AAK | I2C_ENAB);
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	status = I2C_READ_REG(I2C_STAT);
+	control = I2C_READ_REG(I2C_CNTR);
+}
+
+static uchar i2c_start (void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+	control = I2C_READ_REG(I2C_CNTR);
+	control |= I2C_STA;	/* generate the I2C_START_BIT */
+	I2C_WRITE_REG(I2C_CNTR, control);
+
+	status = I2C_READ_REG(I2C_STAT);
+
+	count = 0;
+	while ((status & 0xff) != I2C_START_TRANSMIT) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	I2C_WRITE_REG(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+	udelay (I2C_DELAY);
+
+	status = I2C_READ_REG(I2C_STAT);
+	count = 0;
+	while (((status & 0xff) != I2C_ADDRESS_R_ACK) && ((status & 0xff) != I2C_ADDRESS_W_ACK)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY * 5);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_RECEIVE_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return 0;
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		data = I2C_READ_REG(I2C_DATA);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CNTR, I2C_AAK | I2C_IFLG);
+	while ((status & 0xff) != I2C_DATA_RECEIVE_NACK) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+			return (status);
+		}
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+	}
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		I2C_WRITE_REG(I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CNTR, I2C_IFLG);
+
+		udelay (I2C_DELAY*2);
+
+		status = I2C_READ_REG(I2C_STAT);
+		count++;
+		while ((status & 0xff) != I2C_DATA_TRANSMIT_ACK) {
+			udelay (I2C_DELAY*2);
+			if (count > 20) {
+				I2C_WRITE_REG(I2C_CNTR, I2C_STP);	/*stop */
+				return (status);
+			}
+			status = I2C_READ_REG(I2C_STAT);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG | I2C_STP);
+	I2C_WRITE_REG(I2C_CNTR, I2C_STP); */
+	/* set the interrupt bit in the control register */
+	I2C_WRITE_REG(I2C_CNTR, I2C_IFLG);
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	I2C_WRITE_REG(I2C_CNTR, (0x1 << 4));
+}
+
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	i2c_status = I2C_READ_REG(I2C_STAT);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */
diff --git a/board/mindspeed/common/nand.c b/board/mindspeed/common/nand.c
new file mode 100644
index 0000000..655b66d
--- /dev/null
+++ b/board/mindspeed/common/nand.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <config.h>
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/hardware.h>
+#include <asm/arch/bsp.h>
+
+/* 
+ *	hardware specific access to control-lines
+*/
+void comcerto_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CLE_GPIO));
+		break;
+
+	case NAND_CTL_CLRCLE:
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CLE_GPIO));
+		break;
+
+	case NAND_CTL_SETALE:
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_ALE_GPIO));
+		break;
+
+	case NAND_CTL_CLRALE:
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_ALE_GPIO));
+		break;
+
+	case NAND_CTL_SETNCE:
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+		break;
+
+	case NAND_CTL_CLRNCE:
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NAND_CE_GPIO));
+		break;
+	}
+}
+
+int comcerto_nand_ready(struct mtd_info *mtd)
+{
+	return SoC_gpio_read(SoC_gpio_mask(CFG_NAND_BR_GPIO)) ? 1 : 0;
+}
+
+void board_nand_init(struct nand_chip *nand)
+{
+	printf("board_nand_init nand->IO_ADDR_R =%x\n", nand->IO_ADDR_R);
+
+	nand->options = 0;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->hwcontrol = comcerto_nand_hwcontrol;
+	nand->dev_ready = comcerto_nand_ready;
+	nand->chip_delay = 20;
+}
+#else
+void board_nand_init(struct nand_chip *nand)
+{
+
+}
+#endif
diff --git a/board/mindspeed/common/norboot.S b/board/mindspeed/common/norboot.S
new file mode 100644
index 0000000..010dba5
--- /dev/null
+++ b/board/mindspeed/common/norboot.S
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This code is used to setup the boot CS to 16bit so that 
+the U-boot image can be read from NOR flash. It is compiled into
+a special section (and format) using the u-boot.lds linker script and
+u16_to_u8.c application */
+
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+.globl _start
+_start:
+	adr	r0, iram_code_start
+	ldr	r1, iram_addr
+	adr	r2, iram_code_end
+
+copy:
+	ldmia	r0!, {r3-r6}	/* copy from source address [r0]    */
+	stmia	r1!, {r3-r6}	/* copy to   target address [r1]    */
+	cmp	r0, r2		/* until source end address [r2]    */
+	ble	copy
+
+	/* Calculate return address, offset is multiplied by 2 */
+	adr     r0, _start
+	add     r1, r2, r2
+	sub     lr, r1, r0
+
+	/* Jump to internal RAM */
+	ldr	pc, iram_addr
+
+iram_addr:
+	.word	IRAM_BASEADDR
+
+
+	/* This codes runs from internal RAM and
+	   sets the boot chip select */
+iram_code_start:
+	ldr	r0, cs_reg
+	ldr	r1, cs_val
+	strh	r1, [r0]
+
+	/* Jump back to flash, now running in 16 bit */
+	mov	pc, lr
+
+cs_reg:
+	.word	SDC0_CSBOOT_CFG
+
+cs_val:
+	.word	0x081E
+
+iram_code_end:
diff --git a/board/mindspeed/common/u16_to_u8.c b/board/mindspeed/common/u16_to_u8.c
new file mode 100644
index 0000000..1552fab
--- /dev/null
+++ b/board/mindspeed/common/u16_to_u8.c
@@ -0,0 +1,46 @@
+#include <stdio.h>
+
+int main(int argc, char *argv[])
+{
+	FILE *fpi, *fpo;
+	unsigned char byte;
+	unsigned short word;
+	unsigned int nop; 
+	int count;
+
+	if (argc < 3)
+		goto err0;
+
+	fpi = fopen(argv[1], "r");
+	if (!fpi)
+		goto err0;
+
+	fpo = fopen(argv[2], "w");
+	if (!fpo)
+		goto err1;
+
+	count = 0;
+	while(fread(&byte, 1, sizeof(unsigned char), fpi) == 1) {
+		word = byte << 8 | byte;
+
+		fwrite(&word, 1, sizeof(unsigned short), fpo);
+		count++;
+	}
+
+	/* Align to the next 32bytes boundary with nops */
+	nop = 0xe1a00000;
+	count = (32 - (count * 2) % 32) / 4;
+	while (count--)
+		fwrite(&nop, 1, sizeof(unsigned int), fpo);
+
+	fclose(fpi);
+	fclose(fpo);
+
+	return 0;
+
+err1:
+	fclose(fpi);
+
+err0:
+	return 1;
+}
diff --git a/board/mindspeed/ferouter/Makefile b/board/mindspeed/ferouter/Makefile
new file mode 100644
index 0000000..606ed43
--- /dev/null
+++ b/board/mindspeed/ferouter/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/ferouter/board.c b/board/mindspeed/ferouter/board.c
new file mode 100644
index 0000000..73fe1f6
--- /dev/null
+++ b/board/mindspeed/ferouter/board.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(CFG_NOR_FLASH_A22_GPIO));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(CFG_NOR_FLASH_A22_GPIO));
+	}
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set NOR_FLASH_A22_GPIO as output */
+	SoC_gpio_cfg(CFG_NOR_FLASH_A22_GPIO, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(CFG_NOR_FLASH_A22_GPIO));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x7FF;
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x3FF;
+#endif
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+	SoC_mem_init(7);
+//	SoC_nand_init();
+}
+
+int board_init(void)
+{
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* issue external reset via GPIO17 for 100 msec*/
+	*(volatile u32*) (GPIO_OE_REG) |= 0x20000;
+	*(volatile u32*)(GPIO_OUTPUT_REG) = 0x20000;	
+	udelay(10);
+	*(volatile u32*)(GPIO_OUTPUT_REG) = 0x0;	
+	udelay(100*1000);
+	*(volatile u32*)(GPIO_OUTPUT_REG) = 0x20000;	
+	udelay(100*1000);
+
+	/* enable SPI interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | GPIO_IOCTRL_SPI; 		// enable SPI bus
+   	   *(volatile u32 *)GPIO_LOCK_REG = 0x55555555; 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+
+       *(volatile u32 *)(GPIO_BASEADDR+0x34) = *(volatile u32 *)(GPIO_BASEADDR+0x34) | 0x4;	// set TDM FSync as output
+       *(volatile u32 *)CLKCORE_TDM_CLK_CNTRL = 0x832d70d7;		// set TDM clock freq to 2MHz
+       *(volatile u32 *)CLKCORE_FSYNC_CNTRL = 0x20FF0001;		// set FSync freq to 8KHz
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif	
+
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/ferouter/config.mk b/board/mindspeed/ferouter/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/ferouter/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000
diff --git a/board/mindspeed/ferouter/reset.c b/board/mindspeed/ferouter/reset.c
new file mode 100644
index 0000000..f7ab9b8
--- /dev/null
+++ b/board/mindspeed/ferouter/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the router board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+}
+
diff --git a/board/mindspeed/ferouter/u-boot.lds b/board/mindspeed/ferouter/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/ferouter/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}
diff --git a/board/mindspeed/ipots48-515/Makefile b/board/mindspeed/ipots48-515/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/ipots48-515/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/ipots48-515/board.c b/board/mindspeed/ipots48-515/board.c
new file mode 100644
index 0000000..29d2694
--- /dev/null
+++ b/board/mindspeed/ipots48-515/board.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+
+	SoC_mem_divider_cfg(0x80000000, BELLOW_MEM_SDC1);
+	SoC_high_mem_cfg(SDR_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/ipots48-515/config.mk b/board/mindspeed/ipots48-515/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/ipots48-515/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/ipots48-515/u-boot.lds b/board/mindspeed/ipots48-515/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/ipots48-515/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/ipots48-800/Makefile b/board/mindspeed/ipots48-800/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/ipots48-800/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/ipots48-800/board.c b/board/mindspeed/ipots48-800/board.c
new file mode 100644
index 0000000..29d2694
--- /dev/null
+++ b/board/mindspeed/ipots48-800/board.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+
+	SoC_mem_divider_cfg(0x80000000, BELLOW_MEM_SDC1);
+	SoC_high_mem_cfg(SDR_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if(CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/ipots48-800/config.mk b/board/mindspeed/ipots48-800/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/ipots48-800/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/ipots48-800/u-boot.lds b/board/mindspeed/ipots48-800/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/ipots48-800/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/malindi/Makefile b/board/mindspeed/malindi/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/malindi/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/malindi/board.c b/board/mindspeed/malindi/board.c
new file mode 100644
index 0000000..7f361e9
--- /dev/null
+++ b/board/mindspeed/malindi/board.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP1, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 4 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+//	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/malindi/config.mk b/board/mindspeed/malindi/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/malindi/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/malindi/u-boot.lds b/board/mindspeed/malindi/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/malindi/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/megamombasa515_256M/Makefile b/board/mindspeed/megamombasa515_256M/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/megamombasa515_256M/board.c b/board/mindspeed/megamombasa515_256M/board.c
new file mode 100644
index 0000000..099acd1
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/board.c
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	cfg.baseaddr = PHYS_SDRAM;
+	cfg.size = PHYS_SDRAM_SIZE;
+
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	cfg.baseaddr = PHYS_SDRAM1;
+	cfg.size = PHYS_SDRAM1_SIZE;
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+	
+	SoC_mem_divider_cfg(PHYS_SDRAM1, BELLOW_MEM_SDC0);
+	SoC_high_mem_cfg(EXP_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM1;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM1_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/megamombasa515_256M/config.mk b/board/mindspeed/megamombasa515_256M/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/megamombasa515_256M/u-boot.lds b/board/mindspeed/megamombasa515_256M/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/megamombasa515_256M/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/megamombasa515_sdc1/Makefile b/board/mindspeed/megamombasa515_sdc1/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/megamombasa515_sdc1/board.c b/board/mindspeed/megamombasa515_sdc1/board.c
new file mode 100644
index 0000000..9e85130
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/board.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0411,
+		.pwroncnt = 0x3415,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+
+	SoC_cs_cfg(SDR_CSSD0, CS_ENABLE, &cfg);
+	
+	SoC_mem_divider_cfg(0x80000000, BELLOW_MEM_SDC1);
+	SoC_high_mem_cfg(SDR_CSSD0);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/megamombasa515_sdc1/config.mk b/board/mindspeed/megamombasa515_sdc1/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/megamombasa515_sdc1/u-boot.lds b/board/mindspeed/megamombasa515_sdc1/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/megamombasa515_sdc1/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/moca/Makefile b/board/mindspeed/moca/Makefile
new file mode 100644
index 0000000..d45c7ad
--- /dev/null
+++ b/board/mindspeed/moca/Makefile
@@ -0,0 +1,61 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o ../common/i2c.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/moca/board.c b/board/mindspeed/moca/board.c
new file mode 100644
index 0000000..4ed75e1
--- /dev/null
+++ b/board/mindspeed/moca/board.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(5));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(5));
+	}
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(5, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(5));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x7FF;
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = 0x3FF;
+#endif
+
+        /* adjust EXP bus configuration registers */
+        *(volatile u32 *)EX_CLOCK_DIV_REG = 0x5;
+        *(volatile u32 *)EX_CS0_TMG1_REG = 0x03034007;
+        *(volatile u32 *)EX_CS0_TMG2_REG = 0x04040502;
+
+}
+
+void bsp_init(void)
+{
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+	SoC_mem_init(BOARD_CFG_MOCA);
+}
+
+int board_init(void)
+{
+        u32 i, led_mask;
+    
+	nor_hw_init();
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+        /* force WAN Select (GPIO6) to GigE PHY, not MoCA */
+	SoC_gpio_cfg(6, GPIO_TYPE_OUTPUT);
+	SoC_gpio_set_1(SoC_gpio_mask(6));
+        
+        /* configure MoCA PHY reset lines for as GPIO outputs, hold in reset */
+       	SoC_gpio_cfg(22, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(23, GPIO_TYPE_OUTPUT);
+        SoC_gpio_set_0(SoC_gpio_mask(23) | SoC_gpio_mask(22));
+        
+        /* force external reset via GPIO17 for 100msec */
+       	SoC_gpio_cfg(17, GPIO_TYPE_OUTPUT);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+        udelay(10);
+	SoC_gpio_set_0(SoC_gpio_mask(17));
+        udelay(100*1000);
+	SoC_gpio_set_1(SoC_gpio_mask(17));
+        udelay(100*1000);
+
+	/* enable I2C interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | GPIO_IOCTRL_I2C; 		// enable I2C bus
+   	   *(volatile u32 *)GPIO_LOCK_REG = 0x55555555; 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+
+        /* configure WPS and config-reset buttons as inputs */
+        SoC_gpio_cfg(3, GPIO_TYPE_INPUT);
+        SoC_gpio_cfg(4, GPIO_TYPE_INPUT);
+
+        /* configure GPIO-driven LEDs as outputs, flash them */
+       	SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(15, GPIO_TYPE_OUTPUT);
+       	SoC_gpio_cfg(16, GPIO_TYPE_OUTPUT);
+        led_mask = SoC_gpio_mask(29) | SoC_gpio_mask(30) | SoC_gpio_mask(15) | SoC_gpio_mask(16);
+        for (i = 0; i < 10; i++) {
+            if (i%2) {
+                SoC_gpio_set_1(led_mask);
+            } else {
+                SoC_gpio_set_0(led_mask);
+            }
+            udelay(100*1000);
+        }
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+	printf("DDR Training : ");
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/moca/config.mk b/board/mindspeed/moca/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/moca/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000
diff --git a/board/mindspeed/moca/reset.c b/board/mindspeed/moca/reset.c
new file mode 100644
index 0000000..6192830
--- /dev/null
+++ b/board/mindspeed/moca/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the packet-iad board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+}
+
diff --git a/board/mindspeed/moca/u-boot.lds b/board/mindspeed/moca/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/moca/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}
diff --git a/board/mindspeed/nairobi/Makefile b/board/mindspeed/nairobi/Makefile
new file mode 100644
index 0000000..403d839
--- /dev/null
+++ b/board/mindspeed/nairobi/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/nairobi/board.c b/board/mindspeed/nairobi/board.c
new file mode 100644
index 0000000..07aa8b8
--- /dev/null
+++ b/board/mindspeed/nairobi/board.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_ASYNC, 372000000, CFG_HZ_CLOCK);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/nairobi/config.mk b/board/mindspeed/nairobi/config.mk
new file mode 100644
index 0000000..242dab7
--- /dev/null
+++ b/board/mindspeed/nairobi/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x00100000
diff --git a/board/mindspeed/nairobi/u-boot.lds b/board/mindspeed/nairobi/u-boot.lds
new file mode 100644
index 0000000..db5a529
--- /dev/null
+++ b/board/mindspeed/nairobi/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/packet-iad/Makefile b/board/mindspeed/packet-iad/Makefile
new file mode 100644
index 0000000..0145d72
--- /dev/null
+++ b/board/mindspeed/packet-iad/Makefile
@@ -0,0 +1,62 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o ../common/i2c.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/packet-iad/board.c b/board/mindspeed/packet-iad/board.c
new file mode 100644
index 0000000..4b02884
--- /dev/null
+++ b/board/mindspeed/packet-iad/board.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(5));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(5));
+	}
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+static void nand_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(5, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(5));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x7FF);
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x3FF);
+#endif
+
+        /* adjust EXP bus configuration registers */
+        *(volatile u32 *)EX_CLOCK_DIV_REG = __cpu_to_le32(0x5);
+        *(volatile u32 *)EX_CS0_TMG1_REG = __cpu_to_le32(0x03034007);
+        *(volatile u32 *)EX_CS0_TMG2_REG = __cpu_to_le32(0x04040502);
+
+        return;
+}
+
+void bsp_init(void)
+{
+       /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+#if defined(CONFIG_COMCERTO_50)
+	SoC_mem_init(9);
+#else
+	SoC_mem_init(4);
+#endif
+//	SoC_nand_init();
+}
+
+int board_init(void)
+{
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+       nand_hw_init();
+#endif
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* enable I2C interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG | __cpu_to_le32(GPIO_IOCTRL_I2C); 		// enable I2C bus
+   	   *(volatile u32 *)GPIO_LOCK_REG = __cpu_to_le32(0x55555555); 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/packet-iad/config.mk b/board/mindspeed/packet-iad/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/packet-iad/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000
diff --git a/board/mindspeed/packet-iad/reset.c b/board/mindspeed/packet-iad/reset.c
new file mode 100644
index 0000000..6192830
--- /dev/null
+++ b/board/mindspeed/packet-iad/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the packet-iad board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= BIT17;
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= BIT17;
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= ~BIT17;
+		}
+	}
+}
+
diff --git a/board/mindspeed/packet-iad/u-boot.lds b/board/mindspeed/packet-iad/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/packet-iad/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}
diff --git a/board/mindspeed/router/Makefile b/board/mindspeed/router/Makefile
new file mode 100644
index 0000000..d2a8bd5
--- /dev/null
+++ b/board/mindspeed/router/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o ../common/i2c.o
+SOBJS	:= 
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+OBJS    := $(addprefix $(obj),$(COBJS))
+SOBJS   := $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mindspeed/router/board.c b/board/mindspeed/router/board.c
new file mode 100644
index 0000000..8483d6e
--- /dev/null
+++ b/board/mindspeed/router/board.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2006 Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+void board_map(flash_info_t *info, unsigned long addr)
+{
+	if ((addr >= (PHYS_FLASH1 + 0x800000)) && (addr < (PHYS_FLASH1 + 0x1000000))) {
+		SoC_gpio_set_0(SoC_gpio_mask(5));
+	} else {
+		SoC_gpio_set_1(SoC_gpio_mask(5));
+	}
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+static void nand_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(29, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(30, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(31, GPIO_TYPE_OUTPUT);
+
+}
+#endif
+
+u32 get_ddr_size(void)
+{
+	return PHYS_SDRAM_SIZE;
+}
+
+static void nor_hw_init(void)
+{
+	/* set GPIO5 as output */
+	SoC_gpio_cfg(5, GPIO_TYPE_OUTPUT);
+
+	/* Select upper 8MiB of flash device */
+	SoC_gpio_set_1(SoC_gpio_mask(5));
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x7FF);
+#else
+	*(volatile u32 *)EX_CS0_SEG_REG = __cpu_to_le32(0x3FF);
+#endif
+}
+
+void bsp_init(void)
+{
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  == COMCERTO_PART_MAGIC)
+                return;
+
+	SoC_Check_Device();
+	SoC_APB_setup();
+	SoC_AHB_setup();
+	SoC_ARAM_setup();
+
+	SoC_PLL_init();
+
+	icache_enable();
+#if defined(CONFIG_COMCERTO_50)
+	SoC_mem_init(10); /* for C50 */
+#else
+	SoC_mem_init(5); /* for C100 */
+#endif
+//	SoC_nand_init();
+}
+
+int board_init(void)
+{
+        /* Call nor_hw_init() only when low level initialization is not done */
+        /* If MAGIC Number is present, low level initialization is done */
+        if(__le64_to_cpu(*(u64*)(ARAM_BASEADDR+0x8000))  != COMCERTO_PART_MAGIC)
+                nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+       nand_hw_init();
+#endif
+
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+	/* enable I2C interface */
+	while (1)
+	{
+	   u32 temp;
+   	   temp = *(volatile u32 *)GPIO_IOCTRL_REG |  __cpu_to_le32(GPIO_IOCTRL_I2C); 		// enable I2C bus
+   	   *(volatile u32 *)GPIO_LOCK_REG =  __cpu_to_le32(0x55555555); 			// remove lock
+   	   *(volatile u32 *)GPIO_IOCTRL_REG = temp;				// write to ctrl reg
+   	   if (*(volatile u32 *)GPIO_IOCTRL_REG == temp)
+		   break;
+	}
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ddr_size();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef DDR_TRAINING_DBG
+	u8 wr_dqs = 0; 
+	u8 dqs_out = 0;
+	u8 dqs_delay0 = 0;
+	u8 dqs_delay1 = 0;
+	u8 dqs_delay2 = 0;
+	u8 dqs_delay3 = 0;
+#endif
+
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+
+#ifdef DDR_TRAINING_DBG
+	wr_dqs = DENALI_WR_DQS; 
+	dqs_out = DENALI_DQS_OUT;
+	dqs_delay0 = DENALI_DQS_DELAY0;
+	dqs_delay1 = DENALI_DQS_DELAY1;
+	dqs_delay2 = DENALI_DQS_DELAY2;
+	dqs_delay3 = DENALI_DQS_DELAY3;
+#ifdef DDR_TRAINING
+	printf("DDR Training : ");
+
+#ifdef NEW_DDR_TRAINING
+	printf("(NEW): ");
+#endif
+
+#else
+	printf("DDR default settings : ");
+#endif	
+	printf("wr_dqs 0x%x dqs_out 0x%x delay0 0x%x delay1 0x%x delay2 0x%x delay3 0x%x\n", wr_dqs,dqs_out,dqs_delay0,dqs_delay1,dqs_delay2,dqs_delay3);
+#endif
+	return 0;
+}
+
+#endif
diff --git a/board/mindspeed/router/config.mk b/board/mindspeed/router/config.mk
new file mode 100644
index 0000000..99d1ed8
--- /dev/null
+++ b/board/mindspeed/router/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x80100000
diff --git a/board/mindspeed/router/reset.c b/board/mindspeed/router/reset.c
new file mode 100644
index 0000000..be5d916
--- /dev/null
+++ b/board/mindspeed/router/reset.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/bits.h>
+
+#define WAN_PHY_BIT	0
+#define LAN_PHY_BIT	1
+static u8 wanlan_reset=0;
+
+/*
+	On the router board, the lan and the wan phy are taken out of reset by the same GPIO pin (17)
+*/
+
+void reset_emac0_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=LAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= __cpu_to_le32(BIT17);
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~LAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= __cpu_to_le32(~BIT17);
+		}
+	}
+
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	if(enable)
+	{	//want to take the phy out of reset
+		wanlan_reset|=WAN_PHY_BIT;
+		*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+		*(volatile u32*)(GPIO_OUTPUT_REG) |= __cpu_to_le32(BIT17);
+
+	}
+	else
+	{
+		//want to put the phy in reset
+		wanlan_reset&=~WAN_PHY_BIT;
+		if(wanlan_reset==0)
+		{
+			*(volatile u32*) (GPIO_OE_REG) |= __cpu_to_le32(BIT17);
+			*(volatile u32*)(GPIO_OUTPUT_REG) &= __cpu_to_le32(~BIT17);
+		}
+	}
+}
+
diff --git a/board/mindspeed/router/u-boot.lds b/board/mindspeed/router/u-boot.lds
new file mode 100644
index 0000000..895ea2a
--- /dev/null
+++ b/board/mindspeed/router/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright Mindspeed Technologies Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+	. = 0x0a000000;
+	__training_data_start = .;
+
+}
diff --git a/board/mindspeed/supermombasa910/Makefile b/board/mindspeed/supermombasa910/Makefile
new file mode 100644
index 0000000..f99546f
--- /dev/null
+++ b/board/mindspeed/supermombasa910/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o mii.o reset.o ../common/am29lv040b.o ../common/flash.o ../common/nand.o
+SOBJS	:=  
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all:	$(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS) 
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/supermombasa910/board.c b/board/mindspeed/supermombasa910/board.c
new file mode 100644
index 0000000..567644f
--- /dev/null
+++ b/board/mindspeed/supermombasa910/board.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void SoC_PLL_init(void);
+extern void SoC_mem_init(void);
+//extern void SoC_mem_init(int controller, int base, int length);
+extern void SoC_flash_init(void);
+extern void SoC_nand_init(void);
+
+void bsp_init(void)
+{
+	SoC_Check_Device();
+
+	SoC_PLL_init();
+	//SoC_mem_init(0, PHYS_SDRAM, /*PHYS_SDRAM_SIZE/0x100000*/128);
+	SoC_mem_init();
+	SoC_flash_init();
+	SoC_nand_init();
+	
+	icache_enable();
+}
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+  printf("Reserve MSP memory\n");
+  gd->bd->bi_dram[0].start += (u32)MSP_MEMORY_RESERVED_SIZE;
+  gd->bd->bi_dram[0].size -= (u32)MSP_MEMORY_RESERVED_SIZE;
+  return 0;
+}
+#endif
diff --git a/board/mindspeed/supermombasa910/config.mk b/board/mindspeed/supermombasa910/config.mk
new file mode 100644
index 0000000..242dab7
--- /dev/null
+++ b/board/mindspeed/supermombasa910/config.mk
@@ -0,0 +1,11 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+# We load ourself to internal RAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+#
+
+# XXX TEXT_BASE = 0x20012000
+TEXT_BASE = 0x00100000
diff --git a/board/mindspeed/supermombasa910/mii.c b/board/mindspeed/supermombasa910/mii.c
new file mode 100644
index 0000000..c94a99d
--- /dev/null
+++ b/board/mindspeed/supermombasa910/mii.c
@@ -0,0 +1,29 @@
+#include <common.h>
+
+#if defined(CONFIG_MII) && (CONFIG_COMMANDS & CFG_CMD_MII)
+extern u16 MDIO_Handle_Read(u16 preamble_sup, u16 phy_addr, u16 reg_addr);
+extern u16 MDIO_Handle_Write(u16 preamble_sup, u16 phy_addr, u16 reg_addr, u16 md_data);
+
+int  comcerto_miiphy_read(char *devname, unsigned char addr,
+		unsigned char reg, unsigned short * value)
+{
+	*value = MDIO_Handle_Read(0, 0, reg);
+	return 0;
+}
+
+int  comcerto_miiphy_write(char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value)
+{
+	MDIO_Handle_Write(0, 0, reg, value);
+	return 0;
+}
+
+#endif	/* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+int comcerto_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) && (CONFIG_COMMANDS & CFG_CMD_MII)
+	miiphy_register("Comcerto phy", comcerto_miiphy_read, comcerto_miiphy_write);
+#endif
+	return 0;
+}
diff --git a/board/mindspeed/supermombasa910/reset.c b/board/mindspeed/supermombasa910/reset.c
new file mode 100644
index 0000000..f3de85c
--- /dev/null
+++ b/board/mindspeed/supermombasa910/reset.c
@@ -0,0 +1,15 @@
+#include <common.h>
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+void reset_emac0_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the supermombassa910 board for the lan interface
+}
+
+void reset_emac1_phy(u32 enable)
+{
+	//nothing to do. There is no reset on the supermombassa910 board for the wan interface
+}
+
+
diff --git a/board/mindspeed/supermombasa910/u-boot.lds b/board/mindspeed/supermombasa910/u-boot.lds
new file mode 100644
index 0000000..1f86607
--- /dev/null
+++ b/board/mindspeed/supermombasa910/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/tsavo515/Makefile b/board/mindspeed/tsavo515/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/tsavo515/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/tsavo515/board.c b/board/mindspeed/tsavo515/board.c
new file mode 100644
index 0000000..69a1810
--- /dev/null
+++ b/board/mindspeed/tsavo515/board.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/tsavo515/config.mk b/board/mindspeed/tsavo515/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/tsavo515/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/tsavo515/u-boot.lds b/board/mindspeed/tsavo515/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/tsavo515/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/tsavo515_nor/Makefile b/board/mindspeed/tsavo515_nor/Makefile
new file mode 100644
index 0000000..b3fc1e5
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/Makefile
@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB) ../common/u16_to_u8.bin norboot8.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+norboot8.o: ../common/norboot.o
+	$(LD) -Ttext 0x11000000 $< -o norboot.o
+	$(OBJCOPY) -O binary norboot.o norboot16.bin
+	../common/u16_to_u8.bin norboot16.bin norboot8.bin
+	$(OBJCOPY) -Barm -I binary -O elf32-littlearm norboot8.bin $@
+	$(RM) norboot16.bin norboot8.bin
+
+../common/u16_to_u8.bin: ../common/u16_to_u8.c
+	$(HOSTCC) -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) norboot8.o ../common/u16_to_u8.bin ../common/norboot.o
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/tsavo515_nor/board.c b/board/mindspeed/tsavo515_nor/board.c
new file mode 100644
index 0000000..0cdcc18
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/board.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+	spi_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/tsavo515_nor/config.mk b/board/mindspeed/tsavo515_nor/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/tsavo515_nor/u-boot.lds b/board/mindspeed/tsavo515_nor/u-boot.lds
new file mode 100644
index 0000000..4d51168
--- /dev/null
+++ b/board/mindspeed/tsavo515_nor/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		board/mindspeed/tsavo515_nor/norboot8.o (.data)
+
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/tsavo530/Makefile b/board/mindspeed/tsavo530/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/tsavo530/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/tsavo530/board.c b/board/mindspeed/tsavo530/board.c
new file mode 100644
index 0000000..9bb02a3
--- /dev/null
+++ b/board/mindspeed/tsavo530/board.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 250000000, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 4 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_CS_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/tsavo530/config.mk b/board/mindspeed/tsavo530/config.mk
new file mode 100644
index 0000000..091ad4c
--- /dev/null
+++ b/board/mindspeed/tsavo530/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x03E00000	# 62MiB
diff --git a/board/mindspeed/tsavo530/u-boot.lds b/board/mindspeed/tsavo530/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/tsavo530/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/tsavo530_nor/Makefile b/board/mindspeed/tsavo530_nor/Makefile
new file mode 100644
index 0000000..b3fc1e5
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/Makefile
@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB) ../common/u16_to_u8.bin norboot8.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+norboot8.o: ../common/norboot.o
+	$(LD) -Ttext 0x11000000 $< -o norboot.o
+	$(OBJCOPY) -O binary norboot.o norboot16.bin
+	../common/u16_to_u8.bin norboot16.bin norboot8.bin
+	$(OBJCOPY) -Barm -I binary -O elf32-littlearm norboot8.bin $@
+	$(RM) norboot16.bin norboot8.bin
+
+../common/u16_to_u8.bin: ../common/u16_to_u8.c
+	$(HOSTCC) -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS) norboot8.o ../common/u16_to_u8.bin ../common/norboot.o
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/tsavo530_nor/board.c b/board/mindspeed/tsavo530_nor/board.c
new file mode 100644
index 0000000..4a09a41
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/board.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 250000000, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void nand_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+}
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	nand_hw_init();
+	nor_hw_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/tsavo530_nor/config.mk b/board/mindspeed/tsavo530_nor/config.mk
new file mode 100644
index 0000000..091ad4c
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x03E00000	# 62MiB
diff --git a/board/mindspeed/tsavo530_nor/u-boot.lds b/board/mindspeed/tsavo530_nor/u-boot.lds
new file mode 100644
index 0000000..8b1e558
--- /dev/null
+++ b/board/mindspeed/tsavo530_nor/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		board/mindspeed/tsavo530_nor/norboot8.o (.data)
+
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/udev515/Makefile b/board/mindspeed/udev515/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/udev515/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/udev515/board.c b/board/mindspeed/udev515/board.c
new file mode 100644
index 0000000..a7ed641
--- /dev/null
+++ b/board/mindspeed/udev515/board.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void exp_csp0_init (void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+}
+
+
+static void nand_hw_init(void)
+{
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+extern spi_chipsel_type spi_chipsel[];
+
+static void ethswitch_init(void)
+{
+	uchar dout[3];
+	int rc;
+
+	*(volatile u8 *)CPLD_RESET_CTRL &= ~ESWITCH_OUT_OF_RESET;	/* reset ESwitch */
+	*(volatile u8 *)CPLD_INTMASK |= ESWITCH_IRQMASK;
+	*(volatile u8 *)CPLD_RESET_CTRL |= ESWITCH_OUT_OF_RESET;	/* Take ESwitch out of reset */
+
+	spi_hw_init();
+
+	/* initialize the SPI write buffer */
+	dout[0] = 0x02;				/* Eswitch write command */
+	dout[1] = 1;				/* address */
+	dout[2] = 1;				/* value */
+	
+	rc = spi_xfer(spi_chipsel[2], 24, dout, NULL);
+	if (rc)
+		printf(" ethswitch_init: can't initialize the SPI bus \n", rc);
+}
+
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* CPLD, FPGA and NAND chip select */
+	exp_csp0_init();
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+	ethswitch_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/udev515/config.mk b/board/mindspeed/udev515/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/udev515/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/udev515/u-boot.lds b/board/mindspeed/udev515/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/udev515/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mindspeed/udev800/Makefile b/board/mindspeed/udev800/Makefile
new file mode 100644
index 0000000..c668fa4
--- /dev/null
+++ b/board/mindspeed/udev800/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2006
+# Mindspeed Technologies, Inc. <www.mindspeed.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= board.o ../common/flash.o ../common/am29lv040b.o ../common/amlv640u.o\
+		../common/nand.o ../common/cmd_bootcomcerto.o
+SOBJS	:= ../common/arm1_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+
+HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
+
+all: $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+board.o: board.c
+	$(CC) $(CFLAGS) -fpic -c -o $@ $<
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mindspeed/udev800/board.c b/board/mindspeed/udev800/board.c
new file mode 100644
index 0000000..a7ed641
--- /dev/null
+++ b/board/mindspeed/udev800/board.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/mach-types.h>
+#include <asm/arch/bsp.h>
+#include <asm/hardware.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) || defined(CONFIG_SPI)
+extern void spi_hw_init(void);
+#endif
+
+/* Initialize SDRAM, ARM and bus CLOCK and instruction cache */
+void bsp_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SDRAM,
+		.baseaddr = PHYS_SDRAM,
+		.size = PHYS_SDRAM_SIZE,
+
+		.tras = 0x6,
+		.trc = 0x9,
+		.trcd = 0x3,
+		.trp = 0x3,
+		.cl = 0x3,
+
+		.memchip_dtype = 0x1,
+		.twr = 0x2,
+		.buswidth = 0x1,
+		.tmrd = 0x2,
+		.trrd = 0x2,
+
+		.refcnt = 0x0408,
+		.pwroncnt = 0x0042,
+	};
+
+	SoC_pll_cfg(CLK_MODE_SYNC, 2 * CFG_HZ_CLOCK, 0);
+	SoC_cs_cfg(EXP_CSSD0, CS_ENABLE, &cfg);
+
+	icache_enable();
+}
+
+static void exp_csp0_init (void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.buswidth = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x5,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSP0, CS_ENABLE, &cfg);
+}
+
+
+static void nand_hw_init(void)
+{
+	SoC_gpio_cfg(CFG_NAND_BR_GPIO, GPIO_TYPE_INPUT);
+	SoC_gpio_cfg(CFG_NAND_CE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_CLE_GPIO, GPIO_TYPE_OUTPUT);
+	SoC_gpio_cfg(CFG_NAND_ALE_GPIO, GPIO_TYPE_OUTPUT);
+}
+
+static void nor_hw_init(void)
+{
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+
+		.baseaddr = PHYS_FLASH2,
+		.size = 8 * 1024 * 1024,
+
+		.buswidth = CS_BUSWIDTH_16BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmdwidth = 0x9,
+		.addrsetup = 0x7,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSSD1, CS_ENABLE, &cfg);
+
+	SoC_ioctrl_cfg(IOCTRL_EXPA21_A22, 1);
+}
+
+static void eeprom_hw_init(void)
+{
+#if 0
+	struct cs_cfg cfg = {
+		.memtype = CS_MEMTYPE_SRAM,
+		.bus_width = CS_BUSWIDTH_8BIT,
+		.level = CS_ACTIVE_LOW,
+		.cmd_width = 0x5,
+		.addr_setup = 0x4,
+		.dqm_mode = CS_DQMMODE_NORMAL,
+	};
+
+	SoC_cs_cfg(EXP_CSBOOT, CS_ENABLE, &cfg);
+#endif
+}
+
+extern spi_chipsel_type spi_chipsel[];
+
+static void ethswitch_init(void)
+{
+	uchar dout[3];
+	int rc;
+
+	*(volatile u8 *)CPLD_RESET_CTRL &= ~ESWITCH_OUT_OF_RESET;	/* reset ESwitch */
+	*(volatile u8 *)CPLD_INTMASK |= ESWITCH_IRQMASK;
+	*(volatile u8 *)CPLD_RESET_CTRL |= ESWITCH_OUT_OF_RESET;	/* Take ESwitch out of reset */
+
+	spi_hw_init();
+
+	/* initialize the SPI write buffer */
+	dout[0] = 0x02;				/* Eswitch write command */
+	dout[1] = 1;				/* address */
+	dout[2] = 1;				/* value */
+	
+	rc = spi_xfer(spi_chipsel[2], 24, dout, NULL);
+	if (rc)
+		printf(" ethswitch_init: can't initialize the SPI bus \n", rc);
+}
+
+
+int board_init(void)
+{
+	/* arch number of Mindspeed Comcerto */
+	gd->bd->bi_arch_number = MACH_TYPE_M825XX;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOTPARAM_ADDR;
+
+	/* CPLD, FPGA and NAND chip select */
+	exp_csp0_init();
+
+	nand_hw_init();
+	nor_hw_init();
+	eeprom_hw_init();
+	ethswitch_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+extern void partition_flash(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	printf("Reserve MSP memory\n");
+	gd->bd->bi_dram[0].start += MSP_BOTTOM_MEMORY_RESERVED_SIZE;
+	gd->bd->bi_dram[0].size -= MSP_BOTTOM_MEMORY_RESERVED_SIZE + MSP_TOP_MEMORY_RESERVED_SIZE;
+	return 0;
+}
+#endif
diff --git a/board/mindspeed/udev800/config.mk b/board/mindspeed/udev800/config.mk
new file mode 100644
index 0000000..1ea3c40
--- /dev/null
+++ b/board/mindspeed/udev800/config.mk
@@ -0,0 +1,4 @@
+#
+#
+
+TEXT_BASE = 0x07E00000	# 126MiB
diff --git a/board/mindspeed/udev800/u-boot.lds b/board/mindspeed/udev800/u-boot.lds
new file mode 100644
index 0000000..ff5165a
--- /dev/null
+++ b/board/mindspeed/udev800/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2006
+ * Mindspeed Technologies, Inc. <www.mindspeed.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		cpu/arm920t/start.o (.text)
+
+		__arm1_init_start = .;
+		board/mindspeed/common/arm1_init.o (.text)
+		__arm1_init_end = .;
+
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/build_all.sh b/build_all.sh
new file mode 100644
index 0000000..ec28ea4
--- /dev/null
+++ b/build_all.sh
@@ -0,0 +1,24 @@
+#/bin/bash
+
+set -e
+
+export PATH=$PATH:/usr/local/gcc-3.4.5-glibc-2.3.6/arm-softfloat-linux-gnu/bin
+
+rm -f build_all.log
+
+conf_list='tsavo530 tsavo515 tsavo515_nor '\
+'megamombasa515 megamombasa515_256M megamombasa515_sdc1 '\
+'malindi ipots48-515 ipots48-800 udev515 udev800 nairobi supermombasa910 matisse '\
+'asic packet-iad router'
+
+conf_list='asic packet-iad router ferouter'
+
+for conf in ${conf_list}; do
+
+make distclean >> build_all.log 2>&1
+
+echo "building ${conf}"
+make ${conf}_config >> build_all.log 2>&1
+make >> build_all.log 2>&1
+echo "done"
+done;
diff --git a/common/Makefile b/common/Makefile
index 07ddc95..92e09fa 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -38,7 +38,7 @@
 	  cmd_load.o cmd_log.o \
 	  cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
-	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
+	  cmd_pci.o cmd_pcmcia.o cmd_phy.o cmd_portio.o \
 	  cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
 	  cmd_usb.o cmd_vfd.o \
 	  command.o console.o devices.o dlmalloc.o docecc.o \
@@ -51,7 +51,7 @@
 	  memsize.o miiphybb.o miiphyutil.o \
 	  s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
 	  usb.o usb_kbd.o usb_storage.o \
-	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
+	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o image.o
 
 SRCS	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 3091a58..2052608 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -79,7 +79,9 @@
 # define CHUNKSZ (64 * 1024)
 #endif
 
+#ifndef CONFIG_NO_GZIP
 int  gunzip (void *, int, unsigned char *, unsigned long *);
+#endif
 
 static void *zalloc(void *, unsigned, unsigned);
 static void zfree(void *, void *, unsigned);
@@ -94,6 +96,10 @@
 static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 #endif
 
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+static void fixup_comcerto_bootargs(void);
+#endif
+
 static void print_type (image_header_t *hdr);
 
 #ifdef __I386__
@@ -341,6 +347,7 @@
 #endif	/* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
 		}
 		break;
+#ifndef CONFIG_NO_GZIP
 	case IH_COMP_GZIP:
 		printf ("   Uncompressing %s ... ", name);
 		if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
@@ -350,6 +357,7 @@
 			do_reset (cmdtp, flag, argc, argv);
 		}
 		break;
+#endif /* CONFIG_NO_GZIP */
 #ifdef CONFIG_BZIP2
 	case IH_COMP_BZIP2:
 		printf ("   Uncompressing %s ... ", name);
@@ -409,6 +417,10 @@
 	}
 	SHOW_BOOT_PROGRESS (8);
 
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+	fixup_comcerto_bootargs();
+#endif
+
 	switch (hdr->ih_os) {
 	default:			/* handled by (original) Linux case */
 	case IH_OS_LINUX:
@@ -461,6 +473,20 @@
 	return 1;
 }
 
+int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
+{
+	const char *ep = getenv("autostart");
+
+	if (ep && !strcmp(ep, "yes")) {
+		char *local_args[2];
+		local_args[0] = (char *)cmd;
+		local_args[1] = NULL;
+		printf("Automatic boot of image at addr 0x%08lX ...\n", load_addr);
+		return do_bootm(cmdtp, 0, 1, local_args);
+	}
+
+	return 0;
+}
 U_BOOT_CMD(
  	bootm,	CFG_MAXARGS,	1,	do_bootm,
  	"bootm   - boot application image from memory\n",
@@ -476,6 +502,42 @@
 #endif
 );
 
+
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+extern unsigned char comcerto_part_no[8];
+#define FPP_ENABLED 1 /* Default Mode is FPP Enabled */
+#define FPP_DISABLED 0 /* FPP Enabled */
+
+#if defined(CONFIG_NOFPP_MODE)
+#define FPP_MODE FPP_DISABLED
+#endif
+#if !defined(CONFIG_NOFPP_MODE)
+#define FPP_MODE FPP_ENABLED
+#endif
+
+static void fixup_comcerto_bootargs(void)
+{
+	char buf[256]; 
+	char partno[32]; 
+	char fppmode[32]; 
+	char *cmdline = getenv ("bootargs");
+
+	sprintf (partno, " partno=%s", comcerto_part_no);
+	sprintf (fppmode, " fppmode=%d", FPP_MODE);
+	if (cmdline) {
+		strcpy(buf, cmdline);
+		strcat(buf, partno);
+		strcat(buf, fppmode);
+
+	} else {
+		strcpy(buf, partno);
+		strcat(buf, fppmode);
+	}
+	
+	setenv ("bootargs", buf);
+}
+#endif
+
 #ifdef CONFIG_SILENT_CONSOLE
 static void
 fixup_silent_linux ()
@@ -1429,6 +1491,7 @@
 
 #define DEFLATED	8
 
+#ifndef CONFIG_NO_GZIP
 int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp)
 {
 	z_stream s;
@@ -1483,6 +1546,7 @@
 
 	return (0);
 }
+#endif /* CONFIG_NO_GZIP */
 
 #ifdef CONFIG_BZIP2
 void bz_internal_error(int errcode)
diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 1d92bb3..8df4e8c 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -54,13 +54,14 @@
 	addr = load_elf_image (addr);
 
 	printf ("## Starting application at 0x%08lx ...\n", addr);
-
+#if 0
 	/*
 	 * QNX images require the data cache is disabled.
 	 * Data cache is already flushed, so just turn it off.
 	 */
 	if (dcache_status ())
 		dcache_disable ();
+#endif
 
 	/*
 	 * pass address parameter as argv[0] (aka command name),
@@ -99,8 +100,8 @@
 	if ((tmp = getenv ("loadaddr")) != NULL) {
 		addr = simple_strtoul (tmp, NULL, 16);
 	} else {
-		puts ("No load address provided\n");
-		return 1;
+		addr = 0x81400000;
+		printf("No load address provided, looking @ %x\n", addr);
 	}
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
@@ -137,7 +138,7 @@
 	 */
 
 	if ((tmp = getenv ("bootaddr")) == NULL)
-		bootaddr = 0x4200;
+		bootaddr = 0x80800700; /*Default value for C1xx devices */
 	else
 		bootaddr = simple_strtoul (tmp, NULL, 16);
 
diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index 7fd1fa3..32cf48a 100644
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -107,7 +107,7 @@
 #endif /* !CFG_NAND_LEGACY */
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
 /* enable/disable debugging messages */
-#define	DEBUG_JFFS
+//#define	DEBUG_JFFS
 #undef	DEBUG_JFFS
 
 #ifdef  DEBUG_JFFS
@@ -1835,6 +1835,60 @@
 /***************************************************/
 /* U-boot commands				   */
 /***************************************************/
+int do_jffs2_uload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    char *fsname;
+    char *filename;
+    int size;
+    struct part_info *part;
+    ulong offset = load_addr;
+
+    /* pre-set Boot file name */
+    if ((filename = getenv("bootfile")) == NULL) {
+        filename = "uImage";
+    }
+
+    if (argc == 2) {
+        filename = argv[1];
+    }
+    if (argc == 3) {
+        offset = simple_strtoul(argv[1], NULL, 16);
+        load_addr = offset;
+        filename = argv[2];
+    }
+
+    /* make sure we are in sync with env variables */
+    if (mtdparts_init() !=0)
+        return 1;
+
+    if ((part = jffs2_part_info(current_dev, current_partnum))){
+
+        /* check partition type for cramfs */
+        fsname = (cramfs_check(part) ? "CRAMFS" : "JFFS2");
+        printf("### %s loading '%s' to 0x%lx\n", fsname, filename, offset);
+
+        if (cramfs_check(part)) {
+            size = cramfs_load ((char *) offset, part, filename);
+        } else {
+            /* if this is not cramfs assume jffs2 */
+            size = jffs2_1pass_uload((char *)offset, part, filename);
+        }
+
+        if (size > 0) {
+            char buf[10];
+            printf("### %s load complete: %d bytes loaded to 0x%lx\n",
+                fsname, size, offset);
+            sprintf(buf, "%x", size);
+            setenv("filesize", buf);
+        } else {
+            printf("### %s LOAD ERROR<%x> for %s!\n", fsname, size, filename);
+        }
+
+        return !(size > 0);
+    }
+    return 1;
+}
+
 
 /**
  * Routine implementing fsload u-boot command. This routine tries to load
@@ -2127,6 +2181,15 @@
 
 /***************************************************/
 U_BOOT_CMD(
+    uload, 3,  0,  do_jffs2_uload,
+    "uload\t- load kernel file from a filesystem image\n",
+    "[ off ] [ filename ]\n"
+    "    - load kernel file from flash bank\n"
+    "      with offset 'off'\n"
+);
+
+
+U_BOOT_CMD(
 	fsload,	3,	0,	do_jffs2_fsload,
 	"fsload\t- load binary file from a filesystem image\n",
 	"[ off ] [ filename ]\n"
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index d0fae6b..63884ee 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -438,6 +438,37 @@
 		puts ("done\n");
 		return 0;
 	}
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+        if ( (addr2info(addr) != NULL))
+        {
+                int cfg_gpio = 0;
+                puts ("Copy from Flash... ");
+                board_map(NULL, addr);
+                if((addr < (PHYS_FLASH1 + 0x800000)) && ((addr+(count*size)) >= (PHYS_FLASH1 + 0x800000)))
+                {
+                        cfg_gpio = 1;
+                }
+                while (count-- > 0) {
+                        if((cfg_gpio && (addr >=(PHYS_FLASH1 + 0x800000))))
+                        {
+                                cfg_gpio = 0;
+                                board_map(NULL, addr);
+                        }
+                        if (size == 4)
+                                *((ulong  *)dest) = *((ulong  *)addr);
+                        else if (size == 2)
+                                *((ushort *)dest) = *((ushort *)addr);
+                        else
+                                *((u_char *)dest) = *((u_char *)addr);
+                        addr += size;
+                        dest += size;
+                }
+                puts ("done\n");
+
+                return 0;
+        }
+#endif
+
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_MMC)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 7286726..486aeae 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -4,173 +4,443 @@
  * (c) 1999 Machine Vision Holdings, Inc.
  * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
  *
+ * Ported 'dynenv' to 'nand env.oob' command
+ * (C) 2010 Nanometrics, Inc.
+ * 'dynenv' -- Dynamic environment offset in NAND OOB
+ * (C) Copyright 2006-2007 OpenMoko, Inc.
  * Added 16-bit nand support
  * (C) 2004 Texas Instruments
+ *
+ * Copyright 2010, 2012 Freescale Semiconductor
+ * The portions of this file whose copyright is held by Freescale and which
+ * are not considered a derived work of GPL v2-only code may be distributed
+ * and/or modified under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
  */
 
 #include <common.h>
-
-
-#ifndef CFG_NAND_LEGACY
-/*
- *
- * New NAND support
- *
- */
-#include <common.h>
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-
+#include <linux/mtd/mtd.h>
 #include <command.h>
 #include <watchdog.h>
 #include <malloc.h>
 #include <asm/byteorder.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
 #include <jffs2/jffs2.h>
 #include <nand.h>
+#include <bootstage.h>
+#include <config.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
 
-/* parition handling routines */
+#if defined(CONFIG_CMD_MTDPARTS)
+
+/* partition handling routines */
 int mtdparts_init(void);
 int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
 int find_dev_and_part(const char *id, struct mtd_device **dev,
-		u8 *part_num, struct part_info **part);
+		      u8 *part_num, struct part_info **part);
 #endif
 
-extern nand_info_t nand_info[];       /* info for NAND chips */
-
-static int nand_dump_oob(nand_info_t *nand, ulong off)
-{
-	return 0;
-}
-
-static int nand_dump(nand_info_t *nand, ulong off)
+static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 {
 	int i;
-	u_char *buf, *p;
+	u_char *datbuf, *oobbuf, *p;
+	static loff_t last;
 
-	buf = malloc(nand->oobblock + nand->oobsize);
-	if (!buf) {
+	if (repeat)
+		off = last + nand->writesize;
+
+	last = off;
+
+	datbuf = malloc(nand->writesize);
+	oobbuf = malloc(nand->oobsize);
+	if (!datbuf || !oobbuf) {
 		puts("No memory for page buffer\n");
 		return 1;
 	}
-	off &= ~(nand->oobblock - 1);
-	i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize);
+	off &= ~(nand->writesize - 1);
+	loff_t addr = (loff_t) off;
+	struct mtd_oob_ops ops;
+	memset(&ops, 0, sizeof(ops));
+	ops.datbuf = datbuf;
+	ops.oobbuf = oobbuf;
+	ops.len = nand->writesize;
+	ops.ooblen = nand->oobsize;
+	ops.mode = MTD_OOB_RAW;
+	i = nand->read_oob(nand, addr, &ops);
 	if (i < 0) {
-		printf("Error (%d) reading page %08x\n", i, off);
-		free(buf);
+		printf("Error (%d) reading page %08lx\n", i, off);
+		free(datbuf);
+		free(oobbuf);
 		return 1;
 	}
-	printf("Page %08x dump:\n", off);
-	i = nand->oobblock >> 4; p = buf;
+	printf("Page %08lx dump:\n", off);
+	i = nand->writesize >> 4;
+	p = datbuf;
+
 	while (i--) {
-		printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x"
-			"  %02x %02x %02x %02x %02x %02x %02x %02x\n",
-			p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
-			p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);
+		if (!only_oob)
+			printf("\t%02x %02x %02x %02x %02x %02x %02x %02x"
+			       "  %02x %02x %02x %02x %02x %02x %02x %02x\n",
+			       p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
+			       p[8], p[9], p[10], p[11], p[12], p[13], p[14],
+			       p[15]);
 		p += 16;
 	}
 	puts("OOB:\n");
 	i = nand->oobsize >> 3;
+	p = oobbuf;
 	while (i--) {
-		printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
-			p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+		printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
+		       p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
 		p += 8;
 	}
-	free(buf);
+	free(datbuf);
+	free(oobbuf);
 
 	return 0;
 }
 
 /* ------------------------------------------------------------------------- */
 
-static inline int str2long(char *p, ulong *num)
+static int set_dev(int dev)
+{
+	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+	    !nand_info[dev].name) {
+		puts("No such device\n");
+		return -1;
+	}
+
+	if (nand_curr_device == dev)
+		return 0;
+
+	printf("Device %d: %s", dev, nand_info[dev].name);
+	puts("... is now current device\n");
+	nand_curr_device = dev;
+
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
+	board_nand_select_device(nand_info[dev].priv, dev);
+#endif
+
+	return 0;
+}
+
+static inline int str2off(const char *p, loff_t *num)
+{
+	char *endptr;
+
+	*num = simple_strtoull(p, &endptr, 16);
+	return *p != '\0' && *endptr == '\0';
+}
+
+static inline int str2long(const char *p, ulong *num)
 {
 	char *endptr;
 
 	*num = simple_strtoul(p, &endptr, 16);
-	return (*p != '\0' && *endptr == '\0') ? 1 : 0;
+	return *p != '\0' && *endptr == '\0';
 }
 
-static int
-arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size)
+static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size)
 {
-	int idx = nand_curr_device;
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+#ifdef CONFIG_CMD_MTDPARTS
 	struct mtd_device *dev;
 	struct part_info *part;
 	u8 pnum;
+	int ret;
 
-	if (argc >= 1 && !(str2long(argv[0], off))) {
-		if ((mtdparts_init() == 0) &&
-		    (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) {
-			if (dev->id->type != MTD_DEV_TYPE_NAND) {
-				puts("not a NAND device\n");
-				return -1;
-			}
-			*off = part->offset;
-			if (argc >= 2) {
-				if (!(str2long(argv[1], size))) {
-					printf("'%s' is not a number\n", argv[1]);
-					return -1;
-				}
-				if (*size > part->size)
-					*size = part->size;
-			} else {
-				*size = part->size;
-			}
-			idx = dev->id->num;
-			*nand = nand_info[idx];
-			goto out;
-		}
+	ret = mtdparts_init();
+	if (ret)
+		return ret;
+
+	ret = find_dev_and_part(partname, &dev, &pnum, &part);
+	if (ret)
+		return ret;
+
+	if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		puts("not a NAND device\n");
+		return -1;
 	}
+
+	*off = part->offset;
+	*size = part->size;
+	*idx = dev->id->num;
+
+	ret = set_dev(*idx);
+	if (ret)
+		return ret;
+
+	return 0;
+#else
+	puts("offset is not a number\n");
+	return -1;
 #endif
+}
 
-	if (argc >= 1) {
-		if (!(str2long(argv[0], off))) {
-			printf("'%s' is not a number\n", argv[0]);
-			return -1;
-		}
-	} else {
-		*off = 0;
+static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *maxsize)
+{
+	if (!str2off(arg, off))
+		return get_part(arg, idx, off, maxsize);
+
+	if (*off >= nand_info[*idx].size) {
+		puts("Offset exceeds device limit\n");
+		return -1;
 	}
 
-	if (argc >= 2) {
-		if (!(str2long(argv[1], size))) {
-			printf("'%s' is not a number\n", argv[1]);
-			return -1;
-		}
-	} else {
-		*size = nand->size - *off;
-	}
-
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
-out:
-#endif
-	printf("device %d ", idx);
-	if (*size == nand->size)
-		puts("whole chip\n");
-	else
-		printf("offset 0x%x, size 0x%x\n", *off, *size);
+	*maxsize = nand_info[*idx].size - *off;
 	return 0;
 }
 
-int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int arg_off_size(int argc, char *const argv[], int *idx,
+			loff_t *off, loff_t *size)
 {
-	int i, dev, ret;
-	ulong addr, off, size;
+	int ret;
+	loff_t maxsize = 0;
+
+	if (argc == 0) {
+		*off = 0;
+		*size = nand_info[*idx].size;
+		goto print;
+	}
+
+	ret = arg_off(argv[0], idx, off, &maxsize);
+	if (ret)
+		return ret;
+
+	if (argc == 1) {
+		*size = maxsize;
+		goto print;
+	}
+
+	if (!str2off(argv[1], size)) {
+		printf("'%s' is not a number\n", argv[1]);
+		return -1;
+	}
+
+	if (*size > maxsize) {
+		puts("Size exceeds partition or device limit\n");
+		return -1;
+	}
+
+print:
+	printf("device %d ", *idx);
+	if (*size == nand_info[*idx].size)
+		puts("whole chip\n");
+	else
+		printf("offset 0x%llx, size 0x%llx\n",
+		       (unsigned long long)*off, (unsigned long long)*size);
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+static void print_status(ulong start, ulong end, ulong erasesize, int status)
+{
+	printf("%08lx - %08lx: %08lx blocks %s%s%s\n",
+		start,
+		end - 1,
+		(end - start) / erasesize,
+		((status & NAND_LOCK_STATUS_TIGHT) ?  "TIGHT " : ""),
+		((status & NAND_LOCK_STATUS_LOCK) ?  "LOCK " : ""),
+		((status & NAND_LOCK_STATUS_UNLOCK) ?  "UNLOCK " : ""));
+}
+
+static void do_nand_status(nand_info_t *nand)
+{
+	ulong block_start = 0;
+	ulong off;
+	int last_status = -1;
+
+	struct nand_chip *nand_chip = nand->priv;
+	/* check the WP bit */
+	nand_chip->cmdfunc(nand, NAND_CMD_STATUS, -1, -1);
+	printf("device is %swrite protected\n",
+		(nand_chip->read_byte(nand) & 0x80 ?
+		"NOT " : ""));
+
+	for (off = 0; off < nand->size; off += nand->erasesize) {
+		int s = nand_get_lock_status(nand, off);
+
+		/* print message only if status has changed */
+		if (s != last_status && off != 0) {
+			print_status(block_start, off, nand->erasesize,
+					last_status);
+			block_start = off;
+		}
+		last_status = s;
+	}
+	/* Print the last block info */
+	print_status(block_start, off, nand->erasesize, last_status);
+}
+#endif
+
+#ifdef CONFIG_ENV_OFFSET_OOB
+unsigned long nand_env_oob_offset;
+
+int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
+{
+	int ret;
+	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
+	nand_info_t *nand = &nand_info[0];
+	char *cmd = argv[1];
+
+	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) {
+		puts("no devices available\n");
+		return 1;
+	}
+
+	set_dev(0);
+
+	if (!strcmp(cmd, "get")) {
+		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		if (ret)
+			return 1;
+
+		printf("0x%08lx\n", nand_env_oob_offset);
+	} else if (!strcmp(cmd, "set")) {
+		loff_t addr;
+		loff_t maxsize;
+		struct mtd_oob_ops ops;
+		int idx = 0;
+
+		if (argc < 3)
+			goto usage;
+
+		if (arg_off(argv[2], &idx, &addr, &maxsize)) {
+			puts("Offset or partition name expected\n");
+			return 1;
+		}
+
+		if (idx != 0) {
+			puts("Partition not on first NAND device\n");
+			return 1;
+		}
+
+		if (nand->oobavail < ENV_OFFSET_SIZE) {
+			printf("Insufficient available OOB bytes:\n"
+			       "%d OOB bytes available but %d required for "
+			       "env.oob support\n",
+			       nand->oobavail, ENV_OFFSET_SIZE);
+			return 1;
+		}
+
+		if ((addr & (nand->erasesize - 1)) != 0) {
+			printf("Environment offset must be block-aligned\n");
+			return 1;
+		}
+
+		ops.datbuf = NULL;
+		ops.mode = MTD_OOB_AUTO;
+		ops.ooboffs = 0;
+		ops.ooblen = ENV_OFFSET_SIZE;
+		ops.oobbuf = (void *) oob_buf;
+
+		oob_buf[0] = ENV_OOB_MARKER;
+		oob_buf[1] = addr / nand->erasesize;
+
+		ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops);
+		if (ret) {
+			printf("Error writing OOB block 0\n");
+			return ret;
+		}
+
+		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		if (ret) {
+			printf("Error reading env offset in OOB\n");
+			return ret;
+		}
+
+		if (addr != nand_env_oob_offset) {
+			printf("Verification of env offset in OOB failed: "
+			       "0x%08llx expected but got 0x%08lx\n",
+			       (unsigned long long)addr, nand_env_oob_offset);
+			return 1;
+		}
+	} else {
+		goto usage;
+	}
+
+	return ret;
+
+usage:
+	return CMD_RET_USAGE;
+}
+
+#endif
+
+static void nand_print_and_set_info(int idx)
+{
+	nand_info_t *nand = &nand_info[idx];
+	struct nand_chip *chip = nand->priv;
+	const int bufsz = 32;
+	char buf[bufsz];
+
+	printf("Device %d: ", idx);
+	if (chip->numchips > 1)
+		printf("%dx ", chip->numchips);
+	printf("%s, sector size %u KiB\n",
+	       nand->name, nand->erasesize >> 10);
+	printf("  Page size  %8d b\n", nand->writesize);
+	printf("  OOB size   %8d b\n", nand->oobsize);
+	printf("  Erase size %8d b\n", nand->erasesize);
+
+	/* Set geometry info */
+	sprintf(buf, "%x", nand->writesize);
+	setenv("nand_writesize", buf);
+
+	sprintf(buf, "%x", nand->oobsize);
+	setenv("nand_oobsize", buf);
+
+	sprintf(buf, "%x", nand->erasesize);
+	setenv("nand_erasesize", buf);
+}
+
+static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
+			int read)
+{
+	int ret = 0;
+
+	while (count--) {
+		/* Raw access */
+		mtd_oob_ops_t ops = {
+			.datbuf = (u8 *)addr,
+			.oobbuf = ((u8 *)addr) + nand->writesize,
+			.len = nand->writesize,
+			.ooblen = nand->oobsize,
+			.mode = MTD_OOB_RAW
+		};
+
+		if (read)
+			ret = nand->read_oob(nand, off, &ops);
+		else
+			ret = nand->write_oob(nand, off, &ops);
+
+		if (ret) {
+			printf("%s: error at offset %llx, ret %d\n",
+				__func__, (long long)off, ret);
+			break;
+		}
+
+		addr += nand->writesize + nand->oobsize;
+		off += nand->writesize;
+	}
+
+	return ret;
+}
+
+int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	int i, ret = 0;
+	ulong addr;
+	loff_t off, size;
 	char *cmd, *s;
 	nand_info_t *nand;
+#ifdef CONFIG_SYS_NAND_QUIET
+	int quiet = CONFIG_SYS_NAND_QUIET;
+#else
 	int quiet = 0;
+#endif
 	const char *quiet_str = getenv("quiet");
+	int dev = nand_curr_device;
+	int repeat = flag & CMD_FLAG_REPEAT;
 
 	/* at least two arguments please */
 	if (argc < 2)
@@ -181,69 +451,60 @@
 
 	cmd = argv[1];
 
+	/* Only "dump" is repeatable. */
+	if (repeat && strcmp(cmd, "dump"))
+		return 0;
+
 	if (strcmp(cmd, "info") == 0) {
 
 		putc('\n');
-		for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
+		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
 			if (nand_info[i].name)
-				printf("Device %d: %s, sector size %lu KiB\n",
-					i, nand_info[i].name,
-					nand_info[i].erasesize >> 10);
+				nand_print_and_set_info(i);
 		}
 		return 0;
 	}
 
 	if (strcmp(cmd, "device") == 0) {
-
 		if (argc < 3) {
-			if ((nand_curr_device < 0) ||
-			    (nand_curr_device >= CFG_MAX_NAND_DEVICE))
-				puts("\nno devices available\n");
+			putc('\n');
+			if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE)
+				puts("no devices available\n");
 			else
-				printf("\nDevice %d: %s\n", nand_curr_device,
-					nand_info[nand_curr_device].name);
+				nand_print_and_set_info(dev);
 			return 0;
 		}
-		dev = (int)simple_strtoul(argv[2], NULL, 10);
-		if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
-			puts("No such device\n");
-			return 1;
-		}
-		printf("Device %d: %s", dev, nand_info[dev].name);
-		puts("... is now current device\n");
-		nand_curr_device = dev;
 
-#ifdef CFG_NAND_SELECT_DEVICE
-		/*
-		 * Select the chip in the board/cpu specific driver
-		 */
-		board_nand_select_device(nand_info[dev].priv, dev);
-#endif
+		dev = (int)simple_strtoul(argv[2], NULL, 10);
+		set_dev(dev);
 
 		return 0;
 	}
 
-	if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
-	    strncmp(cmd, "dump", 4) != 0 &&
-	    strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 &&
-	    strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 &&
-	    strcmp(cmd, "biterr") != 0 &&
-	    strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 )
-		goto usage;
+#ifdef CONFIG_ENV_OFFSET_OOB
+	/* this command operates only on the first nand device */
+	if (strcmp(cmd, "env.oob") == 0)
+		return do_nand_env_oob(cmdtp, argc - 1, argv + 1);
+#endif
 
-	/* the following commands operate on the current device */
-	if (nand_curr_device < 0 || nand_curr_device >= CFG_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
+	/* The following commands operate on the current device, unless
+	 * overridden by a partition specifier.  Note that if somehow the
+	 * current device is invalid, it will have to be changed to a valid
+	 * one before these commands can run, even if a partition specifier
+	 * for another device is to be used.
+	 */
+	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+	    !nand_info[dev].name) {
 		puts("\nno devices available\n");
 		return 1;
 	}
-	nand = &nand_info[nand_curr_device];
+	nand = &nand_info[dev];
 
 	if (strcmp(cmd, "bad") == 0) {
-		printf("\nDevice %d bad blocks:\n", nand_curr_device);
+		printf("\nDevice %d bad blocks:\n", dev);
 		for (off = 0; off < nand->size; off += nand->erasesize)
 			if (nand_block_isbad(nand, off))
-				printf("  %08x\n", off);
+				printf("  %08llx\n", (unsigned long long)off);
 		return 0;
 	}
 
@@ -252,39 +513,74 @@
 	 *   0    1     2       3    4
 	 *   nand erase [clean] [off size]
 	 */
-	if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) {
+	if (strncmp(cmd, "erase", 5) == 0 || strncmp(cmd, "scrub", 5) == 0) {
 		nand_erase_options_t opts;
 		/* "clean" at index 2 means request to write cleanmarker */
 		int clean = argc > 2 && !strcmp("clean", argv[2]);
-		int o = clean ? 3 : 2;
-		int scrub = !strcmp(cmd, "scrub");
+		int scrub_yes = argc > 2 && !strcmp("-y", argv[2]);
+		int o = (clean || scrub_yes) ? 3 : 2;
+		int scrub = !strncmp(cmd, "scrub", 5);
+		int spread = 0;
+		int args = 2;
+		const char *scrub_warn =
+			"Warning: "
+			"scrub option will erase all factory set bad blocks!\n"
+			"         "
+			"There is no reliable way to recover them.\n"
+			"         "
+			"Use this command only for testing purposes if you\n"
+			"         "
+			"are sure of what you are doing!\n"
+			"\nReally scrub this NAND flash? <y/N>\n";
 
-		printf("\nNAND %s: ", scrub ? "scrub" : "erase");
+		if (cmd[5] != 0) {
+			if (!strcmp(&cmd[5], ".spread")) {
+				spread = 1;
+			} else if (!strcmp(&cmd[5], ".part")) {
+				args = 1;
+			} else if (!strcmp(&cmd[5], ".chip")) {
+				args = 0;
+			} else {
+				goto usage;
+			}
+		}
+
+		/*
+		 * Don't allow missing arguments to cause full chip/partition
+		 * erases -- easy to do accidentally, e.g. with a misspelled
+		 * variable name.
+		 */
+		if (argc != o + args)
+			goto usage;
+
+		printf("\nNAND %s: ", cmd);
 		/* skip first two or three arguments, look for offset and size */
-		if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0)
+		if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
 			return 1;
 
+		nand = &nand_info[dev];
+
 		memset(&opts, 0, sizeof(opts));
 		opts.offset = off;
 		opts.length = size;
 		opts.jffs2  = clean;
 		opts.quiet  = quiet;
+		opts.spread = spread;
 
 		if (scrub) {
-			puts("Warning: "
-			     "scrub option will erase all factory set "
-			     "bad blocks!\n"
-			     "         "
-			     "There is no reliable way to recover them.\n"
-			     "         "
-			     "Use this command only for testing purposes "
-			     "if you\n"
-			     "         "
-			     "are sure of what you are doing!\n"
-			     "\nReally scrub this NAND flash? <y/N>\n");
+			if (!scrub_yes)
+				puts(scrub_warn);
 
-			if (getc() == 'y' && getc() == '\r') {
+			if (scrub_yes)
 				opts.scrub = 1;
+			else if (getc() == 'y') {
+				puts("y");
+				if (getc() == '\r')
+					opts.scrub = 1;
+				else {
+					puts("scrub aborted\n");
+					return -1;
+				}
 			} else {
 				puts("scrub aborted\n");
 				return -1;
@@ -300,21 +596,17 @@
 		if (argc < 3)
 			goto usage;
 
-		s = strchr(cmd, '.');
 		off = (int)simple_strtoul(argv[2], NULL, 16);
-
-		if (s != NULL && strcmp(s, ".oob") == 0)
-			ret = nand_dump_oob(nand, off);
-		else
-			ret = nand_dump(nand, off);
+		ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
 
 		return ret == 0 ? 1 : 0;
-
 	}
 
-	/* read write */
 	if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
+		size_t rwsize;
+		ulong pagecount = 1;
 		int read;
+		int raw;
 
 		if (argc < 4)
 			goto usage;
@@ -323,68 +615,124 @@
 
 		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
 		printf("\nNAND %s: ", read ? "read" : "write");
-		if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0)
-			return 1;
+
+		nand = &nand_info[dev];
 
 		s = strchr(cmd, '.');
-		if (s != NULL &&
-		    (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
-			if (read) {
-				/* read */
-				nand_read_options_t opts;
-				memset(&opts, 0, sizeof(opts));
-				opts.buffer	= (u_char*) addr;
-				opts.length	= size;
-				opts.offset	= off;
-				opts.quiet      = quiet;
-				ret = nand_read_opts(nand, &opts);
-			} else {
-				/* write */
-				nand_write_options_t opts;
-				memset(&opts, 0, sizeof(opts));
-				opts.buffer	= (u_char*) addr;
-				opts.length	= size;
-				opts.offset	= off;
-				/* opts.forcejffs2 = 1; */
-				opts.pad	= 1;
-				opts.blockalign = 1;
-				opts.quiet      = quiet;
-				ret = nand_write_opts(nand, &opts);
+
+		if (s && !strcmp(s, ".raw")) {
+			printf("\n .raw \n");
+			raw = 1;
+
+			if (arg_off(argv[3], &dev, &off, &size))
+				return 1;
+
+			if (argc > 4 && !str2long(argv[4], &pagecount)) {
+				printf("'%s' is not a number\n", argv[4]);
+				return 1;
 			}
+
+			if (pagecount * nand->writesize > size) {
+				puts("Size exceeds partition or device limit\n");
+				return -1;
+			}
+
+			rwsize = pagecount * (nand->writesize + nand->oobsize);
 		} else {
-			if (read)
-				ret = nand_read(nand, off, &size, (u_char *)addr);
-			else
-				ret = nand_write(nand, off, &size, (u_char *)addr);
+			if (arg_off_size(argc - 3, argv + 3, &dev,
+						&off, &size) != 0)
+				return 1;
+
+			rwsize = size;
 		}
 
-		printf(" %d bytes %s: %s\n", size,
+		if (!s || !strcmp(s, ".jffs2") ||
+		    !strcmp(s, ".e") || !strcmp(s, ".i")) {
+			if (read)
+				ret = nand_read_skip_bad(nand, off, &rwsize,
+							 (u_char *)addr);
+			else
+				ret = nand_write_skip_bad(nand, off, &rwsize,
+							  (u_char *)addr, 0);
+#ifdef CONFIG_CMD_NAND_TRIMFFS
+		} else if (!strcmp(s, ".trimffs")) {
+			if (read) {
+				printf("Unknown nand command suffix '%s'\n", s);
+				return 1;
+			}
+			ret = nand_write_skip_bad(nand, off, &rwsize,
+						(u_char *)addr,
+						WITH_DROP_FFS);
+#endif
+#ifdef CONFIG_CMD_NAND_YAFFS
+		} else if (!strcmp(s, ".yaffs")) {
+			if (read) {
+				printf("Unknown nand command suffix '%s'.\n", s);
+				return 1;
+			}
+			ret = nand_write_skip_bad(nand, off, &rwsize,
+						(u_char *)addr,
+						WITH_INLINE_OOB);
+#endif
+		} else if (!strcmp(s, ".oob")) {
+			/* out-of-band data */
+			mtd_oob_ops_t ops = {
+				.oobbuf = (u8 *)addr,
+				.ooblen = rwsize,
+				.mode = MTD_OOB_RAW
+			};
+
+			if (read)
+				ret = nand->read_oob(nand, off, &ops);
+			else
+				ret = nand->write_oob(nand, off, &ops);
+		} else if (raw) {
+			ret = raw_access(nand, addr, off, pagecount, read);
+		} else {
+			printf("Unknown nand command suffix '%s'.\n", s);
+			return 1;
+		}
+
+		printf(" %d bytes %s: %s\n", rwsize,
 		       read ? "read" : "written", ret ? "ERROR" : "OK");
 
 		return ret == 0 ? 0 : 1;
 	}
 
 	if (strcmp(cmd, "markbad") == 0) {
-		addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+		argc -= 2;
+		argv += 2;
 
-		int ret = nand->block_markbad(nand, addr);
-		if (ret == 0) {
-			printf("block 0x%08lx successfully marked as bad\n",
-			       (ulong) addr);
-			return 0;
-		} else {
-			printf("block 0x%08lx NOT marked as bad! ERROR %d\n",
-			       (ulong) addr, ret);
+		if (argc <= 0)
+			goto usage;
+
+		while (argc > 0) {
+			addr = simple_strtoul(*argv, NULL, 16);
+
+			if (nand->block_markbad(nand, addr)) {
+				printf("block 0x%08lx NOT marked "
+					"as bad! ERROR %d\n",
+					addr, ret);
+				ret = 1;
+			} else {
+				printf("block 0x%08lx successfully "
+					"marked as bad\n",
+					addr);
+			}
+			--argc;
+			++argv;
 		}
-		return 1;
+		return ret;
 	}
+
 	if (strcmp(cmd, "biterr") == 0) {
 		/* todo */
 		return 1;
 	}
 
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
 	if (strcmp(cmd, "lock") == 0) {
-		int tight  = 0;
+		int tight = 0;
 		int status = 0;
 		if (argc == 3) {
 			if (!strcmp("tight", argv[2]))
@@ -392,39 +740,8 @@
 			if (!strcmp("status", argv[2]))
 				status = 1;
 		}
-
 		if (status) {
-			ulong block_start = 0;
-			ulong off;
-			int last_status = -1;
-
-			struct nand_chip *nand_chip = nand->priv;
-			/* check the WP bit */
-			nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1);
-			printf("device is %swrite protected\n",
-			       (nand_chip->read_byte(nand) & 0x80 ?
-				"NOT " : "" ) );
-
-			for (off = 0; off < nand->size; off += nand->oobblock) {
-				int s = nand_get_lock_status(nand, off);
-
-				/* print message only if status has changed
-				 * or at end of chip
-				 */
-				if (off == nand->size - nand->oobblock
-				    || (s != last_status && off != 0))	{
-
-					printf("%08x - %08x: %8d pages %s%s%s\n",
-					       block_start,
-					       off-1,
-					       (off-block_start)/nand->oobblock,
-					       ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
-					       ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
-					       ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
-				}
-
-				last_status = s;
-		       }
+			do_nand_status(nand);
 		} else {
 			if (!nand_lock(nand, tight)) {
 				puts("NAND flash successfully locked\n");
@@ -437,10 +754,10 @@
 	}
 
 	if (strcmp(cmd, "unlock") == 0) {
-		if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0)
+		if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0)
 			return 1;
 
-		if (!nand_unlock(nand, off, size)) {
+		if (!nand_unlock(&nand_info[dev], off, size)) {
 			puts("NAND flash successfully unlocked\n");
 		} else {
 			puts("Error unlocking NAND flash, "
@@ -449,92 +766,150 @@
 		}
 		return 0;
 	}
+#endif
 
 usage:
-	printf("Usage:\n%s\n", cmdtp->usage);
-	return 1;
+	return CMD_RET_USAGE;
 }
 
-U_BOOT_CMD(nand, 5, 1, do_nand,
-	"nand    - NAND sub-system\n",
-	"info                  - show available NAND devices\n"
-	"nand device [dev]     - show or set current device\n"
-	"nand read[.jffs2]     - addr off|partition size\n"
-	"nand write[.jffs2]    - addr off|partiton size - read/write `size' bytes starting\n"
-	"    at offset `off' to/from memory address `addr'\n"
-	"nand erase [clean] [off size] - erase `size' bytes from\n"
-	"    offset `off' (entire device if not specified)\n"
+U_BOOT_CMD(
+	nand, CONFIG_SYS_MAXARGS, 1, do_nand,
+	"NAND sub-system",
+	"info - show available NAND devices\n"
+	"nand device [dev] - show or set current device\n"
+	"nand read - addr off|partition size\n"
+	"nand write - addr off|partition size\n"
+	"    read/write 'size' bytes starting at offset 'off'\n"
+	"    to/from memory address 'addr', skipping bad blocks.\n"
+	"nand read.raw - addr off|partition [count]\n"
+	"nand write.raw - addr off|partition [count]\n"
+	"    Use read.raw/write.raw to avoid ECC and access the flash as-is.\n"
+#ifdef CONFIG_CMD_NAND_TRIMFFS
+	"nand write.trimffs - addr off|partition size\n"
+	"    write 'size' bytes starting at offset 'off' from memory address\n"
+	"    'addr', skipping bad blocks and dropping any pages at the end\n"
+	"    of eraseblocks that contain only 0xFF\n"
+#endif
+#ifdef CONFIG_CMD_NAND_YAFFS
+	"nand write.yaffs - addr off|partition size\n"
+	"    write 'size' bytes starting at offset 'off' with yaffs format\n"
+	"    from memory address 'addr', skipping bad blocks.\n"
+#endif
+	"nand erase[.spread] [clean] off size - erase 'size' bytes "
+	"from offset 'off'\n"
+	"    With '.spread', erase enough for given file size, otherwise,\n"
+	"    'size' includes skipped bad blocks.\n"
+	"nand erase.part [clean] partition - erase entire mtd partition'\n"
+	"nand erase.chip [clean] - erase entire chip'\n"
 	"nand bad - show bad blocks\n"
 	"nand dump[.oob] off - dump page\n"
-	"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
-	"nand markbad off - mark bad block at offset (UNSAFE)\n"
-	"nand biterr off - make a bit error at offset (UNSAFE)\n"
-	"nand lock [tight] [status] - bring nand to lock state or display locked pages\n"
-	"nand unlock [offset] [size] - unlock section\n");
+	"nand scrub [-y] off size | scrub.part partition | scrub.chip\n"
+	"    really clean NAND erasing bad blocks (UNSAFE)\n"
+	"nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n"
+	"nand biterr off - make a bit error at offset (UNSAFE)"
+#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
+	"\n"
+	"nand lock [tight] [status]\n"
+	"    bring nand to lock state or display locked pages\n"
+	"nand unlock [offset] [size] - unlock section"
+#endif
+#ifdef CONFIG_ENV_OFFSET_OOB
+	"\n"
+	"nand env.oob - environment offset in OOB of block 0 of"
+	"    first device.\n"
+	"nand env.oob set off|partition - set enviromnent offset\n"
+	"nand env.oob get - get environment offset"
+#endif
+);
 
 static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 			   ulong offset, ulong addr, char *cmd)
 {
 	int r;
-	char *ep;
-	ulong cnt;
+	char *s;
+	size_t cnt;
 	image_header_t *hdr;
+#if defined(CONFIG_FIT)
+	const void *fit_hdr = NULL;
+#endif
+
+	s = strchr(cmd, '.');
+	if (s != NULL &&
+	    (strcmp(s, ".jffs2") && strcmp(s, ".e") && strcmp(s, ".i"))) {
+		printf("Unknown nand load suffix '%s'\n", s);
+		bootstage_error(BOOTSTAGE_ID_NAND_SUFFIX);
+		return 1;
+	}
 
 	printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
 
-	cnt = nand->oobblock;
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	cnt = nand->writesize;
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_HDR_READ);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_HDR_READ);
 
-	hdr = (image_header_t *) addr;
+	switch (genimg_get_format ((void *)addr)) {
+	case IMAGE_FORMAT_LEGACY:
+		hdr = (image_header_t *)addr;
 
-	if (ntohl(hdr->ih_magic) != IH_MAGIC) {
-		printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_mark(BOOTSTAGE_ID_NAND_TYPE);
+		image_print_contents (hdr);
+
+		cnt = image_get_image_size (hdr);
+		break;
+#if defined(CONFIG_FIT)
+	case IMAGE_FORMAT_FIT:
+		fit_hdr = (const void *)addr;
+		puts ("Fit image detected...\n");
+
+		cnt = fit_get_size (fit_hdr);
+		break;
+#endif
+	default:
+		bootstage_error(BOOTSTAGE_ID_NAND_TYPE);
+		puts ("** Unknown image type\n");
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_TYPE);
 
-	print_image_hdr(hdr);
-
-	cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t));
-
-	r = nand_read(nand, offset, &cnt, (u_char *) addr);
+	r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr);
 	if (r) {
 		puts("** Read error\n");
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_READ);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_READ);
+
+#if defined(CONFIG_FIT)
+	/* This cannot be done earlier, we need complete FIT image in RAM first */
+	if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) {
+		if (!fit_check_format (fit_hdr)) {
+			bootstage_error(BOOTSTAGE_ID_NAND_FIT_READ);
+			puts ("** Bad FIT image format\n");
+			return 1;
+		}
+		bootstage_mark(BOOTSTAGE_ID_NAND_FIT_READ_OK);
+		fit_print_contents (fit_hdr);
+	}
+#endif
 
 	/* Loading ok, update default load address */
 
 	load_addr = addr;
 
-	/* Check if we should attempt an auto-start */
-	if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
-		char *local_args[2];
-		extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
-
-		local_args[0] = cmd;
-		local_args[1] = NULL;
-
-		printf("Automatic boot of image at addr 0x%08lx ...\n", addr);
-
-		do_bootm(cmdtp, 0, 1, local_args);
-		return 1;
-	}
-	return 0;
+	return bootm_maybe_autostart(cmdtp, cmd);
 }
 
-int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	char *boot_device = NULL;
 	int idx;
 	ulong addr, offset = 0;
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+#if defined(CONFIG_CMD_MTDPARTS)
 	struct mtd_device *dev;
 	struct part_info *part;
 	u8 pnum;
@@ -550,18 +925,19 @@
 			if (argc > 3)
 				goto usage;
 			if (argc == 3)
-				addr = simple_strtoul(argv[2], NULL, 16);
+				addr = simple_strtoul(argv[1], NULL, 16);
 			else
-				addr = CFG_LOAD_ADDR;
+				addr = CONFIG_SYS_LOAD_ADDR;
 			return nand_load_image(cmdtp, &nand_info[dev->id->num],
 					       part->offset, addr, argv[0]);
 		}
 	}
 #endif
 
+	bootstage_mark(BOOTSTAGE_ID_NAND_PART);
 	switch (argc) {
 	case 1:
-		addr = CFG_LOAD_ADDR;
+		addr = CONFIG_SYS_LOAD_ADDR;
 		boot_device = getenv("bootdevice");
 		break;
 	case 2:
@@ -578,409 +954,34 @@
 		offset = simple_strtoul(argv[3], NULL, 16);
 		break;
 	default:
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+#if defined(CONFIG_CMD_MTDPARTS)
 usage:
 #endif
-		printf("Usage:\n%s\n", cmdtp->usage);
-		SHOW_BOOT_PROGRESS(-1);
-		return 1;
+		bootstage_error(BOOTSTAGE_ID_NAND_SUFFIX);
+		return CMD_RET_USAGE;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_SUFFIX);
 
 	if (!boot_device) {
 		puts("\n** No boot device **\n");
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_BOOT_DEVICE);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_BOOT_DEVICE);
 
 	idx = simple_strtoul(boot_device, NULL, 16);
 
-	if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) {
+	if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) {
 		printf("\n** Device %d not available\n", idx);
-		SHOW_BOOT_PROGRESS(-1);
+		bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
 		return 1;
 	}
+	bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
 
 	return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
 }
 
 U_BOOT_CMD(nboot, 4, 1, do_nandboot,
-	"nboot   - boot from NAND device\n",
-	"[partition] | [[[loadAddr] dev] offset]\n");
-
-#endif				/* (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
-#else /* CFG_NAND_LEGACY */
-/*
- *
- * Legacy NAND support - to be phased out
- *
- */
-#include <command.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-#if 0
-#include <linux/mtd/nand_ids.h>
-#include <jffs2/jffs2.h>
-#endif
-
-#ifdef CONFIG_OMAP1510
-void archflashwp(void *archdata, int wp);
-#endif
-
-#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
-
-#undef	NAND_DEBUG
-#undef	PSYCHO_DEBUG
-
-/* ****************** WARNING *********************
- * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
- * erase (or at least attempt to erase) blocks that are marked
- * bad. This can be very handy if you are _sure_ that the block
- * is OK, say because you marked a good block bad to test bad
- * block handling and you are done testing, or if you have
- * accidentally marked blocks bad.
- *
- * Erasing factory marked bad blocks is a _bad_ idea. If the
- * erase succeeds there is no reliable way to find them again,
- * and attempting to program or erase bad blocks can affect
- * the data in _other_ (good) blocks.
- */
-#define	 ALLOW_ERASE_BAD_DEBUG 0
-
-#define CONFIG_MTD_NAND_ECC  /* enable ECC */
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-/* bits for nand_legacy_rw() `cmd'; or together as needed */
-#define NANDRW_READ	0x01
-#define NANDRW_WRITE	0x00
-#define NANDRW_JFFS2	0x02
-#define NANDRW_JFFS2_SKIP	0x04
-
-/*
- * Imports from nand_legacy.c
- */
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-extern int curr_device;
-extern int nand_legacy_erase(struct nand_chip *nand, size_t ofs,
-			    size_t len, int clean);
-extern int nand_legacy_rw(struct nand_chip *nand, int cmd, size_t start,
-			 size_t len, size_t *retlen, u_char *buf);
-extern void nand_print(struct nand_chip *nand);
-extern void nand_print_bad(struct nand_chip *nand);
-extern int nand_read_oob(struct nand_chip *nand, size_t ofs,
-			       size_t len, size_t *retlen, u_char *buf);
-extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
-				size_t len, size_t *retlen, const u_char *buf);
-
-
-int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-    int rcode = 0;
-
-    switch (argc) {
-    case 0:
-    case 1:
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    case 2:
-	if (strcmp(argv[1],"info") == 0) {
-		int i;
-
-		putc ('\n');
-
-		for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
-			if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
-				continue; /* list only known devices */
-			printf ("Device %d: ", i);
-			nand_print(&nand_dev_desc[i]);
-		}
-		return 0;
-
-	} else if (strcmp(argv[1],"device") == 0) {
-		if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
-			puts ("\nno devices available\n");
-			return 1;
-		}
-		printf ("\nDevice %d: ", curr_device);
-		nand_print(&nand_dev_desc[curr_device]);
-		return 0;
-
-	} else if (strcmp(argv[1],"bad") == 0) {
-		if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
-			puts ("\nno devices available\n");
-			return 1;
-		}
-		printf ("\nDevice %d bad blocks:\n", curr_device);
-		nand_print_bad(&nand_dev_desc[curr_device]);
-		return 0;
-
-	}
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    case 3:
-	if (strcmp(argv[1],"device") == 0) {
-		int dev = (int)simple_strtoul(argv[2], NULL, 10);
-
-		printf ("\nDevice %d: ", dev);
-		if (dev >= CFG_MAX_NAND_DEVICE) {
-			puts ("unknown device\n");
-			return 1;
-		}
-		nand_print(&nand_dev_desc[dev]);
-		/*nand_print (dev);*/
-
-		if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
-			return 1;
-		}
-
-		curr_device = dev;
-
-		puts ("... is now current device\n");
-
-		return 0;
-	}
-	else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
-		struct nand_chip* nand = &nand_dev_desc[curr_device];
-		ulong off = 0;
-		ulong size = nand->totlen;
-		int ret;
-
-		printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
-			curr_device, off, size);
-
-		ret = nand_legacy_erase (nand, off, size, 1);
-
-		printf("%s\n", ret ? "ERROR" : "OK");
-
-		return ret;
-	}
-
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    default:
-	/* at least 4 args */
-
-	if (strncmp(argv[1], "read", 4) == 0 ||
-	    strncmp(argv[1], "write", 5) == 0) {
-		ulong addr = simple_strtoul(argv[2], NULL, 16);
-		ulong off  = simple_strtoul(argv[3], NULL, 16);
-		ulong size = simple_strtoul(argv[4], NULL, 16);
-		int cmd    = (strncmp(argv[1], "read", 4) == 0) ?
-				NANDRW_READ : NANDRW_WRITE;
-		int ret, total;
-		char* cmdtail = strchr(argv[1], '.');
-
-		if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
-			/* read out-of-band data */
-			if (cmd & NANDRW_READ) {
-				ret = nand_read_oob(nand_dev_desc + curr_device,
-						    off, size, (size_t *)&total,
-						    (u_char*)addr);
-			}
-			else {
-				ret = nand_write_oob(nand_dev_desc + curr_device,
-						     off, size, (size_t *)&total,
-						     (u_char*)addr);
-			}
-			return ret;
-		}
-		else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks */
-		else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
-			if (cmd & NANDRW_READ)
-				cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
-		}
-#ifdef SXNI855T
-		/* need ".e" same as ".j" for compatibility with older units */
-		else if (cmdtail && !strcmp(cmdtail, ".e"))
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks */
-#endif
-#ifdef CFG_NAND_SKIP_BAD_DOT_I
-		/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
-		/* ".i" for image -> read skips bad block (no 0xff) */
-		else if (cmdtail && !strcmp(cmdtail, ".i")) {
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
-			if (cmd & NANDRW_READ)
-				cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
-		}
-#endif /* CFG_NAND_SKIP_BAD_DOT_I */
-		else if (cmdtail) {
-			printf ("Usage:\n%s\n", cmdtp->usage);
-			return 1;
-		}
-
-		printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
-			(cmd & NANDRW_READ) ? "read" : "write",
-			curr_device, off, size);
-
-		ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size,
-			     (size_t *)&total, (u_char*)addr);
-
-		printf (" %d bytes %s: %s\n", total,
-			(cmd & NANDRW_READ) ? "read" : "written",
-			ret ? "ERROR" : "OK");
-
-		return ret;
-	} else if (strcmp(argv[1],"erase") == 0 &&
-		   (argc == 4 || strcmp("clean", argv[2]) == 0)) {
-		int clean = argc == 5;
-		ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
-		ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
-		int ret;
-
-		printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
-			curr_device, off, size);
-
-		ret = nand_legacy_erase (nand_dev_desc + curr_device,
-					off, size, clean);
-
-		printf("%s\n", ret ? "ERROR" : "OK");
-
-		return ret;
-	} else {
-		printf ("Usage:\n%s\n", cmdtp->usage);
-		rcode = 1;
-	}
-
-	return rcode;
-    }
-}
-
-U_BOOT_CMD(
-	nand,	5,	1,	do_nand,
-	"nand    - legacy NAND sub-system\n",
-	"info  - show available NAND devices\n"
-	"nand device [dev] - show or set current device\n"
-	"nand read[.jffs2[s]]  addr off size\n"
-	"nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
-	"    at offset `off' to/from memory address `addr'\n"
-	"nand erase [clean] [off size] - erase `size' bytes from\n"
-	"    offset `off' (entire device if not specified)\n"
-	"nand bad - show bad blocks\n"
-	"nand read.oob addr off size - read out-of-band data\n"
-	"nand write.oob addr off size - read out-of-band data\n"
+	"boot from NAND device",
+	"[partition] | [[[loadAddr] dev] offset]"
 );
-
-int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	char *boot_device = NULL;
-	char *ep;
-	int dev;
-	ulong cnt;
-	ulong addr;
-	ulong offset = 0;
-	image_header_t *hdr;
-	int rcode = 0;
-	switch (argc) {
-	case 1:
-		addr = CFG_LOAD_ADDR;
-		boot_device = getenv ("bootdevice");
-		break;
-	case 2:
-		addr = simple_strtoul(argv[1], NULL, 16);
-		boot_device = getenv ("bootdevice");
-		break;
-	case 3:
-		addr = simple_strtoul(argv[1], NULL, 16);
-		boot_device = argv[2];
-		break;
-	case 4:
-		addr = simple_strtoul(argv[1], NULL, 16);
-		boot_device = argv[2];
-		offset = simple_strtoul(argv[3], NULL, 16);
-		break;
-	default:
-		printf ("Usage:\n%s\n", cmdtp->usage);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	if (!boot_device) {
-		puts ("\n** No boot device **\n");
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	dev = simple_strtoul(boot_device, &ep, 16);
-
-	if ((dev >= CFG_MAX_NAND_DEVICE) ||
-	    (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
-		printf ("\n** Device %d not available\n", dev);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
-		dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
-		offset);
-
-	if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
-			SECTORSIZE, NULL, (u_char *)addr)) {
-		printf ("** Read error on %d\n", dev);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	hdr = (image_header_t *)addr;
-
-	if (ntohl(hdr->ih_magic) == IH_MAGIC) {
-
-		print_image_hdr (hdr);
-
-		cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
-		cnt -= SECTORSIZE;
-	} else {
-		printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic));
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
-			offset + SECTORSIZE, cnt, NULL,
-			(u_char *)(addr+SECTORSIZE))) {
-		printf ("** Read error on %d\n", dev);
-		SHOW_BOOT_PROGRESS (-1);
-		return 1;
-	}
-
-	/* Loading ok, update default load address */
-
-	load_addr = addr;
-
-	/* Check if we should attempt an auto-start */
-	if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
-		char *local_args[2];
-		extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-
-		local_args[0] = argv[0];
-		local_args[1] = NULL;
-
-		printf ("Automatic boot of image at addr 0x%08lx ...\n", addr);
-
-		do_bootm (cmdtp, 0, 1, local_args);
-		rcode = 1;
-	}
-	return rcode;
-}
-
-U_BOOT_CMD(
-	nboot,	4,	1,	do_nandboot,
-	"nboot   - boot from NAND device\n",
-	"loadAddr dev\n"
-);
-
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
-#endif /* CFG_NAND_LEGACY */
diff --git a/common/cmd_phy.c b/common/cmd_phy.c
new file mode 100644
index 0000000..e3e38ec
--- /dev/null
+++ b/common/cmd_phy.c
@@ -0,0 +1,430 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/types.h>
+
+#ifdef CONFIG_PCIE_PHY
+
+/* PCIe PHY registers */
+#define PCIE_PHY_PARALLEL_CR_CTRL_PORT_ADDR	0x00	/* CR_ADDR */
+#define PCIE_PHY_PARALLEL_CR_CTRL_PORT_DATA	0x04	/* CR_DATA */
+#define PCIE_PHY_POWER_GOOD_STATUS		0x08	/* PG_STS */
+#define PCIE_PHY_MPLL_CTRL			0x0C	/* MPLL_CTL */
+#define PCIE_PHY_TEST_CTRL			0x10	/* TEST_CTL */
+#define PCIE_PHY_TRANSMIT_LEVEL_CTRL		0x14	/* TX_LVL_CTL */
+#define PCIE_PHY_LANE0_TX_CTRL			0x18	/* TX0_CTL */
+#define PCIE_PHY_LANE1_TX_CTRL			0x1C	/* TX1_CTL */
+#define PCIE_PHY_LOS_LEVEL_CTRL			0x20	/* LOS_LVL_CTL */
+#define PCIE_PHY_LANE0_RX_CTRL			0x24	/* RX0_CTL */
+#define PCIE_PHY_LANE1_RX_CTRL			0x28	/* RX1_CTL */
+#define PCIE_PHY_TECHNOLOGY_CTRL		0x2C	/* TECH_CTL */
+#define PCIE_PHY_RESISTOR_TUNE_CTRL		0x30	/* RTUNE_CTL */
+#define PCIE_PHY_PCS_STATUS			0x34	/* PCS_STS */
+#define PCIE_PHY_PCS_CTRL			0x38	/* PCS_CTL */
+
+#define COMCERTO_CLK_DDR_PCIE_CLK_CNTRL		0x100B0018
+#define COMCERTO_CLK_CLK_PWR_DWN		0x100B0040
+#define COMCERTO_BLOCK_RESET_REG		0x100B0100 /* APB_VADDR((COMCERTO_APB_CLK_BASE + 0x100)) */
+
+#define USB_DIV_BYPASS		(1 << 30)
+#define IPSEC1_DIV_BYPASS	(1 << 29)
+#define IPSEC0_DIV_BYPASS	(1 << 28)
+#define PCIE_DIV_BYPASS		(1 << 27)
+#define DDR_DIV_BYPASS		(1 << 26)
+
+#define USB_DIV_VAL_OFFSET	20
+#define USB_DIV_VAL_MASK	(0x3f << USB_DIV_VAL_OFFSET)
+
+#define IPSEC_DIV1_VAL_OFFSET	16
+#define IPSEC_DIV1_VAL_MASK	(0xf << IPSEC_DIV0_VAL_OFFSET)
+
+#define IPSEC_DIV0_VAL_OFFSET	12
+#define IPSEC_DIV0_VAL_MASK	(0xf << IPSEC_DIV1_VAL_OFFSET)
+
+#define PCIE_DIV_VAL_OFFSET	8
+#define PCIE_DIV_VAL_MASK	(0xf << PCIE_DIV_VAL_OFFSET)
+
+#define DDR_DIV_VAL_OFFSET	4
+#define DDR_DIV_VAL_MASK	(0xf << DDR_DIV_VAL_OFFSET)
+
+
+#define USB_REF_RESET_N		(1 << 20)
+#define NO_BAL_DDR_REF_RST	(1 << 19)
+#define IPSEC2_AHB_RST		(1 << 18)
+#define RNG_RST			(1 << 17)
+#define IPSEC_CORE_RST		(1 << 16)
+#define IPSEC_AHB_RST		(1 << 15)
+#define USB_AHB_RESET_N		(1 << 14)
+#define TDM_REF_RST		(1 << 13)
+#define TDM_AHB_RST		(1 << 12)
+#define DDR_REF_RST		(1 << 11)
+#define DDR_AHB_RST		(1 << 10)
+#define PCIE1_REF_RST		(1 << 9)
+#define PCIE0_REF_RST		(1 << 8)
+#define PCIE1_AHB_RST		(1 << 7)
+#define PCIE0_AHB_RST		(1 << 6)
+#define GEMAC1_PHY_RST		(1 << 5)
+#define GEMAC0_PHY_RST		(1 << 4)
+#define GEMAC1_AHB_RST		(1 << 3)
+#define GEMAC0_AHB_RST		(1 << 2)
+#define ARM1_AHB_RST		(1 << 1)
+#define ARM0_AHB_RST		(1 << 0)
+
+#define USB_MUX_SEL		(1 << 3)
+#define IPSEC_MUX_SEL		(1 << 2)
+#define PCIE_MUX_SEL		(1 << 1)
+#define DDR_MUX_SEL		(1 << 0)
+
+
+#define USB_REFCLK_PD		(1 << 24)
+#define USB_AHBCLK_PD		(1 << 19)
+#define PCIE1_AHBCLK_PD		(1 << 15)
+#define PCIE0_AHBCLK_PD		(1 << 14)
+#define PCIE_REFCLK_NP_PD	(1 << 6)
+
+#define writel(val, addr)	*(volatile u32 *)(addr) = (val)
+#define readl(addr) 		*(volatile u32 *)(addr)
+
+void *pcie_phy_baseaddr = (void *)0x10060000;
+
+static u16 pcie_phy_reg_read(u16 addr)
+{
+	writel(addr, pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_ADDR);
+	return (u16)(readl(pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_DATA) & 0xffff);
+}
+
+static void pcie_phy_reg_write(u16 val, u16 addr)
+{
+	writel(addr, pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_ADDR);
+	writel(val, pcie_phy_baseaddr + PCIE_PHY_PARALLEL_CR_CTRL_PORT_DATA);
+}
+
+
+int do_txlvl (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 tx_level;
+
+	if (argc < 2)
+		return -1;
+
+	tx_level = simple_strtoul(argv[1], NULL, 16) & 0x1f;
+
+	writel(tx_level, pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL);
+
+	printf("%x=%x", pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL, readl(pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL));
+}
+
+U_BOOT_CMD(
+	txlvl,   2,              0,      do_txlvl,
+	"txlvl    - sets tx level\n",
+);
+
+#if 0
+int do_loopback (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 tx_level;
+
+	if (argc < 2)
+		return -1;
+
+
+}
+
+U_BOOT_CMD(
+	txlvl,   2,              0,      do_txlvl,
+	"txlvl    - start phy BERT test\n",
+);
+#endif
+
+
+int do_phytest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+	u16 type, pat0, val;
+
+	if (argc < 3)
+		return -1;
+
+	type = simple_strtoul(argv[1], NULL, 16) & 0xffff;
+	pat0 = simple_strtoul(argv[2], NULL, 16) & 0xffff;
+
+	printf("type(%x), pat0(%x)\n", type, pat0);
+
+	/* Enable pattern output */
+	pcie_phy_reg_write((type & 0x7) | ((pat0 & 0x3ff) << 4), 0x2110);
+
+	/* Enable pattern matching and sync */
+	pcie_phy_reg_write((type & 0x7) | (1 << 3), 0x2118);
+
+	/* disable sync */
+	pcie_phy_reg_write((type & 0x7), 0x2118);
+
+	pcie_phy_reg_write((type & 0x7) | (1 << 3), 0x2118);
+
+	/* disable sync */
+	pcie_phy_reg_write((type & 0x7), 0x2118);
+
+	for (i = 0; i < 1000; i++) {
+		udelay(1000);
+
+		val = pcie_phy_reg_read(0x2119);
+		if ((val & 0x8000))
+			printf("error count %x\n", (val & 0x7fff) * 128);
+		else
+			printf("error count %x\n", (val & 0x7fff));
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	phytest,   3,              0,      do_phytest,
+	"phytest    - start phy BERT test\n",
+);
+
+int do_initphy (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 val;
+
+	u32 ncy = 0x4 & 0x1f;
+	u32 ncy5 = 0x0 & 0x3;
+	u32 prescale = 0x0 & 0x3;
+
+
+	/* Put block into reset */
+	writel(readl(COMCERTO_BLOCK_RESET_REG) & ~(PCIE1_REF_RST | PCIE0_REF_RST | PCIE1_AHB_RST | PCIE0_AHB_RST), COMCERTO_BLOCK_RESET_REG);
+
+	/* Power up clocks */
+	writel(readl(COMCERTO_CLK_CLK_PWR_DWN) & ~(PCIE_REFCLK_NP_PD | PCIE0_AHBCLK_PD | PCIE1_AHBCLK_PD), COMCERTO_CLK_CLK_PWR_DWN);
+
+	/* Set reference clock to 250/4 = 62.5 MHz */
+	val = readl(COMCERTO_CLK_DDR_PCIE_CLK_CNTRL);
+
+	val &= ~(PCIE_DIV_VAL_MASK | PCIE_DIV_BYPASS);
+	val |= 4 << PCIE_DIV_VAL_OFFSET;
+
+	writel(val, COMCERTO_CLK_DDR_PCIE_CLK_CNTRL);
+
+	/* Switch to clock output */
+	writel(val & ~PCIE_MUX_SEL, COMCERTO_CLK_DDR_PCIE_CLK_CNTRL);
+
+	/* Take block out of reset */
+	writel(readl(COMCERTO_BLOCK_RESET_REG) | (PCIE1_REF_RST | PCIE0_REF_RST | PCIE1_AHB_RST | PCIE0_AHB_RST), COMCERTO_BLOCK_RESET_REG);
+
+	udelay(10);
+
+
+#if 0
+	/* Synopsys recommended values */
+	u32 tx_level = 0x6 & 0x1f;
+	u32 tx_boost = 0xa & 0xf;
+	u32 tx_atten = 0x0 & 0x7;
+	u32 tx_edge_rate = 0x0 & 0x3;
+	u32 tx_clk_align = 0x0 & 0x1;
+
+	u32 los_lvl = 0x14 & 0x1f;
+
+	u32 rx_equal_val = 0x2 & 0x7;
+#elif 1
+	/* Default values */
+	u32 tx_level = 0xa & 0x1f;
+	u32 tx_boost = 0xb & 0xf;
+	u32 tx_atten = 0x0 & 0x7;
+	u32 tx_edge_rate = 0x0 & 0x3;
+	u32 tx_clk_align = 0x0 & 0x1;
+
+	u32 los_lvl = 0x11 & 0x1f;
+
+	u32 rx_equal_val = 0x2 & 0x7;
+#else
+	/* Custom values */
+/* 	u32 tx_level = 0xa & 0x1f; */
+ 	u32 tx_level = 0x13 & 0x1f;
+	u32 tx_boost = 0xb & 0xf;
+	u32 tx_atten = 0x0 & 0x7;
+	u32 tx_edge_rate = 0x0 & 0x3;
+	u32 tx_clk_align = 0x0 & 0x1;
+
+	u32 los_lvl = 0x10 & 0x1f;
+
+	u32 rx_equal_val = 0x2 & 0x7;
+#endif
+
+	/* Baud rate = 62.5MHz * MPLL_divisor / 0.5 = 62.5MHz * 20 / 0.5 = 2.5GHz */
+	writel((prescale << 1) | (ncy5 << 3) | (ncy << 5), pcie_phy_baseaddr + PCIE_PHY_MPLL_CTRL);
+
+	writel(tx_level, pcie_phy_baseaddr + PCIE_PHY_TRANSMIT_LEVEL_CTRL);
+#if 0
+	writel(tx_edge_rate | (tx_boost << 2) | (tx_atten << 6) | (tx_clk_align << 9), pcie_phy_baseaddr + PCIE_PHY_LANE0_TX_CTRL);
+
+	writel(tx_edge_rate | (tx_boost << 2) | (tx_atten << 6) | (tx_clk_align << 9), pcie_phy_baseaddr + PCIE_PHY_LANE1_TX_CTRL);
+
+	writel(los_lvl, pcie_phy_baseaddr + PCIE_PHY_LOS_LEVEL_CTRL);
+
+	writel(rx_equal_val, pcie_phy_baseaddr + PCIE_PHY_LANE0_RX_CTRL);
+	writel(rx_equal_val, pcie_phy_baseaddr + PCIE_PHY_LANE1_RX_CTRL);
+#endif
+	writel(0x00000000, pcie_phy_baseaddr + PCIE_PHY_PCS_CTRL);
+#if 1
+	/* Manual calibration of rx resistor */
+	udelay(1000);
+
+	writel(0x1, pcie_phy_baseaddr + PCIE_PHY_RESISTOR_TUNE_CTRL);
+
+	udelay(100);
+
+	writel(0x0, pcie_phy_baseaddr + PCIE_PHY_RESISTOR_TUNE_CTRL);
+#endif
+ 
+#if 0
+ 	/* Set both phys in digital loopback */
+ 	val = pcie_phy_reg_read(0x2030);
+ 	val |= (1 << 4);
+ 	pcie_phy_reg_write(val, 0x2030);
+ 
+ 	printk("lane0.rx_ana.ctrl %x\n", pcie_phy_reg_read(0x2030));
+ 
+ 	val = pcie_phy_reg_read(0x2130);
+ 	val |= (1 << 4);
+ 	pcie_phy_reg_write(val, 0x2130);
+ 
+ 	printk("lane1.rx_ana.ctrl %x\n", pcie_phy_reg_read(0x2130));
+#endif
+ 
+	return 0;
+}
+
+U_BOOT_CMD(
+	initphy,   1,              0,      do_initphy,
+	"initphy    - initialize PCIe phy\n",
+);
+
+
+int do_dumpreg (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u16 val;
+
+ 	printf("clock.rtune_ctl %x\n", pcie_phy_reg_read(0x9));
+ 
+ 	val = pcie_phy_reg_read(0xe);
+ 	printf("clock.freq_stat(%x) prop_ctl(%x) int_ctl(%x) ncy5(%x) ncy(%x) prescale(%x)\n",
+ 			val, (val & 0x7), (val >> 3) & 0x7, (val >> 6) & 0x3, (val >> 8) & 0x1f, (val >> 13) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0xf);
+ 	printf("clock.ctl_stat(%x) use_refclk_dat(%x) mpll_clk_off(%x) mpll_pwron(%x) mpll_ss_en(%x) cko_alive_con(%x) cko_word_con(%x) rtune_to_tune(%x) wide_xface(%x) vph_is_3p3(%x) vp_is_1p2(%x) fast_tech(%x)\n",
+ 			val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1, (val >> 3) & 0x1, (val >> 4) & 0x3,
+ 			(val >> 6) & 0x7, (val >> 10) & 0x1, (val >> 11) & 0x1, (val >> 12) & 0x1, (val >> 13) & 0x1,
+ 			(val >> 14) & 0x1);
+ 
+ 	printf("clock.lvl_stat %x\n", pcie_phy_reg_read(0x10));
+ 	printf("clock.ctl_ovrd %x\n", pcie_phy_reg_read(0x13));
+ 	printf("clock.lvl_ovrd %x\n", pcie_phy_reg_read(0x14));
+ 	printf("clock.creg_ovrd %x\n", pcie_phy_reg_read(0x15));
+ 	printf("clock.mpll_ctl %x\n", pcie_phy_reg_read(0x16));
+ 	printf("clock.mpll_tst %x\n", pcie_phy_reg_read(0x17));
+ 
+ 	val = pcie_phy_reg_read(0x2001);
+ 	printf("lane0.tx_stat(%x) tx_cko_en(%x) tx_en(%x) tx_clk_align(%x) tx_boost(%x) tx_atten(%x) tx_edgerate(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x7, (val >> 4) & 0x1,
+ 				(val >> 6) & 0xf, (val >> 10) & 0x7, (val >> 13) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2101);
+ 	printf("lane1.tx_stat(%x) tx_cko_en(%x) tx_en(%x) tx_clk_align(%x) tx_boost(%x) tx_atten(%x) tx_edgerate(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x7, (val >> 4) & 0x1,
+ 				(val >> 6) & 0xf, (val >> 10) & 0x7, (val >> 13) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2002);
+ 	printf("lane0.rx_stat(%x) half_rate(%x) rx_pll_pwron(%x) rx_en(%x) rx_align_en(%x) rx_term_en(%x) rx_equal_val(%x) rx_dpll_mode(%x) dpll_reset(%x) los_ctl(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1, (val >> 5) & 0x7, (val >> 8) & 0x7, (val >> 11) & 0x1,
+ 				(val >> 12) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2102);
+ 	printf("lane1.rx_stat(%x) half_rate(%x) rx_pll_pwron(%x) rx_en(%x) rx_align_en(%x) rx_term_en(%x) rx_equal_val(%x) rx_dpll_mode(%x) dpll_reset(%x) los_ctl(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1, (val >> 5) & 0x7, (val >> 8) & 0x7, (val >> 11) & 0x1,
+ 				(val >> 12) & 0x3);
+ 
+ 	val = pcie_phy_reg_read(0x2003);
+ 	printf("lane0.out_stat(%x) rx_valid(%x) rx_pll_state(%x) los(%x) tx_done(%x) tx_rxpres(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1);
+ 
+ 	val = pcie_phy_reg_read(0x2103);
+ 	printf("lane1.out_stat(%x) rx_valid(%x) rx_pll_state(%x) los(%x) tx_done(%x) tx_rxpres(%x)\n",
+ 				val, val & 0x1, (val >> 1) & 0x1, (val >> 2) & 0x1,
+ 				(val >> 3) & 0x1, (val >> 4) & 0x1);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	dumpreg,   1,             1,      do_dumpreg,
+	"dumpreg    - dumps all PCIe phy registers\n",
+);
+
+int do_writereg (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u16 val, addr;
+
+	if (argc < 3)
+		return -1;
+
+	val = simple_strtoul(argv[1], NULL, 16) & 0xffff;
+	addr = simple_strtoul(argv[2], NULL, 16) & 0xffff;
+
+	printf("%x=%x\n", addr, val);
+
+	pcie_phy_reg_write(val, addr);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	writereg,   3,              0,      do_writereg,
+	"writereg    - writes PCIe phy reg\n",
+);
+
+int do_readreg (cmd_tbl_t *cmdtp, int flag,
+		 int	argc, char *argv[])
+{
+	u16 addr;
+
+	if (argc < 2)
+		return -1;
+
+	addr = simple_strtoul(argv[1], NULL, 16) & 0xffff;
+
+	printf("%x=%x\n", addr, pcie_phy_reg_read(addr));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	readreg,   2,             1,      do_readreg,
+	"readreg    - read PCIe phy reg\n",
+);
+
+#endif
diff --git a/common/cmd_spi.c b/common/cmd_spi.c
index a6fdf7f..9eaf152 100644
--- a/common/cmd_spi.c
+++ b/common/cmd_spi.c
@@ -31,113 +31,70 @@
 
 #if (CONFIG_COMMANDS & CFG_CMD_SPI)
 
-/*-----------------------------------------------------------------------
- * Definitions
- */
-
 #ifndef MAX_SPI_BYTES
-#   define MAX_SPI_BYTES 32	/* Maximum number of bytes we can handle */
+#   define MAX_SPI_BYTES 32     /* Maximum number of bytes we can handle */
 #endif
-
-/*
- * External table of chip select functions (see the appropriate board
- * support for the actual definition of the table).
- */
-extern spi_chipsel_type spi_chipsel[];
-extern int spi_chipsel_cnt;
-
-/*
- * Values from last command.
- */
-static int   device;
-static int   bitlen;
 static uchar dout[MAX_SPI_BYTES];
 static uchar din[MAX_SPI_BYTES];
 
-/*
- * SPI read/write
- *
- * Syntax:
- *   spi {dev} {num_bits} {dout}
- *     {dev} is the device number for controlling chip select (see TBD)
- *     {num_bits} is the number of bits to send & receive (base 10)
- *     {dout} is a hexadecimal string of data to send
- * The command prints out the hexadecimal string received via SPI.
- */
-
 int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	char  *cp = 0;
-	uchar tmp;
-	int   j;
-	int   rcode = 0;
+        int   rcode = 0;
+        int i;
+	int cs;
+	int len;
 
-	/*
-	 * We use the last specified parameters, unless new ones are
-	 * entered.
-	 */
-
-	if ((flag & CMD_FLAG_REPEAT) == 0)
+        if (argc < 3)
 	{
-		if (argc >= 2)
-			device = simple_strtoul(argv[1], NULL, 10);
-		if (argc >= 3)
-			bitlen = simple_strtoul(argv[2], NULL, 10);
-		if (argc >= 4) {
-			cp = argv[3];
-			for(j = 0; *cp; j++, cp++) {
-				tmp = *cp - '0';
-				if(tmp > 9)
-					tmp -= ('A' - '0') - 10;
-				if(tmp > 15)
-					tmp -= ('a' - 'A');
-				if(tmp > 15) {
-					printf("Hex conversion error on %c, giving up.\n", *cp);
-					return 1;
-				}
-				if((j % 2) == 0)
-					dout[j / 2] = (tmp << 4);
-				else
-					dout[j / 2] |= tmp;
-			}
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (strcmp(argv[1],"read") == 0) {
+		cs = simple_strtoul(argv[2], NULL, 10);
+		if(argc == 4)
+		{		
+			len = simple_strtoul(argv[3], NULL, 16);
 		}
-	}
-
-	if ((device < 0) || (device >=  spi_chipsel_cnt)) {
-		printf("Invalid device %d, giving up.\n", device);
-		return 1;
-	}
-	if ((bitlen < 0) || (bitlen >  (MAX_SPI_BYTES * 8))) {
-		printf("Invalid bitlen %d, giving up.\n", bitlen);
-		return 1;
-	}
-
-	debug ("spi_chipsel[%d] = %08X\n",
-		device, (uint)spi_chipsel[device]);
-
-	if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) {
-		printf("Error with the SPI transaction.\n");
-		rcode = 1;
-	} else {
-		cp = (char *)din;
-		for(j = 0; j < ((bitlen + 7) / 8); j++) {
-			printf("%02X", *cp++);
+		else
+		{
+			printf ("Usage:\n%s\n", cmdtp->usage);
+		}
+		printf("Read cs %d: ",cs);
+		for(i = 0; i < len; i++)
+		{
+			c2k_spi_read(cs, &dout, 1);
+			printf("%02x ",dout[0]);
 		}
 		printf("\n");
 	}
 
-	return rcode;
+	else if (strcmp(argv[1],"write") == 0) {
+		cs = simple_strtoul(argv[2], NULL, 10);
+		
+		printf("Write cs %d: ",cs);
+		for (i = 3; i < argc; i++)
+		{
+			din[0] = simple_strtoul(argv[i], NULL, 16);
+			c2k_spi_write(cs, &din, 1);
+			printf("%02x ",din[0]);
+		}
+		printf("\n");
+	}
+	else
+	{
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+	
 }
 
 /***************************************************/
 
 U_BOOT_CMD(
-	sspi,	5,	1,	do_spi,
-	"sspi    - SPI utility commands\n",
-	"<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n"
-	"<device>  - Identifies the chip select of the device\n"
-	"<bit_len> - Number of bits to send (base 10)\n"
-	"<dout>    - Hexadecimal string that gets sent\n"
+	spi,	32,	1,	do_spi,
+	"spi     - SPI utility commands\n",
+	"spi read chipselect len - Read len number of bytes from the SPI device \n"
+	"spi write chipselect byte0 <byte1> <byte2> ... - Write bytes to the SPI device\n"
 );
-
-#endif	/* CFG_CMD_SPI */
+#endif
diff --git a/common/command.c b/common/command.c
index e917975..7a9b2e9 100644
--- a/common/command.c
+++ b/common/command.c
@@ -27,12 +27,48 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/arch/bsp.h>
+
+#if defined (CONFIG_COMCERTO_1000)
+extern unsigned char comcerto_part_no[8];
+#endif
 
 int
 do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	extern char version_string[];
+	int clk;
+
+	printf ("-----------------------------\n");
 	printf ("\n%s\n", version_string);
+
+#if defined (CONFIG_COMCERTO_1000)
+	clk = HAL_get_arm_pll();
+	printf ("ARM PLL: %0d Hz\n", clk);
+	clk = HAL_get_ahb_pll();
+	printf ("AHB PLL: %0d Hz\n", clk);
+	clk = HAL_get_phy_pll();
+	printf ("PHY PLL: %0d Hz\n\n", clk);
+#endif
+#if 0
+	clk = HAL_get_arm_clk();
+	printf ("ARM Clock: %0d Hz\n", clk);
+	clk = HAL_get_amba_clk();
+	printf ("AHB Clock: %d Hz\n", clk);
+#endif
+#if defined (CONFIG_COMCERTO_1000)
+	clk = HAL_get_ddr_clk();
+	printf ("DDR Clock: %d Hz\n", clk);
+	clk = HAL_get_ipsec_clk();
+	printf ("IPSEC Clock: %d Hz\n", clk);
+#endif
+#if 0
+        printf ("DDR Size : %d MByte\n", get_ddr_size() / (1024 * 1024));
+#endif
+#if defined(CONFIG_M8326XG) || defined(CONFIG_M8325XG) || defined(CONFIG_M8324XG)
+        printf ("Part No: %s\n", comcerto_part_no);
+#endif
+	printf ("-----------------------------\n");
 	return 0;
 }
 
diff --git a/common/env_flash.c b/common/env_flash.c
index 1674b30..4c28da2 100644
--- a/common/env_flash.c
+++ b/common/env_flash.c
@@ -182,6 +182,9 @@
 				up_data);
 			goto Done;
 		}
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+		board_map(NULL, ((long)flash_addr_new + CFG_ENV_SIZE));
+#endif
 		memcpy(saved_data,
 			(void *)((long)flash_addr_new + CFG_ENV_SIZE), up_data);
 		debug ("Data (start 0x%x, len 0x%x) saved at 0x%x\n",
@@ -265,6 +268,11 @@
 	if(flash_probe() == 0)
 		goto bad_flash;
 #endif
+
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	board_map(NULL, env_ptr);
+#endif
+
 	if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
 		gd->env_addr  = (ulong)&(env_ptr->data);
 		gd->env_valid = 1;
@@ -302,6 +310,10 @@
 		"sect_addr: %08lX  env_addr: %08lX  offset: %08lX\n",
 		flash_sect_addr, (ulong)flash_addr, flash_offset);
 
+#ifdef CFG_FLASH_COMPLEX_MAPPINGS
+	board_map(NULL, flash_sect_addr);
+#endif
+
 	/* copy old contents to temporary buffer */
 	memcpy (env_buffer, (void *)flash_sect_addr, CFG_ENV_SECT_SIZE);
 
diff --git a/common/image.c b/common/image.c
new file mode 100644
index 0000000..9ff4c2d
--- /dev/null
+++ b/common/image.c
@@ -0,0 +1,3215 @@
+/*
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <watchdog.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+#endif
+
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
+#include <rtc.h>
+#endif
+
+#include <image.h>
+
+#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+#if defined(CONFIG_FIT)
+#include <u-boot/md5.h>
+#include <sha1.h>
+
+static int fit_check_ramdisk(const void *fit, int os_noffset,
+		uint8_t arch, int verify);
+#endif
+
+#ifdef CONFIG_CMD_BDI
+extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+
+#include <bootstage.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
+						int verify);
+#else
+#include "mkimage.h"
+#include <u-boot/md5.h>
+#include <time.h>
+#include <image.h>
+#endif /* !USE_HOSTCC*/
+
+static const table_entry_t uimage_arch[] = {
+	{	IH_ARCH_INVALID,	NULL,		"Invalid ARCH",	},
+	{	IH_ARCH_ALPHA,		"alpha",	"Alpha",	},
+	{	IH_ARCH_ARM,		"arm",		"ARM",		},
+	{	IH_ARCH_I386,		"x86",		"Intel x86",	},
+	{	IH_ARCH_IA64,		"ia64",		"IA64",		},
+	{	IH_ARCH_M68K,		"m68k",		"M68K",		},
+	{	IH_ARCH_MICROBLAZE,	"microblaze",	"MicroBlaze",	},
+	{	IH_ARCH_MIPS,		"mips",		"MIPS",		},
+	{	IH_ARCH_MIPS64,		"mips64",	"MIPS 64 Bit",	},
+	{	IH_ARCH_NIOS2,		"nios2",	"NIOS II",	},
+	{	IH_ARCH_PPC,		"powerpc",	"PowerPC",	},
+	{	IH_ARCH_PPC,		"ppc",		"PowerPC",	},
+	{	IH_ARCH_S390,		"s390",		"IBM S390",	},
+	{	IH_ARCH_SH,		"sh",		"SuperH",	},
+	{	IH_ARCH_SPARC,		"sparc",	"SPARC",	},
+	{	IH_ARCH_SPARC64,	"sparc64",	"SPARC 64 Bit",	},
+	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
+	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
+	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
+	{	IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
+	{	-1,			"",		"",		},
+};
+
+static const table_entry_t uimage_os[] = {
+	{	IH_OS_INVALID,	NULL,		"Invalid OS",		},
+	{	IH_OS_LINUX,	"linux",	"Linux",		},
+#if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
+	{	IH_OS_LYNXOS,	"lynxos",	"LynxOS",		},
+#endif
+	{	IH_OS_NETBSD,	"netbsd",	"NetBSD",		},
+	{	IH_OS_OSE,	"ose",		"Enea OSE",		},
+	{	IH_OS_RTEMS,	"rtems",	"RTEMS",		},
+	{	IH_OS_U_BOOT,	"u-boot",	"U-Boot",		},
+#if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
+	{	IH_OS_QNX,	"qnx",		"QNX",			},
+	{	IH_OS_VXWORKS,	"vxworks",	"VxWorks",		},
+#endif
+#if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC)
+	{	IH_OS_INTEGRITY,"integrity",	"INTEGRITY",		},
+#endif
+#ifdef USE_HOSTCC
+	{	IH_OS_4_4BSD,	"4_4bsd",	"4_4BSD",		},
+	{	IH_OS_DELL,	"dell",		"Dell",			},
+	{	IH_OS_ESIX,	"esix",		"Esix",			},
+	{	IH_OS_FREEBSD,	"freebsd",	"FreeBSD",		},
+	{	IH_OS_IRIX,	"irix",		"Irix",			},
+	{	IH_OS_NCR,	"ncr",		"NCR",			},
+	{	IH_OS_OPENBSD,	"openbsd",	"OpenBSD",		},
+	{	IH_OS_PSOS,	"psos",		"pSOS",			},
+	{	IH_OS_SCO,	"sco",		"SCO",			},
+	{	IH_OS_SOLARIS,	"solaris",	"Solaris",		},
+	{	IH_OS_SVR4,	"svr4",		"SVR4",			},
+#endif
+	{	-1,		"",		"",			},
+};
+
+static const table_entry_t uimage_type[] = {
+	{	IH_TYPE_AISIMAGE,   "aisimage",   "Davinci AIS image",},
+	{	IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image",	},
+	{	IH_TYPE_FIRMWARE,   "firmware",	  "Firmware",		},
+	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
+	{	IH_TYPE_KERNEL,	    "kernel",	  "Kernel Image",	},
+	{	IH_TYPE_KERNEL_NOLOAD, "kernel_noload",  "Kernel Image (no loading done)", },
+	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
+	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
+	{	IH_TYPE_INVALID,    NULL,	  "Invalid Image",	},
+	{	IH_TYPE_MULTI,	    "multi",	  "Multi-File Image",	},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP SPL With GP CH",},
+	{	IH_TYPE_RAMDISK,    "ramdisk",	  "RAMDisk Image",	},
+	{	IH_TYPE_SCRIPT,     "script",	  "Script",		},
+	{	IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
+	{	IH_TYPE_UBLIMAGE,   "ublimage",   "Davinci UBL image",},
+	{	-1,		    "",		  "",			},
+};
+
+static const table_entry_t uimage_comp[] = {
+	{	IH_COMP_NONE,	"none",		"uncompressed",		},
+	{	IH_COMP_BZIP2,	"bzip2",	"bzip2 compressed",	},
+	{	IH_COMP_GZIP,	"gzip",		"gzip compressed",	},
+	{	IH_COMP_LZMA,	"lzma",		"lzma compressed",	},
+	{	IH_COMP_LZO,	"lzo",		"lzo compressed",	},
+	{	-1,		"",		"",			},
+};
+
+unsigned long crc32(unsigned long, const unsigned char *, uint);
+unsigned long crc32_wd(unsigned long, const unsigned char *, uint, uint);
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+static void genimg_print_time(time_t timestamp);
+#endif
+
+/*****************************************************************************/
+/* Legacy format routines */
+/*****************************************************************************/
+int image_check_hcrc(const image_header_t *hdr)
+{
+	ulong hcrc;
+	ulong len = image_get_header_size();
+	image_header_t header;
+
+	/* Copy header so we can blank CRC field for re-calculation */
+	memmove(&header, (char *)hdr, image_get_header_size());
+	image_set_hcrc(&header, 0);
+
+	hcrc = crc32(0, (unsigned char *)&header, len);
+
+	return (hcrc == image_get_hcrc(hdr));
+}
+
+int image_check_dcrc(const image_header_t *hdr)
+{
+	ulong data = image_get_data(hdr);
+	ulong len = image_get_data_size(hdr);
+	ulong dcrc = crc32_wd(0, (unsigned char *)data, len, CHUNKSZ_CRC32);
+
+	return (dcrc == image_get_dcrc(hdr));
+}
+
+/**
+ * image_multi_count - get component (sub-image) count
+ * @hdr: pointer to the header of the multi component image
+ *
+ * image_multi_count() returns number of components in a multi
+ * component image.
+ *
+ * Note: no checking of the image type is done, caller must pass
+ * a valid multi component image.
+ *
+ * returns:
+ *     number of components
+ */
+ulong image_multi_count(const image_header_t *hdr)
+{
+	ulong i, count = 0;
+	uint32_t *size;
+
+	/* get start of the image payload, which in case of multi
+	 * component images that points to a table of component sizes */
+	size = (uint32_t *)image_get_data(hdr);
+
+	/* count non empty slots */
+	for (i = 0; size[i]; ++i)
+		count++;
+
+	return count;
+}
+
+/**
+ * image_multi_getimg - get component data address and size
+ * @hdr: pointer to the header of the multi component image
+ * @idx: index of the requested component
+ * @data: pointer to a ulong variable, will hold component data address
+ * @len: pointer to a ulong variable, will hold component size
+ *
+ * image_multi_getimg() returns size and data address for the requested
+ * component in a multi component image.
+ *
+ * Note: no checking of the image type is done, caller must pass
+ * a valid multi component image.
+ *
+ * returns:
+ *     data address and size of the component, if idx is valid
+ *     0 in data and len, if idx is out of range
+ */
+void image_multi_getimg(const image_header_t *hdr, ulong idx,
+			ulong *data, ulong *len)
+{
+	int i;
+	uint32_t *size;
+	ulong offset, count, img_data;
+
+	/* get number of component */
+	count = image_multi_count(hdr);
+
+	/* get start of the image payload, which in case of multi
+	 * component images that points to a table of component sizes */
+	size = (uint32_t *)image_get_data(hdr);
+
+	/* get address of the proper component data start, which means
+	 * skipping sizes table (add 1 for last, null entry) */
+	img_data = image_get_data(hdr) + (count + 1) * sizeof(uint32_t);
+
+	if (idx < count) {
+		*len = uimage_to_cpu(size[idx]);
+		offset = 0;
+
+		/* go over all indices preceding requested component idx */
+		for (i = 0; i < idx; i++) {
+			/* add up i-th component size, rounding up to 4 bytes */
+			offset += (uimage_to_cpu(size[i]) + 3) & ~3 ;
+		}
+
+		/* calculate idx-th component data address */
+		*data = img_data + offset;
+	} else {
+		*len = 0;
+		*data = 0;
+	}
+}
+
+static void image_print_type(const image_header_t *hdr)
+{
+	const char *os, *arch, *type, *comp;
+
+	os = genimg_get_os_name(image_get_os(hdr));
+	arch = genimg_get_arch_name(image_get_arch(hdr));
+	type = genimg_get_type_name(image_get_type(hdr));
+	comp = genimg_get_comp_name(image_get_comp(hdr));
+
+	printf("%s %s %s (%s)\n", arch, os, type, comp);
+}
+
+/**
+ * image_print_contents - prints out the contents of the legacy format image
+ * @ptr: pointer to the legacy format image header
+ * @p: pointer to prefix string
+ *
+ * image_print_contents() formats a multi line legacy image contents description.
+ * The routine prints out all header fields followed by the size/offset data
+ * for MULTI/SCRIPT images.
+ *
+ * returns:
+ *     no returned results
+ */
+void image_print_contents(const void *ptr)
+{
+	const image_header_t *hdr = (const image_header_t *)ptr;
+	const char *p;
+
+#ifdef USE_HOSTCC
+	p = "";
+#else
+	p = "   ";
+#endif
+
+	printf("%sImage Name:   %.*s\n", p, IH_NMLEN, image_get_name(hdr));
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
+	printf("%sCreated:      ", p);
+	genimg_print_time((time_t)image_get_time(hdr));
+#endif
+	printf("%sImage Type:   ", p);
+	image_print_type(hdr);
+	printf("%sData Size:    ", p);
+	genimg_print_size(image_get_data_size(hdr));
+	printf("%sLoad Address: %08x\n", p, image_get_load(hdr));
+	printf("%sEntry Point:  %08x\n", p, image_get_ep(hdr));
+
+	if (image_check_type(hdr, IH_TYPE_MULTI) ||
+			image_check_type(hdr, IH_TYPE_SCRIPT)) {
+		int i;
+		ulong data, len;
+		ulong count = image_multi_count(hdr);
+
+		printf("%sContents:\n", p);
+		for (i = 0; i < count; i++) {
+			image_multi_getimg(hdr, i, &data, &len);
+
+			printf("%s   Image %d: ", p, i);
+			genimg_print_size(len);
+
+			if (image_check_type(hdr, IH_TYPE_SCRIPT) && i > 0) {
+				/*
+				 * the user may need to know offsets
+				 * if planning to do something with
+				 * multiple files
+				 */
+				printf("%s    Offset = 0x%08lx\n", p, data);
+			}
+		}
+	}
+}
+
+
+#ifndef USE_HOSTCC
+/**
+ * image_get_ramdisk - get and verify ramdisk image
+ * @rd_addr: ramdisk image start address
+ * @arch: expected ramdisk architecture
+ * @verify: checksum verification flag
+ *
+ * image_get_ramdisk() returns a pointer to the verified ramdisk image
+ * header. Routine receives image start address and expected architecture
+ * flag. Verification done covers data and header integrity and os/type/arch
+ * fields checking.
+ *
+ * If dataflash support is enabled routine checks for dataflash addresses
+ * and handles required dataflash reads.
+ *
+ * returns:
+ *     pointer to a ramdisk image header, if image was found and valid
+ *     otherwise, return NULL
+ */
+static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
+						int verify)
+{
+	const image_header_t *rd_hdr = (const image_header_t *)rd_addr;
+
+	if (!image_check_magic(rd_hdr)) {
+		puts("Bad Magic Number\n");
+		bootstage_error(BOOTSTAGE_ID_RD_MAGIC);
+		return NULL;
+	}
+
+	if (!image_check_hcrc(rd_hdr)) {
+		puts("Bad Header Checksum\n");
+		bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+		return NULL;
+	}
+
+	bootstage_mark(BOOTSTAGE_ID_RD_MAGIC);
+	image_print_contents(rd_hdr);
+
+	if (verify) {
+		puts("   Verifying Checksum ... ");
+		if (!image_check_dcrc(rd_hdr)) {
+			puts("Bad Data CRC\n");
+			bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM);
+			return NULL;
+		}
+		puts("OK\n");
+	}
+
+	bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM);
+
+	if (!image_check_os(rd_hdr, IH_OS_LINUX) ||
+	    !image_check_arch(rd_hdr, arch) ||
+	    !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) {
+		printf("No Linux %s Ramdisk Image\n",
+				genimg_get_arch_name(arch));
+		bootstage_error(BOOTSTAGE_ID_RAMDISK);
+		return NULL;
+	}
+
+	return rd_hdr;
+}
+#endif /* !USE_HOSTCC */
+
+/*****************************************************************************/
+/* Shared dual-format routines */
+/*****************************************************************************/
+#ifndef USE_HOSTCC
+int getenv_yesno(char *var)
+