blob: fa16b54440db82a0794aa969a7e26b3b83c10b53 [file] [log] [blame]
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio_c2000.h>
#include <asm/arch/exp-bus_c2000.h>
#include <asm/arch/clkcore_c2000.h>
#include <asm/arch/bsp.h>
DECLARE_GLOBAL_DATA_PTR;
#define EXP_CS0_SEG_SIZE_VAL 0x7FFF
#define A9_TIMER_LOAD 0x0
#define A9_TIMER_COUNTER 0x4
#define A9_TIMER_CNTRL 0x8
#define A9_TIMER_ENABLE (1<<0)
#define A9_TIMER_RELOAD (1<<1)
#define MAX_TIMER_COUNT 0xffffffff
void comcerto_pad_config();
void nor_hw_init(void)
{
*(volatile u32*) EXP_CS0_SEG_REG = EXP_CS0_SEG_SIZE_VAL;
*(volatile u32*) EXP_CS0_TMG1_REG = 0x03034007;
*(volatile u32*) EXP_CS0_TMG2_REG = 0x04040502;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
void nand_hw_init(void)
{
SoC_gpio_cfg(28, GPIO_TYPE_OUTPUT); /* NAND CE */
SoC_gpio_cfg(29, GPIO_TYPE_INPUT); /* NAND BR */
}
#endif
#if 0
void a9_timer_init(void)
{
*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_LOAD) = MAX_TIMER_COUNT;
*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_COUNTER) = MAX_TIMER_COUNT;
*(volatile u32*) (COMCERTO_A9_TIMER_BASE + A9_TIMER_CNTRL) = A9_TIMER_ENABLE | A9_TIMER_RELOAD;
}
#endif
void bsp_init(void)
{
int val;
comcerto_pad_config();
//DDRC ODT Source Select
*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG = ( (1 << 6) | (*(volatile u32*) COMCERTO_GPIO_MISC_PIN_SELECT_REG));
nor_hw_init();
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
SoC_nand_init();
#endif
#if 0
a9_timer_init();
#endif
}
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
}
int board_init(void)
{
/* arch number of Mindspeed Comcerto */
gd->bd->bi_arch_number = MACH_TYPE_COMCERTO;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x100;
gd->bd->bi_dram[0].start = 0x0;
gd->bd->bi_dram[0].size = 0x20000000; //512 MB
#if 0
c2k_zds_init();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
nand_hw_init();
#endif
return 0;
}