| commit | 0476bf3eb06a58b764a0c58fd6e74ec4e23e4ad5 | [log] [tgz] |
|---|---|---|
| author | Margarita Granov <margra@marvell.com> | Thu Oct 15 16:51:26 2015 +0200 |
| committer | Greg Poist <poist@google.com> | Thu Mar 24 11:59:54 2016 -0700 |
| tree | 02f2db45baff2da81cf130f2336e37c228753ec5 | |
| parent | 9f3d8138d02a52e545b25a51d36b5f483abc7c44 [diff] |
fix:ddr3libv2: Fix DDR3 Rank Control Register value calculation. Set mirroring bit is done for referenced CS Caelum topology is changed to be aligned with the fix: Change-Id: I6af113b8088b58a436cbfb124f7da1184e2adbf2 Signed-off-by: Margarita Granov <margra@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/24031 Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/24176 Reviewed-by: Omri Itach <omrii@marvell.com> Tested-by: Omri Itach <omrii@marvell.com>