tree 02f2db45baff2da81cf130f2336e37c228753ec5
parent 9f3d8138d02a52e545b25a51d36b5f483abc7c44
author Margarita Granov <margra@marvell.com> 1444920686 +0200
committer Greg Poist <poist@google.com> 1458845994 -0700

fix:ddr3libv2: Fix DDR3 Rank Control Register value calculation.

	Set mirroring bit is done for referenced CS
	Caelum topology is changed to be aligned with the fix:

Change-Id: I6af113b8088b58a436cbfb124f7da1184e2adbf2
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24031
Reviewed-by: Haim Boot <hayim@marvell.com>
Tested-by: Haim Boot <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24176
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>