)]}' { "commit": "0476bf3eb06a58b764a0c58fd6e74ec4e23e4ad5", "tree": "02f2db45baff2da81cf130f2336e37c228753ec5", "parents": [ "9f3d8138d02a52e545b25a51d36b5f483abc7c44" ], "author": { "name": "Margarita Granov", "email": "margra@marvell.com", "time": "Thu Oct 15 16:51:26 2015 +0200" }, "committer": { "name": "Greg Poist", "email": "poist@google.com", "time": "Thu Mar 24 11:59:54 2016 -0700" }, "message": "fix:ddr3libv2: Fix DDR3 Rank Control Register value calculation.\n\n\tSet mirroring bit is done for referenced CS\n\tCaelum topology is changed to be aligned with the fix:\n\nChange-Id: I6af113b8088b58a436cbfb124f7da1184e2adbf2\nSigned-off-by: Margarita Granov \u003cmargra@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/24031\nReviewed-by: Haim Boot \u003chayim@marvell.com\u003e\nTested-by: Haim Boot \u003chayim@marvell.com\u003e\nReviewed-on: http://vgitil04.il.marvell.com:8080/24176\nReviewed-by: Omri Itach \u003comrii@marvell.com\u003e\nTested-by: Omri Itach \u003comrii@marvell.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "befc70aac203b5d8b0854c65dd4d4c4a37090ab0", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c", "new_id": "e8cdf7083165deb2636b68bb814dfd157b3d5ed9", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c" }, { "type": "modify", "old_id": "35f614c7a6e7d3d675f014676a8c093e422e41bf", "old_mode": 33261, "old_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c", "new_id": "5dc1d49ec452d619c4cfd823dcc0d6d64a525f3e", "new_mode": 33261, "new_path": "tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c" } ] }