fix:ddr3libv2: Fix DDR3 Rank Control Register value calculation.
Set mirroring bit is done for referenced CS
Caelum topology is changed to be aligned with the fix:
Change-Id: I6af113b8088b58a436cbfb124f7da1184e2adbf2
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24031
Reviewed-by: Haim Boot <hayim@marvell.com>
Tested-by: Haim Boot <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24176
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index befc70a..e8cdf70 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -824,21 +824,21 @@
if (topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask == GT_TRUE)
{
/* checking mirrorEnableBitmask - if mirrorEnableBitmask is enabled - CS+4 bit in word shall be '1' */
- if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask & 0x1) != 0)
+ if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].csBitmask & 0x1) != 0)
{
- dataValue |= (1 << 4);
+ dataValue |= (topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask << 4);
}
- if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask & 0x2) != 0)
+ if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].csBitmask & 0x2) != 0)
{
- dataValue |= (1 << 5);
+ dataValue |= (topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask << 5);
}
- if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask & 0x4) != 0)
+ if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].csBitmask & 0x4) != 0)
{
- dataValue |= (1 << 6);
+ dataValue |= (topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask << 6);
}
- if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask & 0x8) != 0)
+ if ((topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].csBitmask & 0x8) != 0)
{
- dataValue |= (1 << 7);
+ dataValue |= (topologyMap->interfaceParams[interfaceId].asBusParams[busCnt].mirrorEnableBitmask << 7);
}
}
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
index 35f614c..5dc1d49 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -323,10 +323,10 @@
{
0xB, /* active interfaces */
/*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_width mem_size frequency casL casWL temperature */
- { {{{0x2,1,0,0}, {0x2,1,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
- {{{0x2,1,0,0}, {0x2,1,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ { {{{0x2,0,0,0}, {0x2,0,0,0}, {0x1,1,0,0}, {0x1,1,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x2,0,0,0}, {0x2,0,0,0}, {0x1,1,0,0}, {0x1,1,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
{{{0x1,1,0,0}, {0x1,1,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
- {{{0x2,1,0,0}, {0x2,1,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
+ {{{0x2,0,0,0}, {0x2,0,0,0}, {0x1,1,0,0}, {0x1,1,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} ,
{{{0x1,1,0,0}, {0x1,1,0,0}, {0x2,0,0,0}, {0x2,0,0,0}, {0,0,0,0}}, SPEED_BIN_DDR_1866M, BUS_WIDTH_16 , MEM_4G, DDR_FREQ_667, 0 , 0 , MV_HWS_TEMP_HIGH} },
0xF /* Buses mask */
}
