Documentation/devicetree/bindings/interrupt-controller/ti,c64x+megamod-pic.txt

C6X Interrupt Chips
-------------------

* C64X+ Core Interrupt Controller

  The core interrupt controller provides 16 prioritized interrupts to the
  C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
  Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
  sources coming from outside the core.

  Required properties:
  --------------------
  - compatible: Should be "ti,c64x+core-pic";
  - #interrupt-cells: <1>

  Interrupt Specifier Definition
  ------------------------------
  Single cell specifying the core interrupt priority level (4-15) where
  4 is highest priority and 15 is lowest priority.

  Example
  -------
  core_pic: interrupt-controller@0 {
	interrupt-controller;
	#interrupt-cells = <1>;
	compatible = "ti,c64x+core-pic";
  };



* C64x+ Megamodule Interrupt Controller

  The megamodule PIC consists of four interrupt mupliplexers each of which
  combine up to 32 interrupt inputs into a single interrupt output which
  may be cascaded into the core interrupt controller. The megamodule PIC
  has a total of 12 outputs cascading into the core interrupt controller.
  One for each core interrupt priority level. In addition to the combined
  interrupt sources, individual megamodule interrupts may be cascaded to
  the core interrupt controller. When an individual interrupt is cascaded,
  it is no longer handled through a megamodule interrupt combiner and is
  considered to have the core interrupt controller as the parent.

  Required properties:
  --------------------
  - compatible: "ti,c64x+megamod-pic"
  - interrupt-controller
  - #interrupt-cells: <1>
  - reg: base address and size of register area
  - interrupt-parent: must be core interrupt controller
  - interrupts: This should have four cells; one for each interrupt combiner.
                The cells contain the core priority interrupt to which the
                corresponding combiner output is wired.

  Optional properties:
  --------------------
  - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
                             priority interrupts. The first cell corresponds to
                             core priority 4 and the last cell corresponds to
                             core priority 15. The value of each cell is the
                             megamodule interrupt source which is MUXed to
                             the core interrupt corresponding to the cell
                             position. Allowed values are 4 - 127. Mapping for
                             interrupts 0 - 3 (combined interrupt sources) are
                             ignored.

  Interrupt Specifier Definition
  ------------------------------
  Single cell specifying the megamodule interrupt source (4-127). Note that
  interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
  use the core interrupt controller as their parent and the specifier will
  be the core priority level, not the megamodule interrupt number.

  Examples
  --------
  megamod_pic: interrupt-controller@1800000 {
	compatible = "ti,c64x+megamod-pic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1800000 0x1000>;
	interrupt-parent = <&core_pic>;
	interrupts = < 12 13 14 15 >;
  };

  This is a minimal example where all individual interrupts go through a
  combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
  to interrupt 13, etc.


  megamod_pic: interrupt-controller@1800000 {
	compatible = "ti,c64x+megamod-pic";
	interrupt-controller;
	#interrupt-cells = <1>;
	reg = <0x1800000 0x1000>;
	interrupt-parent = <&core_pic>;
	interrupts = < 12 13 14 15 >;
	ti,c64x+megamod-pic-mux = <  0  0  0  0
                                    32  0  0  0
                                     0  0  0  0 >;
  };

  This the same as the first example except that megamodule interrupt 32 is
  mapped directly to core priority interrupt 8. The node using this interrupt
  must set the core controller as its interrupt parent and use 8 in the
  interrupt specifier value.