| /* **************************************************************** |
| * Common defs for reg spec for chip ka_sc |
| * Auto-generated by trex2: DO NOT HAND-EDIT!! |
| * **************************************************************** |
| */ |
| |
| #ifndef HAL_KA_SC_AUTO_H |
| #define HAL_KA_SC_AUTO_H |
| |
| |
| /* ---------------------------------------------------------------- |
| * For block: 'scan' |
| */ |
| |
| /* ---- Block instance addressing (for block-select) */ |
| #define SCAN_BLOCK_ADDR_BIT_L 7 |
| #define SCAN_BLOCK_ADDR_BIT_H 9 |
| #define SCAN_BLOCK_ADDR_WIDTH 3 |
| |
| #define SCAN_ADDR 0x0 |
| |
| /* ---- Reg addressing (within block) */ |
| #define SCAN_REG_ADDR_BIT_L 2 |
| #define SCAN_REG_ADDR_BIT_H 6 |
| #define SCAN_REG_ADDR_WIDTH 5 |
| |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_REVISION */ |
| #define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 |
| #ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_RESET */ |
| #define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 |
| #ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_STATUS */ |
| #define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 |
| #ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_CNTL */ |
| #define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c |
| #ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_BRD_INFO */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 |
| #ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 |
| #ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 |
| #ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SCAN_TO_0 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c |
| #ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SCAN_TO_1 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 |
| #ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SCAN_CTRL */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 |
| #ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_PLL_CTRL */ |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 |
| #ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c |
| #ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 |
| #ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 |
| #ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 |
| #ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c |
| #ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_BRD_BRD_IN */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 |
| #ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_MISC */ |
| #define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 |
| #ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_INTERRUPT */ |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c |
| #ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 |
| #ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SCRATCH */ |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 |
| #ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 |
| |
| /* ================================================================ |
| * ---- Register KA_SC_SCAN_SCRATCH_MASK */ |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 |
| #ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 |
| #endif |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_REVISION */ |
| #define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff |
| #define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_RESET */ |
| #define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 |
| #define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 |
| #define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 |
| #define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 |
| #define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 |
| #define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 |
| #define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 |
| #define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 |
| #define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 |
| #define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 |
| #define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 |
| #define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 |
| #define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 |
| #define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 |
| #define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 |
| #define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 |
| #define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 |
| #define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 |
| #define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 |
| #define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 |
| #define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 |
| #define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 |
| #define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 |
| #define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 |
| #define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 |
| #define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 |
| #define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 |
| #define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 |
| #define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_STATUS */ |
| #define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_CNTL */ |
| #define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_BRD_INFO */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SCAN_TO_0 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SCAN_TO_1 */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SCAN_CTRL */ |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_PLL_CTRL */ |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_BRD_BRD_IN */ |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_MISC */ |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_INTERRUPT */ |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SCRATCH */ |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 |
| |
| /* ================================================================ |
| * Field info for register KA_SC_SCAN_SCRATCH_MASK */ |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) |
| #define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff |
| |
| #endif /* matches #ifndef HAL_KA_SC_AUTO_H */ |
