u-boot ethernet changes for prowl
by danielmentz@
configure the QCA8337N Ethernet switch to "Mode 5" as described in the
datasheet where RMGII 0 is connected to MAC0 of the Ethernet switch and
RGMII 1 is routed straight to PHY 4 (WAN port).
Change-Id: Ida68072f2d6443b6bd5b556c45c28a980592f320
diff --git a/board/ruby/ar8237.c b/board/ruby/ar8237.c
index 08e39aa..5ab1e41 100755
--- a/board/ruby/ar8237.c
+++ b/board/ruby/ar8237.c
@@ -120,14 +120,30 @@
#define AR8237_MASK_CTL_RESET (0x80000000)
#define AR8237_MASK_CLEAR_DEF (0)
#define AR8237_MODE_CTRL (0x04)
-#define AR8237_MODE_RGMII_PHY (0x07600000)
+
+#define S17_MAC0_RGMII_RXCLK_SHIFT 20
+#define S17_MAC0_RGMII_TXCLK_SHIFT 22
+#define S17_MAC0_RGMII_TXCLK_DELAY_EN (1 << 25)
+#define S17_MAC0_RGMII_EN (1 << 26)
+
+#define AR8237_MODE_RGMII_PHY (S17_MAC0_RGMII_EN)
+
+//#define AR8237_MODE_RGMII_PHY (0x07600000)
//#define AR8237_MODE_RGMII_PHY (0x07402000)
#define AR8237_PWS_CTRL (0x10)
#define AR8237_PWS_CTRL_DEF (0x40000000)
#define AR8237_FWCTL_CTRL (0x0624)
#define AR8237_FWCTL_CTRL_DEF (0x007f7f7f)
+
+#define S17_P0STATUS_REG 0x007c
+#define S17_P5STATUS_REG 0x0090
+#define S17_P6STATUS_REG 0x0094
+
#define AR8237_PORT6_CTRL (0xc)
-#define AR8237_PORT6_CTRL_DEF (0x01000000)
+#define S17_PHY4_RGMII_EN (1 << 17)
+#define S17_MAC6_RGMII_EN (1 << 26)
+#define AR8237_PORT6_CTRL_DEF (S17_PHY4_RGMII_EN)
+
#define AR8237_PORT0_CTRL (0x7c)
#define AR8237_PORT0_CTRL_DEF (0x7e)
@@ -143,6 +159,27 @@
#define AR8237_MIN_PHY_NUM (0)
#define AR8237_MAX_PHY_NUM (4)
+
+#define S17_P5PAD_MODE_REG 0x0008
+#define S17_MAC_RGMII_RXCLK_DELAY_EN (1 << 24)
+
+#define S17_SPEED_10M (0 << 0)
+#define S17_SPEED_100M (1 << 0)
+#define S17_SPEED_1000M (2 << 0)
+#define S17_TXMAC_EN (1 << 2)
+#define S17_RXMAC_EN (1 << 3)
+#define S17_TX_FLOW_EN (1 << 4)
+#define S17_RX_FLOW_EN (1 << 5)
+#define S17_DUPLEX_FULL (1 << 6)
+#define S17_DUPLEX_HALF (0 << 6)
+#define S17_TX_HALF_FLOW_EN (1 << 7)
+#define S17_LINK_EN (1 << 9)
+#define S17_FLOW_LINK_EN (1 << 12)
+#define S17_PORT_STATUS_DEFAULT (S17_SPEED_1000M | S17_TXMAC_EN | \
+ S17_RXMAC_EN | \
+ S17_DUPLEX_FULL )
+
+
////////////////////////////////////////////////////////////////////
// Types
////////////////////////////////////////////////////////////////////
@@ -190,6 +227,42 @@
return 0;
}
+int ar8237_normal_mdio_write(u16 phyAddr, u8 regAddr, u16 data)
+{
+ // check for clear MDIO status
+ if (ar8237_mdio_poll() != 0) {
+ return -1;
+ }
+
+ ar8237_emac_wrreg(EMAC_MAC_MDIO_DATA, data & 0xffff);
+ ar8237_emac_wrreg(EMAC_MAC_MDIO_CTRL,
+ ((mdc_clk_divisor & MacMdioCtrlClkMask) << MacMdioCtrlClkShift) |
+ (regAddr << 5) | (phyAddr & 0x1f) |
+ AR8237_MDIO_START);
+ if (ar8237_mdio_poll() != 0) {
+ return -1;
+ }
+ // return without waiting for final completion
+ return 0;
+}
+int ar8237_normal_mdio_read(u16 phyAddr, u8 regAddr, u16 *data)
+{
+ if (ar8237_mdio_poll() != 0) {
+ return -1;
+ }
+
+ ar8237_emac_wrreg(EMAC_MAC_MDIO_CTRL, ( (regAddr & 0x1f) << 5) | AR8237_MDIO_START |
+ ((mdc_clk_divisor & MacMdioCtrlClkMask) << MacMdioCtrlClkShift) |
+ AR8237_MDIO_READ | (phyAddr & 0x1f));
+ if (ar8237_mdio_poll() != 0) {
+ return -1;
+ }
+
+ *data = ar8237_emac_rdreg(EMAC_MAC_MDIO_DATA);
+ return 0;
+}
+int __ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data);
+
/*********************************************************************
Name: ar8237_mdio_write
Purpose: mdio write routine for AR8237 device
@@ -204,6 +277,9 @@
u32 rg = (regAddr & 0x3c) >> 1;
u32 ph = (regAddr & 0x1c0) >> 6;
+ u32 prev;
+ __ar8237_mdio_read(phyAddr, regAddr, &prev);
+
// check for clear MDIO status
if (ar8237_mdio_poll() != 0) {
return -1;
@@ -237,6 +313,8 @@
return -1;
}
+ // printf("%s reg 0x%04x data 0x%08x previously %08x\n", __func__, regAddr, data, prev);
+
// return without waiting for final completion
return 0;
}
@@ -248,7 +326,7 @@
more than one cycle to complete the write.
checks for completion first
*********************************************************************/
-int ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data)
+int __ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data)
{
u32 highAddr = regAddr >> 9;
// need to swizzle the bits into arasan's fields which are different
@@ -288,6 +366,16 @@
*data = *data | (ar8237_emac_rdreg(EMAC_MAC_MDIO_DATA) << 16);
return 0;
}
+int ar8237_mdio_read(u32 phyAddr, u32 regAddr, u32 * data) {
+ int rc;
+ rc = __ar8237_mdio_read(phyAddr, regAddr, data);
+ if (!rc) {
+ // printf("%s reg 0x%04x data 0x%08x\n", __func__, regAddr, *data);
+ } else {
+ printf("%s failed reg 0x%04x data 0x%08x\n", __func__, regAddr, *data);
+ }
+ return rc;
+}
/*********************************************************************
Name: ar8237_init
@@ -299,6 +387,7 @@
{
u32 addr;
u32 devID;
+ u16 val;
g8237Dev.base = baseAddr;
// need to scan?
@@ -315,29 +404,37 @@
while (addr < AR8237_MAX_PHY_NUM) {
uint32_t reset = AR8237_MASK_CTL_RESET;
ar8237_mdio_read(addr, AR8237_MASK_CTL, &devID);
- if ((devID & 0xff00) == 0x1200) {
- printf("Detected AR8237 Switch %d - set for RGMII, 1000FD\n",addr);
+ if ((devID & 0xff00) == 0x1300) {
+ printf("Detected AR8337 Switch %d - set for RGMII, 1000FD devID 0x%x\n",addr, devID);
// do a softreset
- ar8237_mdio_write(phy_addr, AR8237_MODE_CTRL, AR8237_MODE_RGMII_PHY);
-
// do a clean reset and wait for completion
ar8237_mdio_write(phy_addr, AR8237_MASK_CTL, AR8237_MASK_CTL_RESET);
while (reset & AR8237_MASK_CTL_RESET) {
ar8237_mdio_read(addr, AR8237_MASK_CTL, &reset);
}
+ ar8237_mdio_write(phy_addr, AR8237_MODE_CTRL, AR8237_MODE_RGMII_PHY);
+
ar8237_mdio_write(phy_addr, AR8237_MASK_CTL, AR8237_MASK_CLEAR_DEF);
-
- ar8237_mdio_write(phy_addr, AR8237_PWS_CTRL, AR8237_PWS_CTRL_DEF);
ar8237_mdio_write(phy_addr, AR8237_FWCTL_CTRL, AR8237_FWCTL_CTRL_DEF);
ar8237_mdio_write(phy_addr, AR8237_PORT6_CTRL, AR8237_PORT6_CTRL_DEF);
- ar8237_mdio_write(phy_addr, AR8237_PORT0_CTRL, AR8237_PORT0_CTRL_DEF);
- g8237Dev.phy = addr;
+
+ /* Disable MAC5 and MAC6 (due to PHY4), QCA */
+ ar8237_mdio_write(phy_addr, S17_P5STATUS_REG, 0);
+ ar8237_mdio_write(phy_addr, S17_P6STATUS_REG, 0);
- //set the register 0xe00000b4 for RGMII Dll control register
- *(volatile u32 *)(0xe00000b4) = 0x86868f8f;
+ ar8237_mdio_write(phy_addr, S17_P0STATUS_REG, S17_PORT_STATUS_DEFAULT);
+
+ ar8237_normal_mdio_write(4, 29, 0x12);
+ ar8237_normal_mdio_read(4, 30, &val);
+ val |= (1<<3);
+ ar8237_normal_mdio_write(4, 30, val);
+ ar8237_normal_mdio_write(4, 29, 0);
+
+
+ g8237Dev.phy = addr;
return addr;
}
diff --git a/board/ruby/arasan-emac-ahb.c b/board/ruby/arasan-emac-ahb.c
index d70bf7e..2f62807 100644
--- a/board/ruby/arasan-emac-ahb.c
+++ b/board/ruby/arasan-emac-ahb.c
@@ -887,6 +887,11 @@
const char *dbg_bus = getenv("debug_bus");
int i;
+ printf("Resetting QCA8337\n");
+ gpio_config(7, GPIO_MODE_OUTPUT);
+ gpio_output(7, 1);
+ udelay(10);
+
if (!((emac0_cfg & EMAC_IN_USE) || (emac1_cfg & EMAC_IN_USE))) {
printf("error: no emac enabled\n");
return -1;
@@ -949,7 +954,7 @@
if (strcmp(argv[1],"read") == 0) {
uint32_t a1,a2,val;
a1 = simple_strtoul (argv[2], NULL, 10);
- a2 = simple_strtoul (argv[3], NULL, 16);
+ a2 = simple_strtoul (argv[3], NULL, 10);
mdio_postrd_raw(base, a1, a2);
val = mdio_rdval_raw(base, 1);
printf("phy:%d reg:%d=0x%x\n",a1,a2,val);
diff --git a/include/configs/ruby.h b/include/configs/ruby.h
index 882682c..4d0c629 100644
--- a/include/configs/ruby.h
+++ b/include/configs/ruby.h
@@ -168,7 +168,7 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_ARASAN_GBE 1
#define CONFIG_IPADDR 192.168.1.100
- #define CONFIG_SERVERIP 192.168.1.150
+ #define CONFIG_SERVERIP 192.168.1.2
#define CONFIG_ETHADDR 30:46:9a:25:be:e4
#define CONFIG_BOOTFILE "topaz-linux.lzma.img"
#ifndef PLATFORM_NOSPI
