| /* |
| * (C) Copyright 2014 Quantenna Communications, Inc. |
| * |
| * Program to print memory map defines. |
| */ |
| |
| #include <stdio.h> |
| #include <string.h> |
| #include <stdint.h> |
| #include "ruby_mem.h" |
| |
| struct ruby_mem_symbol { |
| char *name; |
| uint32_t addr; |
| }; |
| |
| struct ruby_mem_symbol ruby_mem_symbols[] = { |
| { "RUBY_SRAM_UNIFIED_BEGIN", RUBY_SRAM_UNIFIED_BEGIN }, |
| { "RUBY_SRAM_UNIFIED_NOCACHE_BEGIN", RUBY_SRAM_UNIFIED_NOCACHE_BEGIN }, |
| { "RUBY_SRAM_FLIP_BEGIN", RUBY_SRAM_FLIP_BEGIN }, |
| { "RUBY_SRAM_FLIP_NOCACHE_BEGIN", RUBY_SRAM_FLIP_NOCACHE_BEGIN }, |
| { "RUBY_SRAM_NOFLIP_BEGIN", RUBY_SRAM_NOFLIP_BEGIN }, |
| { "RUBY_SRAM_NOFLIP_NOCACHE_BEGIN", RUBY_SRAM_NOFLIP_NOCACHE_BEGIN }, |
| { "RUBY_SRAM_BANK_SIZE", RUBY_SRAM_BANK_SIZE }, |
| { "RUBY_SRAM_SIZE", RUBY_SRAM_SIZE }, |
| { "RUBY_SRAM_BANK_SAFE_SIZE", RUBY_SRAM_BANK_SAFE_SIZE }, |
| { "RUBY_DRAM_UNIFIED_BEGIN", RUBY_DRAM_UNIFIED_BEGIN }, |
| { "RUBY_DRAM_UNIFIED_NOCACHE_BEGIN", RUBY_DRAM_UNIFIED_NOCACHE_BEGIN }, |
| { "RUBY_DRAM_FLIP_BEGIN", RUBY_DRAM_FLIP_BEGIN }, |
| { "RUBY_DRAM_FLIP_NOCACHE_BEGIN", RUBY_DRAM_FLIP_NOCACHE_BEGIN }, |
| { "RUBY_DRAM_NOFLIP_BEGIN", RUBY_DRAM_NOFLIP_BEGIN }, |
| { "RUBY_DRAM_NOFLIP_NOCACHE_BEGIN", RUBY_DRAM_NOFLIP_NOCACHE_BEGIN }, |
| { "RUBY_MAX_DRAM_SIZE", RUBY_MAX_DRAM_SIZE }, |
| { "RUBY_MIN_DRAM_SIZE", RUBY_MIN_DRAM_SIZE }, |
| { "RUBY_SRAM_BEGIN", RUBY_SRAM_BEGIN }, |
| { "RUBY_SRAM_BUS_BEGIN", RUBY_SRAM_BUS_BEGIN }, |
| { "RUBY_SRAM_NOCACHE_BEGIN", RUBY_SRAM_NOCACHE_BEGIN }, |
| { "RUBY_DRAM_BEGIN", RUBY_DRAM_BEGIN }, |
| { "RUBY_DRAM_BUS_BEGIN", RUBY_DRAM_BUS_BEGIN }, |
| { "RUBY_DRAM_NOCACHE_BEGIN", RUBY_DRAM_NOCACHE_BEGIN }, |
| { "RUBY_SPI_FLASH_ADDR", RUBY_SPI_FLASH_ADDR }, |
| { "RUBY_HARDWARE_BEGIN", RUBY_HARDWARE_BEGIN }, |
| { "CONFIG_ARC_CONF_SIZE", CONFIG_ARC_CONF_SIZE }, |
| { "CONFIG_ARC_CONF_BASE", CONFIG_ARC_CONF_BASE }, |
| { "CONFIG_ARC_KERNEL_PAGE_SIZE", CONFIG_ARC_KERNEL_PAGE_SIZE }, |
| { "RUBY_KERNEL_LOAD_DRAM_BEGIN", RUBY_KERNEL_LOAD_DRAM_BEGIN }, |
| { "CONFIG_ARC_NULL_BASE", CONFIG_ARC_NULL_BASE }, |
| { "CONFIG_ARC_NULL_SIZE", CONFIG_ARC_NULL_SIZE }, |
| { "CONFIG_ARC_NULL_END", CONFIG_ARC_NULL_END }, |
| { "CONFIG_ARC_PCIE_BASE", CONFIG_ARC_PCIE_BASE }, |
| { "CONFIG_ARC_PCIE_SIZE", CONFIG_ARC_PCIE_SIZE }, |
| { "CONFIG_ARC_MUC_STACK_SIZE", CONFIG_ARC_MUC_STACK_SIZE }, |
| { "RUBY_CRUMBS_MAGIC", RUBY_CRUMBS_MAGIC }, |
| { "NO_RUBY_WEAK", NO_RUBY_WEAK }, |
| { "RUBY_BAD_BUS_ADDR", RUBY_BAD_BUS_ADDR }, |
| { "RUBY_ERROR_ADDR", RUBY_ERROR_ADDR }, |
| { "RUBY_DSP_XYMEM_BEGIN", RUBY_DSP_XYMEM_BEGIN }, |
| { "RUBY_DSP_XYMEM_END", RUBY_DSP_XYMEM_END }, |
| { "RUBY_CRUMBS_SIZE", RUBY_CRUMBS_SIZE }, |
| { "CONFIG_ARC_KERNEL_SRAM_B1_BASE", CONFIG_ARC_KERNEL_SRAM_B1_BASE }, |
| { "CONFIG_ARC_KERNEL_SRAM_B1_SIZE", CONFIG_ARC_KERNEL_SRAM_B1_SIZE }, |
| { "CONFIG_ARC_KERNEL_SRAM_B1_END", CONFIG_ARC_KERNEL_SRAM_B1_END }, |
| { "CONFIG_ARC_KERNEL_SRAM_B2_BASE", CONFIG_ARC_KERNEL_SRAM_B2_BASE }, |
| { "CONFIG_ARC_KERNEL_SRAM_B2_END", CONFIG_ARC_KERNEL_SRAM_B2_END }, |
| { "CONFIG_ARC_KERNEL_SRAM_B2_SIZE", CONFIG_ARC_KERNEL_SRAM_B2_SIZE }, |
| { "CONFIG_ARC_MUC_SRAM_B1_BASE", CONFIG_ARC_MUC_SRAM_B1_BASE }, |
| { "CONFIG_ARC_MUC_SRAM_B1_END", CONFIG_ARC_MUC_SRAM_B1_END }, |
| { "CONFIG_ARC_MUC_SRAM_B1_SIZE", CONFIG_ARC_MUC_SRAM_B1_SIZE }, |
| { "CONFIG_ARC_MUC_SRAM_B2_BASE", CONFIG_ARC_MUC_SRAM_B2_BASE }, |
| { "CONFIG_ARC_MUC_SRAM_B2_SIZE", CONFIG_ARC_MUC_SRAM_B2_SIZE }, |
| { "CONFIG_ARC_MUC_SRAM_B2_END", CONFIG_ARC_MUC_SRAM_B2_END }, |
| { "CONFIG_ARC_MUC_STACK_OFFSET", CONFIG_ARC_MUC_STACK_OFFSET }, |
| { "CONFIG_ARC_MUC_STACK_INIT", CONFIG_ARC_MUC_STACK_INIT }, |
| { "RUBY_CRUMBS_OFFSET", RUBY_CRUMBS_OFFSET }, |
| { "RUBY_CRUMBS_ADDR", RUBY_CRUMBS_ADDR }, |
| { "CONFIG_ARC_PCIE_RSVD_SIZE", CONFIG_ARC_PCIE_RSVD_SIZE }, |
| { "CONFIG_ARC_DSP_BASE", CONFIG_ARC_DSP_BASE }, |
| { "CONFIG_ARC_DSP_SIZE", CONFIG_ARC_DSP_SIZE }, |
| { "CONFIG_ARC_DSP_END", CONFIG_ARC_DSP_END }, |
| { "CONFIG_ARC_MUC_BASE", CONFIG_ARC_MUC_BASE }, |
| { "CONFIG_ARC_MUC_SIZE", CONFIG_ARC_MUC_SIZE }, |
| { "CONFIG_ARC_MUC_END", CONFIG_ARC_MUC_END }, |
| { "CONFIG_ARC_MUC_MAPPED_BASE", CONFIG_ARC_MUC_MAPPED_BASE }, |
| { "CONFIG_ARC_MUC_MAPPED_SIZE", CONFIG_ARC_MUC_MAPPED_SIZE }, |
| { "CONFIG_ARC_KERNEL_MEM_BASE", CONFIG_ARC_KERNEL_MEM_BASE }, |
| { "CONFIG_ARC_UBOOT_RESERVED_SPACE", CONFIG_ARC_UBOOT_RESERVED_SPACE }, |
| { "CONFIG_ARC_KERNEL_BOOT_BASE", CONFIG_ARC_KERNEL_BOOT_BASE }, |
| { "CONFIG_ARC_KERNEL_BASE", CONFIG_ARC_KERNEL_BASE }, |
| { "CONFIG_ARC_KERNEL_MAX_SIZE", CONFIG_ARC_KERNEL_MAX_SIZE }, |
| { "CONFIG_ARC_KERNEL_MIN_SIZE", CONFIG_ARC_KERNEL_MIN_SIZE }, |
| { "TOPAZ_AUC_IMEM_ADDR", TOPAZ_AUC_IMEM_ADDR }, |
| { "TOPAZ_AUC_IMEM_SIZE", TOPAZ_AUC_IMEM_SIZE }, |
| { "TOPAZ_AUC_DMEM_ADDR", TOPAZ_AUC_DMEM_ADDR }, |
| { "TOPAZ_AUC_DMEM_SIZE", TOPAZ_AUC_DMEM_SIZE }, |
| { "RUBY_SYS_CTL_SAFE_READ_REGISTER", RUBY_SYS_CTL_SAFE_READ_REGISTER }, |
| { "TOPAZ_CACHE_WAR_OFFSET", TOPAZ_CACHE_WAR_OFFSET }, |
| { "TOPAZ_HBM_BUF_EMAC_RX_COUNT", TOPAZ_HBM_BUF_EMAC_RX_COUNT }, |
| { "TOPAZ_HBM_BUF_WMAC_RX_COUNT", TOPAZ_HBM_BUF_WMAC_RX_COUNT }, |
| { "TOPAZ_HBM_EMAC_TX_DONE_COUNT", TOPAZ_HBM_EMAC_TX_DONE_COUNT }, |
| { "TOPAZ_HBM_POOL_PTR_SIZE", TOPAZ_HBM_POOL_PTR_SIZE }, |
| { "TOPAZ_HBM_POOL_EMAC_RX_START", TOPAZ_HBM_POOL_EMAC_RX_START }, |
| { "TOPAZ_HBM_POOL_EMAC_RX_SIZE", TOPAZ_HBM_POOL_EMAC_RX_SIZE }, |
| { "TOPAZ_HBM_POOL_EMAC_RX_END", TOPAZ_HBM_POOL_EMAC_RX_END }, |
| { "TOPAZ_HBM_POOL_WMAC_RX_START", TOPAZ_HBM_POOL_WMAC_RX_START }, |
| { "TOPAZ_HBM_POOL_WMAC_RX_SIZE", TOPAZ_HBM_POOL_WMAC_RX_SIZE }, |
| { "TOPAZ_HBM_POOL_WMAC_RX_END", TOPAZ_HBM_POOL_WMAC_RX_END }, |
| { "TOPAZ_HBM_POOL_EMAC_TX_DONE_START", TOPAZ_HBM_POOL_EMAC_TX_DONE_START }, |
| { "TOPAZ_HBM_POOL_EMAC_TX_DONE_SIZE", TOPAZ_HBM_POOL_EMAC_TX_DONE_SIZE }, |
| { "TOPAZ_HBM_POOL_EMAC_TX_DONE_END", TOPAZ_HBM_POOL_EMAC_TX_DONE_END }, |
| { "TOPAZ_HBM_BUF_ALIGN", TOPAZ_HBM_BUF_ALIGN }, |
| { "TOPAZ_HBM_BUF_EMAC_RX_POOL", TOPAZ_HBM_BUF_EMAC_RX_POOL }, |
| { "TOPAZ_HBM_BUF_WMAC_RX_POOL", TOPAZ_HBM_BUF_WMAC_RX_POOL }, |
| { "TOPAZ_HBM_AUC_FEEDBACK_POOL", TOPAZ_HBM_AUC_FEEDBACK_POOL }, |
| { "TOPAZ_HBM_EMAC_TX_DONE_POOL", TOPAZ_HBM_EMAC_TX_DONE_POOL }, |
| { "TOPAZ_HBM_BUF_EMAC_RX_SIZE", TOPAZ_HBM_BUF_EMAC_RX_SIZE }, |
| { "TOPAZ_HBM_BUF_WMAC_RX_SIZE", TOPAZ_HBM_BUF_WMAC_RX_SIZE }, |
| { "TOPAZ_HBM_BUF_EMAC_RX_TOTAL", TOPAZ_HBM_BUF_EMAC_RX_TOTAL }, |
| { "TOPAZ_HBM_BUF_WMAC_RX_TOTAL", TOPAZ_HBM_BUF_WMAC_RX_TOTAL }, |
| { "TOPAZ_HBM_BUF_EMAC_RX_BASE", TOPAZ_HBM_BUF_EMAC_RX_BASE }, |
| { "TOPAZ_HBM_BUF_EMAC_RX_END", TOPAZ_HBM_BUF_EMAC_RX_END }, |
| { "TOPAZ_HBM_BUF_WMAC_RX_BASE", TOPAZ_HBM_BUF_WMAC_RX_BASE }, |
| { "TOPAZ_HBM_BUF_WMAC_RX_END", TOPAZ_HBM_BUF_WMAC_RX_END }, |
| { "TOPAZ_FWT_SW_START", TOPAZ_FWT_SW_START }, |
| { "TOPAZ_FWT_SW_SIZE", TOPAZ_FWT_SW_SIZE }, |
| { "TOPAZ_FWT_SW_END", TOPAZ_FWT_SW_END }, |
| { "TOPAZ_FWT_MCAST_ENTRIES", TOPAZ_FWT_MCAST_ENTRIES }, |
| { "TOPAZ_FWT_MCAST_FF_ENTRIES", TOPAZ_FWT_MCAST_FF_ENTRIES }, |
| { "TOPAZ_FWT_MCAST_IPMAP_ENT_SIZE", TOPAZ_FWT_MCAST_IPMAP_ENT_SIZE }, |
| { "TOPAZ_FWT_MCAST_TQE_ENT_SIZE", TOPAZ_FWT_MCAST_TQE_ENT_SIZE }, |
| { "TOPAZ_FWT_MCAST_IPMAP_SIZE", TOPAZ_FWT_MCAST_IPMAP_SIZE }, |
| { "TOPAZ_FWT_MCAST_TQE_SIZE", TOPAZ_FWT_MCAST_TQE_SIZE }, |
| { "TOPAZ_FWT_MCAST_TQE_FF_SIZE", TOPAZ_FWT_MCAST_TQE_FF_SIZE }, |
| { "TOPAZ_FWT_MCAST_IPMAP_BASE", TOPAZ_FWT_MCAST_IPMAP_BASE }, |
| { "TOPAZ_FWT_MCAST_IPMAP_END", TOPAZ_FWT_MCAST_IPMAP_END }, |
| { "TOPAZ_FWT_MCAST_TQE_BASE", TOPAZ_FWT_MCAST_TQE_BASE }, |
| { "TOPAZ_FWT_MCAST_TQE_END", TOPAZ_FWT_MCAST_TQE_END }, |
| { "TOPAZ_FWT_MCAST_TQE_FF_BASE", TOPAZ_FWT_MCAST_TQE_FF_BASE }, |
| { "TOPAZ_FWT_MCAST_TQE_FF_END", TOPAZ_FWT_MCAST_TQE_FF_END }, |
| { "TOPAZ_FWT_MCAST_END", TOPAZ_FWT_MCAST_END }, |
| { "CONFIG_ARC_KERNEL_SRAM_B1_BASE", CONFIG_ARC_KERNEL_SRAM_B1_BASE }, |
| { "CONFIG_ARC_KERNEL_SRAM_B1_END", CONFIG_ARC_KERNEL_SRAM_B1_END }, |
| { "CONFIG_ARC_KERNEL_SRAM_B2_BASE", CONFIG_ARC_KERNEL_SRAM_B2_BASE }, |
| { "CONFIG_ARC_KERNEL_SRAM_B2_END", CONFIG_ARC_KERNEL_SRAM_B2_END }, |
| { "CONFIG_ARC_MUC_SRAM_B1_BASE", CONFIG_ARC_MUC_SRAM_B1_BASE }, |
| { "CONFIG_ARC_MUC_SRAM_B1_END", CONFIG_ARC_MUC_SRAM_B1_END }, |
| { "CONFIG_ARC_AUC_SRAM_BASE", CONFIG_ARC_AUC_SRAM_BASE }, |
| { "CONFIG_ARC_AUC_SRAM_SIZE", CONFIG_ARC_AUC_SRAM_SIZE }, |
| { "CONFIG_ARC_AUC_SRAM_END", CONFIG_ARC_AUC_SRAM_END }, |
| { "CONFIG_ARC_AUC_BASE", CONFIG_ARC_AUC_BASE }, |
| { "CONFIG_ARC_AUC_SIZE", CONFIG_ARC_AUC_SIZE }, |
| { "CONFIG_ARC_AUC_END", CONFIG_ARC_AUC_END }, |
| { "CONFIG_ARC_SRAM_END", CONFIG_ARC_SRAM_END }, |
| }; |
| |
| #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) |
| |
| int main(int argc, char const *argv[]) |
| { |
| int i; |
| |
| for (i = 0; i < ARRAY_SIZE(ruby_mem_symbols); ++i) |
| printf("%-40s 0x%08X\n", ruby_mem_symbols[i].name, ruby_mem_symbols[i].addr); |
| |
| return 0; |
| } |