Merge remote-tracking branch 'gfiber-internal/vendor_drops' into local_master
Change-Id: I9c1357caab2a3f1cdc8f5c608275b73806098203
diff --git a/Makefile b/Makefile
index ea1709b..ba40312 100644
--- a/Makefile
+++ b/Makefile
@@ -2646,7 +2646,6 @@
$(CPP) $(AFLAGS) $< -o $@ -MP -MD -MF $@.d
RUBY_MINI_OBJS += board/ruby/start.o
-RUBY_MINI_OBJS += board/ruby/flip.o
RUBY_MINI_OBJS += board/ruby/gpio.o
RUBY_MINI_OBJS += board/ruby/timer.o
RUBY_MINI_OBJS += board/ruby/serial.o
@@ -2672,6 +2671,9 @@
ifeq ($(board_config),topaz_vzn_config)
CFLAGS += -DTOPAZ_VZN_MINI_UBOOT
endif
+ifeq ($(board_config),topaz_qfdr_config)
+RUBY_MINI_CFLAGS += -DTOPAZ_QFDR_VLAN=2
+endif
ifeq ($(TOPAZ_EP_MINI_UBOOT),1)
CFLAGS += -DTOPAZ_EP_MINI_UBOOT
diff --git a/board/ruby/Makefile b/board/ruby/Makefile
index d824f02..f5a4413 100644
--- a/board/ruby/Makefile
+++ b/board/ruby/Makefile
@@ -4,8 +4,6 @@
CFLAGS += -Wall -Werror
-RTL8367B_SRC=./rtl8367b
-
LIB = lib$(BOARD).a
OBJS := \
@@ -30,10 +28,7 @@
uc.o \
cmd_memtest.o \
tftp_bootp_loop.o \
- pcie2.o \
- $(RTL8367B_SRC)/rtl8367b_init.o \
- $(RTL8367B_SRC)/rtl8367b_api.o \
- $(RTL8367B_SRC)/rtl8367b_smi.o
+ pcie2.o
ifneq ($(filter topaz_amber_medium_config, $(board_config)),)
OBJS += amber_uboot.o
@@ -41,7 +36,6 @@
SOBJS := \
vectors.o \
- flip.o \
start.o \
newlib_memcpy-700.o \
newlib_memcmp.o \
diff --git a/board/ruby/arasan-emac-ahb.c b/board/ruby/arasan-emac-ahb.c
index 241385c..940d087 100644
--- a/board/ruby/arasan-emac-ahb.c
+++ b/board/ruby/arasan-emac-ahb.c
@@ -34,7 +34,6 @@
#include <asm/arch/platform.h>
#include "ar8236.h"
#include "ar8237.h"
-#include "rtl8367b/rtl8367b_init.h"
#include "ruby_board_cfg.h"
#include "board_cfg.h"
#include <asm/arch/arasan_emac_ahb.h>
@@ -908,10 +907,6 @@
arasan_initialize_gpio_reset(emac_cfg);
arasan_initialize_release_reset(emac0_cfg, emac1_cfg, rgmii_timing, 1);
- if (emac_cfg & (EMAC_PHY_RTL8363SB_P0 | EMAC_PHY_RTL8363SB_P1 | EMAC_PHY_RTL8365MB)) {
- rtl8367b_init(emac_priv, emac_cfg);
- }
-
br_priv->nemacs = 0;
br_priv->phy_addr_mask = 0;
@@ -1057,7 +1052,6 @@
static int emac_phy_init(struct emac_private *priv)
{
const uintptr_t base = priv->io_base;
- const uintptr_t mdio_base = priv->mdio->base;
const int emac = priv->emac;
int i;
uint32_t val, x;
@@ -1066,7 +1060,9 @@
uint32_t lpa2 = 0;
uint32_t media = 0;
uint32_t duplex = 0;
-
+#if (TOPAZ_FPGA_PLATFORM)
+ const uintptr_t mdio_base = priv->mdio->base;
+#endif
if (!(priv->phy_flags & EMAC_PHY_NOT_IN_USE)) {
if (priv->phy_flags & EMAC_PHY_RESET) {
udelay(4);
@@ -1189,7 +1185,7 @@
}
/* Force link speed & duplex */
-#if defined(TOPAZ_FPGA_PLATFORM)
+#if (TOPAZ_FPGA_PLATFORM)
/*
* Must reset PHYs in the order listed below - PHY ADDR=(4, 1, 2, 3)
* Only FPGA-B will bring-up the PHYs and configure them since FPGA-A
@@ -1201,6 +1197,24 @@
mdio_postwr_raw(mdio_base, TOPAZ_FPGAA_PHY1_ADDR, PhyBMCR, i);
#else
priv->mdio->write(priv, PhyBMCR, i);
+ i = 0;
+ do {
+ /* Wait for phy linkup */
+ udelay(500);
+ if ((val = priv->mdio->read(priv, PhyBMSR)) == MDIO_READ_FAIL) {
+ return 0;
+ }
+ i++;
+
+ if (!(val & PhyLinkIsUp) && (i >= 3000)) {
+ printf("LinkDown\n");
+ return 0;
+ }
+ if (ctrlc()) {
+ printf("Ctrl+C detected\n");
+ return 0;
+ }
+ } while (!(val & PhyLinkIsUp));
#endif
printf("GMII: Forced link speed is ");
@@ -1256,12 +1270,6 @@
printf("-HD\n");
}
- /* for certain switches, poll waiting for a link up before returning */
- if (priv->phy_flags & EMAC_PHY_NOT_IN_USE) {
- if (priv->phy_flags & (EMAC_PHY_RTL8363SB_P0 | EMAC_PHY_RTL8363SB_P1)) {
- rtl8367b_poll_linkup(priv);
- }
- }
emac_wrreg(base, EMAC_MAC_GLOBAL_CTRL, x);
diff --git a/board/ruby/rtl8367b/rtl8367b_api.c b/board/ruby/rtl8367b/rtl8367b_api.c
deleted file mode 100644
index 059883e..0000000
--- a/board/ruby/rtl8367b/rtl8367b_api.c
+++ /dev/null
@@ -1,1249 +0,0 @@
-/*
- * Copyright (C) 2010 Realtek Semiconductor Corp.
- * All Rights Reserved.
- *
- * This program is the proprietary software of Realtek Semiconductor
- * Corporation and/or its licensors, and only be used, duplicated,
- * modified or distributed under the authorized license from Realtek.
- *
- * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
- * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
- *
- * $Revision: 33266 $
- * $Date: 2012-10-08 14:33:47 +0800 (星期一, 08 十月 2012) $
- *
- * Purpose : RTK switch high-level API for RTL8367/RTL8367B
- * Feature : Here is a list of all functions and variables in this module.
- *
- */
-
-#include "rtl8367b_init.h"
-#include "rtl8367b_smi.h"
-
-#define DELAY_800MS_FOR_CHIP_STATABLE() { }
-
-uint16_t (*init_para)[2];
-uint16_t init_size;
-
-#if defined(CHIP_RTL8363SB)
-uint16_t ChipData00[][2]= {
-/*Code of Func*/
-{0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
-{0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
-{0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
-{0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
-{0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
-{0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
-{0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
-{0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
-{0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
-{0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
-{0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
-{0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
-{0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
-{0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
-{0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
-{0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
-{0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
-{0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
-{0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
-{0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
-{0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
-{0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
-{0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
-{0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
-{0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
-{0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
-{0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
-{0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
-{0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
-{0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
-{0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
-{0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
-{0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
-{0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
-{0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
-{0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
-{0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
-{0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
-{0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
-{0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
-{0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
-{0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
-{0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
-{0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
-{0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
-{0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
-{0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
-{0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
-{0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
-{0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
-{0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
-{0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
-{0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
-{0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
-{0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
-{0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
-{0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
-{0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
-{0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
-{0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
-{0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
-{0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
-{0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
-{0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
-{0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
-{0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
-{0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
-{0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
-{0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
-{0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
-{0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
-{0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
-{0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
-{0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
-{0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
-{0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
-{0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
-{0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
-{0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
-{0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
-{0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
-{0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
-{0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
-{0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
-{0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
-{0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
-{0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
-{0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
-{0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
-{0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
-{0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
-{0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
-{0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
-{0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
-{0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
-{0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
-{0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
-{0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
-{0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
-{0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
-{0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
-{0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
-{0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
-{0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
-{0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
-{0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
-{0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
-{0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
-{0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
-{0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
-{0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
-{0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
-{0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
-{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
-{0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
-{0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
-{0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
-{0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
-{0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
-{0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
-{0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
-{0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
-{0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
-{0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
-{0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
-{0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
-{0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
-{0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
-{0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
-{0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
-{0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
-{0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
-{0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
-{0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
-{0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
-{0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
-{0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
-{0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
-{0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
-{0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
-{0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
-{0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
-{0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
-{0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
-{0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
-{0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
-{0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
-{0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
-{0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
-{0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
-{0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
-{0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
-{0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
-{0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
-{0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
-{0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
-{0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
-{0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
-{0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
-{0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
-{0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
-{0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
-{0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
-{0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
-{0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
-{0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
-{0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
-{0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
-{0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
-{0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
-{0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
-{0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
-{0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
-{0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
-{0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
-{0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
-{0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
-{0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
-{0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
-{0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
-{0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
-{0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
-{0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
-{0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
-{0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
-{0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
-{0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
-{0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
-{0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
-{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
-{0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
-{0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
-{0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
-{0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
-{0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
-{0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
-{0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
-{0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
-{0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
-{0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
-{0x13EB, 0x11BB}, {0x2017, 0xA11F}, {0x2077, 0xA11F}, {0x2097, 0xA11F}
- };
-/*End of ChipData00[][2]*/
-
-uint16_t ChipData01[][2]= {
-/*Code of Func*/
-{0x1303, 0x0778}, {0x1304, 0x7777}, {0x13E2, 0x01FE}, {0x1310, 0x1075},
-{0x1305, 0x0003}, {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000},
-{0x121E, 0x03CA}, {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096},
-{0x1238, 0x0078}, {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002},
-{0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000},
-{0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000},
-{0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000},
-{0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000},
-{0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86},
-{0x2206, 0x800E}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200},
-{0x6107, 0xE58B}, {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
-{0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030},
-{0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000},
-{0x220F, 0x0100}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000},
-{0x2206, 0x0280}, {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7},
-{0x2206, 0xA080}, {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153},
-{0x2206, 0x0201}, {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201},
-{0x2206, 0x7CE0}, {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E},
-{0x2206, 0x01E1}, {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000},
-{0x2206, 0xE4AE}, {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
-{0x2206, 0x85C1}, {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE},
-{0x2206, 0x8AFD}, {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE},
-{0x2206, 0xFFF7}, {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E},
-{0x2206, 0xAD20}, {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04},
-{0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548},
-{0x2206, 0xE08A}, {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00},
-{0x2206, 0x009E}, {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE},
-{0x2206, 0x8AE5}, {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A},
-{0x2206, 0xFDE2}, {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102},
-{0x2206, 0x2DAC}, {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4},
-{0x2206, 0x03EE}, {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0},
-{0x2206, 0x00EE}, {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115},
-{0x2206, 0xE685}, {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08},
-{0x2206, 0xEE85}, {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100},
-{0x2206, 0xFDFC}, {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701},
-{0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000},
-{0x133E, 0x000E}, {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002},
-{0x2073, 0x1D22}, {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
-{0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010}, {0x2000, 0x1940},
-{0x2060, 0x1940}, {0x2080, 0x1940}, {0x2017, 0xA100}, {0x2077, 0xA100},
-{0x2097, 0xA100}, };
-/*End of ChipData01[][2]*/
-#endif
-
-#if defined(CHIP_RTL8365MB)
-uint16_t ChipData10[][2]= {
-/*Code of Func*/
-{0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
-{0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
-{0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
-{0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
-{0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
-{0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
-{0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
-{0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
-{0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
-{0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
-{0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
-{0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
-{0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
-{0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
-{0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
-{0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
-{0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
-{0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
-{0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
-{0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
-{0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
-{0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
-{0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
-{0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
-{0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
-{0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
-{0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
-{0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
-{0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
-{0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
-{0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
-{0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
-{0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
-{0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
-{0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
-{0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
-{0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
-{0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
-{0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
-{0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
-{0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
-{0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
-{0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
-{0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
-{0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
-{0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
-{0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
-{0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
-{0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
-{0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
-{0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
-{0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
-{0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
-{0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
-{0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
-{0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
-{0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
-{0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
-{0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
-{0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
-{0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
-{0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
-{0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
-{0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
-{0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
-{0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
-{0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
-{0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
-{0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
-{0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
-{0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
-{0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
-{0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
-{0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
-{0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
-{0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
-{0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
-{0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
-{0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
-{0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
-{0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
-{0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
-{0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
-{0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
-{0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
-{0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
-{0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
-{0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
-{0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
-{0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
-{0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
-{0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
-{0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
-{0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
-{0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
-{0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
-{0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
-{0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
-{0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
-{0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
-{0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
-{0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
-{0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
-{0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
-{0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
-{0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
-{0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
-{0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
-{0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
-{0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
-{0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
-{0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
-{0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
-{0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
-{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
-{0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
-{0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
-{0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
-{0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
-{0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
-{0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
-{0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
-{0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
-{0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
-{0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
-{0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
-{0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
-{0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
-{0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
-{0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
-{0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
-{0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
-{0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
-{0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
-{0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
-{0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
-{0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
-{0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
-{0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
-{0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
-{0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
-{0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
-{0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
-{0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
-{0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
-{0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
-{0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
-{0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
-{0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
-{0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
-{0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
-{0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
-{0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
-{0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
-{0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
-{0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
-{0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
-{0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
-{0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
-{0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
-{0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
-{0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
-{0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
-{0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
-{0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
-{0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
-{0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
-{0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
-{0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
-{0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
-{0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
-{0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
-{0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
-{0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
-{0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
-{0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
-{0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
-{0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
-{0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
-{0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
-{0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
-{0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
-{0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
-{0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
-{0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
-{0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
-{0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
-{0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
-{0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
-{0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
-{0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
-{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
-{0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
-{0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
-{0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
-{0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
-{0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
-{0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
-{0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
-{0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
-{0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
-{0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
-{0x13EB, 0x11BB}, {0x2097, 0xA11F}
- };
-/*End of ChipData10[][2]*/
-
-uint16_t ChipData11[][2]= {
-/*Code of Func*/
-{0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
-{0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
-{0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
-{0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
-{0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
-{0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
-{0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
-{0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
-{0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
-{0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
-{0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
-{0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
-{0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
-{0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
-{0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
-{0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
-{0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
-{0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
-{0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
-{0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
-{0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
-{0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
-{0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
-{0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
-{0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
-{0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
-{0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
-{0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
-{0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
-{0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
-{0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
-{0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
-{0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
-{0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
-{0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
-{0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
-{0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
-{0x133E, 0x000E}, {0x133F, 0x0010}, {0x2080, 0x1940}, {0x2097, 0xA100},
-};
-/*End of ChipData11[][2]*/
-
-#endif
-
-static rtk_api_ret_t _rtk_switch_init_setreg(uint32_t reg, uint32_t data);
-
-/* Function Name:
- * rtk_port_macForceLinkExt_set
- * Description:
- * Set external interface force linking configuration.
- * Input:
- * port - external port ID
- * mode - external interface mode
- * pPortability - port ability configuration
- * Output:
- * None
- * Return:
- * RT_ERR_OK - OK
- * RT_ERR_FAILED - Failed
- * RT_ERR_SMI - SMI access error
- * RT_ERR_INPUT - Invalid input parameters.
- * Note:
- * This API can set external interface force mode properties.
- * The external interface can be set to:
- * - MODE_EXT_DISABLE,
- * - MODE_EXT_RGMII,
- * - MODE_EXT_MII_MAC,
- * - MODE_EXT_MII_PHY,
- * - MODE_EXT_TMII_MAC,
- * - MODE_EXT_TMII_PHY,
- * - MODE_EXT_GMII,
- * - MODE_EXT_RMII_MAC,
- * - MODE_EXT_RMII_PHY,
- */
-rtk_api_ret_t
-rtk_port_macForceLinkExt_set(rtk_ext_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability)
-{
- rtk_api_ret_t retVal;
- rtl8367b_port_ability_t ability;
- uint32_t __attribute__((unused)) reg, mask;
-
- if (port >= EXT_PORT_END)
- return RT_ERR_INPUT;
-
- if (mode >=MODE_EXT_END)
- return RT_ERR_INPUT;
-
- if (mode == MODE_EXT_RGMII_33V)
- return RT_ERR_INPUT;
-
- if (pPortability->forcemode > 1 || pPortability->speed > 2 || pPortability->duplex > 1 ||
- pPortability->link > 1 || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1)
- return RT_ERR_INPUT;
-
- if(port == EXT_PORT_0)
- {
- reg = RTL8367B_REG_DIGITAL_INTERFACE_SELECT;
- mask = RTL8367B_SELECT_GMII_0_MASK;
- }
- else if(port == EXT_PORT_1)
- {
- reg = RTL8367B_REG_DIGITAL_INTERFACE_SELECT;
- mask = RTL8367B_SELECT_GMII_1_MASK;
- }
- else if(port == EXT_PORT_2)
- {
- reg = RTL8367B_REG_DIGITAL_INTERFACE_SELECT_1;
- mask = RTL8367B_SELECT_RGMII_2_MASK;
- }
- else
- return RT_ERR_INPUT;
-
- if ((retVal = rtl8367b_setAsicPortExtMode(port, mode)) != RT_ERR_OK)
- return retVal;
-
- if ((retVal = rtl8367b_getAsicPortForceLinkExt( (uint32_t)port, &ability)) != RT_ERR_OK)
- return retVal;
-
- ability.forcemode = pPortability->forcemode;
- ability.speed = pPortability->speed;
- ability.duplex = pPortability->duplex;
- ability.link = pPortability->link;
- ability.nway = pPortability->nway;
- ability.txpause = pPortability->txpause;
- ability.rxpause = pPortability->rxpause;
-
- if ((retVal = rtl8367b_setAsicPortForceLinkExt( (uint32_t)port, &ability)) != RT_ERR_OK)
- return retVal;
-
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtk_port_rgmiiDelayExt_set
- * Description:
- * Set RGMII interface delay value for TX and RX.
- * Input:
- * txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay
- * rxDelay - RX delay value, 0~7 for delay setup.
- * Output:
- * None
- * Return:
- * RT_ERR_OK - OK
- * RT_ERR_FAILED - Failed
- * RT_ERR_SMI - SMI access error
- * RT_ERR_INPUT - Invalid input parameters.
- * Note:
- * This API can set external interface 2 RGMII delay.
- * In TX delay, there are 2 selection: no-delay and 2ns delay.
- * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay.
- */
-rtk_api_ret_t
-rtk_port_rgmiiDelayExt_set(rtk_ext_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay)
-{
- rtk_api_ret_t retVal;
- uint32_t regAddr = 0;
- uint32_t regData = 0;
-
- if ((txDelay > 1) || (rxDelay > 7))
- return RT_ERR_INPUT;
-
- if (port >= EXT_PORT_END)
- return RT_ERR_INPUT;
-
- if(port == EXT_PORT_0)
- regAddr = RTL8367B_REG_EXT0_RGMXF;
- else if(port == EXT_PORT_1)
- regAddr = RTL8367B_REG_EXT1_RGMXF;
- else if(port == EXT_PORT_2)
- regAddr = RTL8367B_REG_EXT2_RGMXF;
- else
- return RT_ERR_INPUT;
-
- if ((retVal = rtl8367b_getAsicReg(regAddr, ®Data)) != RT_ERR_OK)
- return retVal;
-
- if (RGMII_TIMING_DEBUG) {
- printf("%s: pre regData 0x%x\n", __FUNCTION__, regData);
- }
-
- regData = (regData & 0xFFF0) | ((txDelay << 3) & 0x0008) | (rxDelay & 0x0007);
- if (RGMII_TIMING_DEBUG) {
- printf("%s: pst regData 0x%x\n", __FUNCTION__, regData);
- }
-
- if ((retVal = rtl8367b_setAsicReg(regAddr, regData)) != RT_ERR_OK)
- return retVal;
-
- return RT_ERR_OK;
-}
-
-static
-rtk_api_ret_t
-_rtk_switch_init_setreg(uint32_t reg, uint32_t data)
-{
- rtk_api_ret_t retVal;
-
- if((retVal = rtl8367b_setAsicReg(reg, data) != RT_ERR_OK))
- return retVal;
-
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtk_switch_init
- * Description:
- * Set chip to default configuration enviroment
- * Input:
- * None
- * Output:
- * None
- * Return:
- * RT_ERR_OK - OK
- * RT_ERR_FAILED - Failed
- * RT_ERR_SMI - SMI access error
- * Note:
- * The API can set chip registers to default configuration for different release chip model.
- */
-rtk_api_ret_t
-rtk_switch_init(void)
-{
- uint16_t i = 0;
- uint32_t data = 0;
- rtk_api_ret_t retVal = 0;
- uint32_t phy;
-#if defined(CHIP_AUTO_DETECT)
- uint32_t polling_time;
- uint32_t chip_idx = 0;
-#endif
-
- if((retVal = rtl8367b_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)
- return retVal;
-
- if((retVal = rtl8367b_getAsicReg(0x1301, &data)) != RT_ERR_OK)
- return retVal;
-
-#if defined(CHIP_RTL8363SB)
- if(data & 0xF000)
- {
- init_para = ChipData01;
- init_size = (sizeof(ChipData01) / ((sizeof(uint16_t))*2));
- }
- else
- {
- init_para = ChipData00;
- init_size = (sizeof(ChipData00) / ((sizeof(uint16_t))*2));
- }
-#elif defined(CHIP_RTL8365MB)
- if(data & 0xF000)
- {
- init_para = ChipData11;
- init_size = (sizeof(ChipData11) / ((sizeof(uint16_t))*2));
- }
- else
- {
- init_para = ChipData10;
- init_size = (sizeof(ChipData10) / ((sizeof(uint16_t))*2));
- }
-#else
- /* Not define CHIP, Error */
- init_para = NULL;
-#endif
-
- if(init_para == NULL)
- return RT_ERR_CHIP_NOT_SUPPORTED;
-
- /* Analog parameter update. ID:0001 */
- for(phy = 0; phy <= RTK_PHY_ID_MAX; phy++)
- {
- if((retVal = rtl8367b_setAsicPHYReg(phy, 31, 0x7)) != RT_ERR_OK)
- return retVal;
-
- if((retVal = rtl8367b_setAsicPHYReg(phy, 30, 0x2c)) != RT_ERR_OK)
- return retVal;
-
- if((retVal = rtl8367b_setAsicPHYReg(phy, 25, 0x0504)) != RT_ERR_OK)
- return retVal;
-
- if((retVal = rtl8367b_setAsicPHYReg(phy, 31, 0x0)) != RT_ERR_OK)
- return retVal;
- }
-
- for(i = 0; i < init_size; i++)
- {
- if((retVal = _rtk_switch_init_setreg((uint32_t)init_para[i][0], (uint32_t)init_para[i][1])) != RT_ERR_OK)
- return retVal;
- }
-
- /* Analog parameter update. ID:0002 */
- if((retVal = rtl8367b_setAsicPHYReg(1, 31, 0x2)) != RT_ERR_OK)
- return retVal;
-
- if((retVal = rtl8367b_getAsicPHYReg(1, 17, &data)) != RT_ERR_OK)
- return retVal;
-
- data |= 0x01E0;
-
- if((retVal = rtl8367b_setAsicPHYReg(1, 17, data)) != RT_ERR_OK)
- return retVal;
-
- if((retVal = rtl8367b_setAsicPHYReg(1, 31, 0x0)) != RT_ERR_OK)
- return retVal;
-
-
- if((retVal = rtl8367b_setAsicRegBit(0x18e0, 0, 0)) != RT_ERR_OK)
- return retVal;
-
- if((retVal = rtl8367b_setAsicReg(0x1303, 0x0778)) != RT_ERR_OK)
- return retVal;
- if((retVal = rtl8367b_setAsicReg(0x1304, 0x7777)) != RT_ERR_OK)
- return retVal;
- if((retVal = rtl8367b_setAsicReg(0x13E2, 0x01FE)) != RT_ERR_OK)
- return retVal;
-
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_setAsicRegBit
- * Description:
- * Set a bit value of a specified register
- * Input:
- * reg - register's address
- * bit - bit location
- * value - value to set. It can be value 0 or 1.
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_INPUT - Invalid input parameter
- * Note:
- * Set a bit of a specified register to 1 or 0.
- */
-ret_t
-rtl8367b_setAsicRegBit(uint32_t reg, uint32_t bit, uint32_t value)
-{
-
- uint32_t regData = 0;
- ret_t retVal = 0;
-
- if(bit >= RTL8367B_REGBITLENGTH)
- return RT_ERR_INPUT;
-
- retVal = smi_read(reg, ®Data);
- if(retVal != RT_ERR_OK)
- return RT_ERR_SMI;
-
- if(value)
- regData = regData | (1 << bit);
- else
- regData = regData & (~(1 << bit));
-
- retVal = smi_write(reg, regData);
- if(retVal != RT_ERR_OK)
- return RT_ERR_SMI;
-
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_getAsicRegBit
- * Description:
- * Get a bit value of a specified register
- * Input:
- * reg - register's address
- * bit - bit location
- * value - value to get.
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_INPUT - Invalid input parameter
- * Note:
- * None
- */
-ret_t
-rtl8367b_getAsicRegBit(uint32_t reg, uint32_t bit, uint32_t *pValue)
-{
- uint32_t regData = 0;
- ret_t retVal = 0;
-
- retVal = smi_read(reg, ®Data);
- if(retVal != RT_ERR_OK)
- return RT_ERR_SMI;
-
- *pValue = (regData & (0x1 << bit)) >> bit;
-
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_setAsicRegBits
- * Description:
- * Set bits value of a specified register
- * Input:
- * reg - register's address
- * bits - bits mask for setting
- * value - bits value for setting
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_INPUT - Invalid input parameter
- * Note:
- * Set bits of a specified register to value. Both bits and value are be treated as bit-mask
- */
-ret_t
-rtl8367b_setAsicRegBits(uint32_t reg, uint32_t bits, uint32_t value)
-{
- uint32_t regData = 0;
- ret_t retVal = 0;
- uint32_t bitsShift = 0;
- uint32_t valueShifted = 0;
-
- if(bits >= (1 << RTL8367B_REGBITLENGTH) )
- return RT_ERR_INPUT;
-
- bitsShift = 0;
- while(!(bits & (1 << bitsShift)))
- {
- bitsShift++;
- if(bitsShift >= RTL8367B_REGBITLENGTH)
- return RT_ERR_INPUT;
- }
- valueShifted = value << bitsShift;
-
- if(valueShifted > RTL8367B_REGDATAMAX)
- return RT_ERR_INPUT;
-
- retVal = smi_read(reg, ®Data);
- if(retVal != RT_ERR_OK)
- return RT_ERR_SMI;
-
- regData = regData & (~bits);
- regData = regData | (valueShifted & bits);
-
- retVal = smi_write(reg, regData);
- if(retVal != RT_ERR_OK)
- return RT_ERR_SMI;
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_getAsicRegBits
- * Description:
- * Get bits value of a specified register
- * Input:
- * reg - register's address
- * bits - bits mask for setting
- * value - bits value for setting
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_INPUT - Invalid input parameter
- * Note:
- * None
- */
-ret_t
-rtl8367b_getAsicRegBits(uint32_t reg, uint32_t bits, uint32_t *pValue)
-{
- uint32_t regData = 0;
- ret_t retVal = 0;
- uint32_t bitsShift = 0;
-
- if(bits>= (1<<RTL8367B_REGBITLENGTH) )
- return RT_ERR_INPUT;
-
- bitsShift = 0;
- while(!(bits & (1 << bitsShift)))
- {
- bitsShift++;
- if(bitsShift >= RTL8367B_REGBITLENGTH)
- return RT_ERR_INPUT;
- }
-
- retVal = smi_read(reg, ®Data);
- if(retVal != RT_ERR_OK) return RT_ERR_SMI;
-
- *pValue = (regData & bits) >> bitsShift;
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_setAsicReg
- * Description:
- * Set content of asic register
- * Input:
- * reg - register's address
- * value - Value setting to register
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * Note:
- * The value will be set to ASIC mapping address only and it is always return RT_ERR_OK while setting un-mapping address registers
- */
-ret_t
-rtl8367b_setAsicReg(uint32_t reg, uint32_t value)
-{
- ret_t retVal = 0;
-
- retVal = smi_write(reg, value);
- if(retVal != RT_ERR_OK)
- return RT_ERR_SMI;
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_getAsicReg
- * Description:
- * Get content of asic register
- * Input:
- * reg - register's address
- * value - Value setting to register
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * Note:
- * Value 0x0000 will be returned for ASIC un-mapping address
- */
-ret_t
-rtl8367b_getAsicReg(uint32_t reg, uint32_t *pValue)
-{
- uint32_t regData = 0;
- ret_t retVal = 0;
-
- retVal = smi_read(reg, ®Data);
- if(retVal != RT_ERR_OK)
- return RT_ERR_SMI;
-
- *pValue = regData;
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_setAsicPortExtMode
- * Description:
- * Set external interface mode configuration
- * Input:
- * id - external interface id (0~2)
- * mode - external interface mode
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_OUT_OF_RANGE - input parameter out of range
- * Note:
- * None
- */
-ret_t
-rtl8367b_setAsicPortExtMode(uint32_t id, uint32_t mode)
-{
- ret_t retVal = 0;
-
- if(id >= RTL8367B_EXTNO)
- return RT_ERR_OUT_OF_RANGE;
-
- if(mode >= EXT_END)
- return RT_ERR_OUT_OF_RANGE;
-
- if(mode == EXT_GMII)
- {
- if( (retVal = rtl8367b_setAsicRegBit(RTL8367B_REG_EXT0_RGMXF, RTL8367B_EXT0_RGTX_INV_OFFSET, 1)) != RT_ERR_OK)
- return retVal;
-
- if( (retVal = rtl8367b_setAsicRegBit(RTL8367B_REG_EXT1_RGMXF, RTL8367B_EXT1_RGTX_INV_OFFSET, 1)) != RT_ERR_OK)
- return retVal;
-
- if( (retVal = rtl8367b_setAsicRegBits(RTL8367B_REG_EXT_TXC_DLY, RTL8367B_EXT1_GMII_TX_DELAY_MASK, 5)) != RT_ERR_OK)
- return retVal;
-
- if( (retVal = rtl8367b_setAsicRegBits(RTL8367B_REG_EXT_TXC_DLY, RTL8367B_EXT0_GMII_TX_DELAY_MASK, 6)) != RT_ERR_OK)
- return retVal;
- }
-
- if( (mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY) )
- {
- if( (retVal = rtl8367b_setAsicRegBit(RTL8367B_REG_BYPASS_LINE_RATE, id, 1)) != RT_ERR_OK)
- return retVal;
- }
- else
- {
- if( (retVal = rtl8367b_setAsicRegBit(RTL8367B_REG_BYPASS_LINE_RATE, id, 0)) != RT_ERR_OK)
- return retVal;
- }
-
- if(0 == id || 1 == id)
- return rtl8367b_setAsicRegBits(RTL8367B_REG_DIGITAL_INTERFACE_SELECT, RTL8367B_SELECT_GMII_0_MASK << (id * RTL8367B_SELECT_GMII_1_OFFSET), mode);
- else
- return rtl8367b_setAsicRegBits(RTL8367B_REG_DIGITAL_INTERFACE_SELECT_1, RTL8367B_SELECT_RGMII_2_MASK, mode);
-}
-
-/* Function Name:
- * rtl8367b_getAsicPortForceLinkExt
- * Description:
- * Get external interface force linking configuration
- * Input:
- * id - external interface id (0~1)
- * pPortAbility - port ability configuration
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_OUT_OF_RANGE - input parameter out of range
- * Note:
- * None
- */
-ret_t
-rtl8367b_getAsicPortForceLinkExt(uint32_t id, rtl8367b_port_ability_t *pPortAbility)
-{
- uint32_t reg_data = 0;
- uint16_t ability_data = 0;
- ret_t retVal = 0;
-
- /* Invalid input parameter */
- if(id >= RTL8367B_EXTNO)
- return RT_ERR_OUT_OF_RANGE;
-
- if(0 == id || 1 == id)
- retVal = rtl8367b_getAsicReg(RTL8367B_REG_DIGITAL_INTERFACE0_FORCE+id, ®_data);
- else
- retVal = rtl8367b_getAsicReg(RTL8367B_REG_DIGITAL_INTERFACE2_FORCE, ®_data);
-
- if(retVal != RT_ERR_OK)
- return retVal;
-
- ability_data = (uint16_t)reg_data;
- memcpy(pPortAbility, &ability_data, sizeof(rtl8367b_port_ability_t));
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_setAsicPortForceLinkExt
- * Description:
- * Set external interface force linking configuration
- * Input:
- * id - external interface id (0~2)
- * portAbility - port ability configuration
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_OUT_OF_RANGE - input parameter out of range
- * Note:
- * None
- */
-ret_t
-rtl8367b_setAsicPortForceLinkExt(uint32_t id, rtl8367b_port_ability_t *pPortAbility)
-{
- uint32_t reg_data = 0;
-
- /* Invalid input parameter */
- if(id >= RTL8367B_EXTNO)
- return RT_ERR_OUT_OF_RANGE;
-
- reg_data = (uint32_t)(*(uint16_t *)pPortAbility);
-
- if(0 == id || 1 == id)
- return rtl8367b_setAsicReg(RTL8367B_REG_DIGITAL_INTERFACE0_FORCE + id, reg_data);
- else
- return rtl8367b_setAsicReg(RTL8367B_REG_DIGITAL_INTERFACE2_FORCE, reg_data);
-}
-
-/* Function Name:
- * rtl8367b_setAsicPHYReg
- * Description:
- * Set PHY registers
- * Input:
- * phyNo - Physical port number (0~4)
- * phyAddr - PHY address (0~31)
- * phyData - Writing data
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_PHY_REG_ID - invalid PHY address
- * RT_ERR_PHY_ID - invalid PHY no
- * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
- * Note:
- * None
- */
-ret_t
-rtl8367b_setAsicPHYReg( uint32_t phyNo, uint32_t phyAddr, uint32_t value)
-{
- uint32_t regAddr;
-
- if(phyNo > RTL8367B_PHY_INTERNALNOMAX)
- return RT_ERR_PORT_ID;
-
- if(phyAddr > RTL8367B_PHY_REGNOMAX)
- return RT_ERR_PHY_REG_ID;
-
- regAddr = 0x2000 + (phyNo << 5) + phyAddr;
-
- return rtl8367b_setAsicReg(regAddr, value);
-}
-
-/* Function Name:
- * rtl8367b_getAsicPHYReg
- * Description:
- * Get PHY registers
- * Input:
- * phyNo - Physical port number (0~4)
- * phyAddr - PHY address (0~31)
- * pRegData - Writing data
- * Output:
- * None
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_SMI - SMI access error
- * RT_ERR_PHY_REG_ID - invalid PHY address
- * RT_ERR_PHY_ID - invalid PHY no
- * RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
- * Note:
- * None
- */
-ret_t
-rtl8367b_getAsicPHYReg( uint32_t phyNo, uint32_t phyAddr, uint32_t *value)
-{
- uint32_t regAddr;
-
- if(phyNo > RTL8367B_PHY_INTERNALNOMAX)
- return RT_ERR_PORT_ID;
-
- if(phyAddr > RTL8367B_PHY_REGNOMAX)
- return RT_ERR_PHY_REG_ID;
-
- regAddr = 0x2000 + (phyNo << 5) + phyAddr;
-
- return rtl8367b_getAsicReg(regAddr, value);
-}
diff --git a/board/ruby/rtl8367b/rtl8367b_init.c b/board/ruby/rtl8367b/rtl8367b_init.c
deleted file mode 100644
index 5e99cb3..0000000
--- a/board/ruby/rtl8367b/rtl8367b_init.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright (C) 2012 Realtek Semiconductor Corp.
- * All Rights Reserved.
- *
- * This program is the proprietary software of Realtek Semiconductor
- * Corporation and/or its licensors, and only be used, duplicated,
- * modified or distributed under the authorized license from Realtek.
- *
- * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
- * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
- *
- * $Revision: $
- * $Date: $
- *
- * Purpose : RTK switch driver module init for RTL8367/RTL8367B
- * Feature : Init switch and configure it for operation
- *
- */
-
-#include "rtl8367b_init.h"
-#include "rtl8367b_smi.h"
-#include <asm/arch/arasan_emac_ahb.h>
-
-ret_t rtl8367b_poll_linkup(struct emac_private *priv)
-{
- /* either PHY1 or PHY2 should have link established */
- const uint32_t delay_us = 1000;
- const int poll_secs = 2;
- const uint32_t mask = PhyLinkIsUp | PhyAutoNegComplete;
- const unsigned long start = get_timer(0);
-
- printf("%s: polling for link up...\n", __FUNCTION__);
-
- while (1) {
- int phy;
-
- for (phy = RTL8367B_QTN_EXT_PHY_ADDR_MIN; phy <= RTL8367B_QTN_EXT_PHY_ADDR_MAX; phy++) {
- uint32_t val;
-
- if (rtl8367b_getAsicPHYReg(phy, PhyBMSR, &val) != RT_ERR_OK) {
- return -1;
- }
-
- if ((val & mask) == mask) {
- printf("%s: link found, phy %d\n",
- __FUNCTION__, phy);
- return 0;
- }
- }
-
- if (ctrlc() || (get_timer(start) > (poll_secs * CONFIG_SYS_HZ))) {
- break;
- }
-
- udelay(delay_us);
- }
-
- printf("%s: no link found\n", __FUNCTION__);
-
- return -1;
-}
-
-static void rtl8367b_ext_reset(void)
-{
- const int delay_us = 20000;
- uint32_t mask = RUBY_SYS_CTL_RESET_EXT;
-
- writel(mask, RUBY_SYS_CTL_CPU_VEC_MASK);
-
- writel(0, RUBY_SYS_CTL_CPU_VEC);
- udelay(delay_us);
- writel(mask, RUBY_SYS_CTL_CPU_VEC);
- udelay(delay_us);
- writel(0, RUBY_SYS_CTL_CPU_VEC);
- udelay(delay_us);
-
- writel(0, RUBY_SYS_CTL_CPU_VEC_MASK);
-}
-
-static uint32_t smi_mdio_read_adapter(struct emac_private *priv, uint8_t reg)
-{
- uint32_t val;
-
- if (rtl8367b_getAsicPHYReg(priv->phy_addr, reg, &val) != RT_ERR_OK) {
- return MDIO_READ_FAIL;
- }
-
- return val;
-}
-
-static int smi_mdio_write_adapter(struct emac_private *priv, uint8_t reg, uint16_t value)
-{
- return rtl8367b_setAsicPHYReg(priv->phy_addr, reg, value);
-}
-
-static ret_t rtl8367b_init_port(rtk_port_mac_ability_t *mac_cfg, rtk_mode_ext_t mode, rtk_ext_port_t port)
-{
- ret_t ret;
- rtk_data_t rgmii_tx_delay = 0;
- rtk_data_t rgmii_rx_delay = 4;
-
- ret = rtk_port_macForceLinkExt_set(port, mode, mac_cfg);
- if (RT_ERR_OK != ret) {
- printf("rtk_port_macForceLinkExt_set failed, port %d (%d)\n", port, ret);
- return ret;
- }
-
- ret = rtk_port_rgmiiDelayExt_set(port, rgmii_tx_delay, rgmii_rx_delay);
- if (RT_ERR_OK != ret) {
- printf("rtk_port_rgmiiDelayExt_set failed, port %d (%d)\n", port, ret);
- return ret;
- }
-
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * rtl8367b_init
- * Description:
- * Initialize RTL8367B Chipsets
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_FAILED - Failure
- * Note:
- * None
- */
-ret_t rtl8367b_init(struct emac_private *priv, uint32_t emac_cfg)
-{
- ret_t ret = RT_ERR_OK;
- rtk_port_mac_ability_t mac_cfg;
- rtk_mode_ext_t mode;
-
- printf("%s...\n", __FUNCTION__);
-
- priv->mdio->read = &smi_mdio_read_adapter;
- priv->mdio->write = &smi_mdio_write_adapter;
-
- rtl8367b_ext_reset();
-
- smi_mdio_base_set(priv->mdio->base);
- ret = rtk_switch_init();
- if (RT_ERR_OK != ret) {
- printf("rtl8635MB switch init failed!!! (%d)\n", ret);
- return ret;
- }
-
- /*
- * Set external interface 0 to RGMII with Force mode, 1000M, Full-duplex,
- * enable TX&RX pause
- */
- mode = MODE_EXT_RGMII;
- mac_cfg.forcemode = MAC_FORCE;
- mac_cfg.speed = SPD_1000M;
- mac_cfg.duplex = FULL_DUPLEX;
- mac_cfg.link = PORT_LINKUP;
- mac_cfg.nway = DISABLED;
- mac_cfg.txpause = ENABLED;
- mac_cfg.rxpause = ENABLED;
-
- if (emac_cfg & EMAC_PHY_RTL8363SB_P0) {
- ret = rtl8367b_init_port(&mac_cfg, mode, EXT_PORT_0);
- if (RT_ERR_OK != ret) {
- return ret;
- }
- }
-
- if (emac_cfg & EMAC_PHY_RTL8363SB_P1) {
- ret = rtl8367b_init_port(&mac_cfg, mode, EXT_PORT_1);
- if (RT_ERR_OK != ret) {
- return ret;
- }
- }
-
- printf("%s completed successfully\n", __FUNCTION__);
-
- return ret;
-}
-
diff --git a/board/ruby/rtl8367b/rtl8367b_init.h b/board/ruby/rtl8367b/rtl8367b_init.h
deleted file mode 100644
index d48d854..0000000
--- a/board/ruby/rtl8367b/rtl8367b_init.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Copyright(c) Realtek Semiconductor Corporation, 2008
- * All rights reserved.
- *
- * $Revision: 28599 $
- * $Date: 2012-05-07 09:41:37 +0800 (星期一, 07 五月 2012) $
- *
- * Purpose : Definition function prototype of RTK API.
- *
- * Feature : Function prototype definition
- *
- */
-
-#ifndef __RTL8367B_INIT_H__
-#define __RTL8367B_INIT_H__
-
-#include "../ruby.h"
-#include "malloc.h"
-
-#define _LITTLE_ENDIAN
-#undef CHIP_RTL8365MB
-#define CHIP_RTL8363SB
-
-#define RTL8367B_REG_DIGITAL_INTERFACE_SELECT 0x1305
-#define RTL8367B_SELECT_GMII_1_OFFSET 4
-#define RTL8367B_SELECT_GMII_1_MASK 0xF0
-#define RTL8367B_SELECT_GMII_0_OFFSET 0
-#define RTL8367B_SELECT_GMII_0_MASK 0xF
-#define RTL8367B_REG_DIGITAL_INTERFACE_SELECT_1 0x13c3
-#define RTL8367B_SKIP_MII_2_RXER_OFFSET 4
-#define RTL8367B_SKIP_MII_2_RXER_MASK 0x10
-#define RTL8367B_SELECT_RGMII_2_OFFSET 0
-#define RTL8367B_SELECT_RGMII_2_MASK 0xF
-#define RTL8367B_REG_EXT0_RGMXF 0x1306
-#define RTL8367B_REG_EXT1_RGMXF 0x1307
-#define RTL8367B_REG_EXT2_RGMXF 0x13c5
-#define RTL8367B_REGBITLENGTH 16
-#define RTL8367B_REGDATAMAX 0xFFFF
-#define RTL8367B_MAC7 7
-#define RTL8367B_EXTNO 3
-#define RTL8367B_EXT0_RGTX_INV_OFFSET 6
-#define RTL8367B_EXT0_RGTX_INV_MASK 0x40
-#define RTL8367B_EXT0_RGRX_INV_OFFSET 5
-#define RTL8367B_EXT0_RGRX_INV_MASK 0x20
-#define RTL8367B_EXT0_RGMXF_OFFSET 0
-#define RTL8367B_EXT0_RGMXF_MASK 0x1F
-#define RTL8367B_EXT1_RGTX_INV_OFFSET 6
-#define RTL8367B_EXT1_RGTX_INV_MASK 0x40
-#define RTL8367B_EXT1_RGRX_INV_OFFSET 5
-#define RTL8367B_EXT1_RGRX_INV_MASK 0x20
-#define RTL8367B_EXT1_RGMXF_OFFSET 0
-#define RTL8367B_EXT1_RGMXF_MASK 0x1F
-#define RTL8367B_REG_EXT_TXC_DLY 0x13f9
-#define RTL8367B_EXT1_GMII_TX_DELAY_OFFSET 12
-#define RTL8367B_EXT1_GMII_TX_DELAY_MASK 0x7000
-#define RTL8367B_EXT0_GMII_TX_DELAY_OFFSET 9
-#define RTL8367B_EXT0_GMII_TX_DELAY_MASK 0xE00
-#define RTL8367B_EXT2_RGMII_TX_DELAY_OFFSET 6
-#define RTL8367B_EXT2_RGMII_TX_DELAY_MASK 0x1C0
-#define RTL8367B_EXT1_RGMII_TX_DELAY_OFFSET 3
-#define RTL8367B_EXT1_RGMII_TX_DELAY_MASK 0x38
-#define RTL8367B_EXT0_RGMII_TX_DELAY_OFFSET 0
-#define RTL8367B_EXT0_RGMII_TX_DELAY_MASK 0x7
-#define RTL8367B_REG_BYPASS_LINE_RATE 0x03f7
-#define RTL8367B_REG_DIGITAL_INTERFACE0_FORCE 0x1310
-#define RTL8367B_GMII_0_FORCE_OFFSET 12
-#define RTL8367B_GMII_0_FORCE_MASK 0x1000
-#define RTL8367B_RGMII_0_FORCE_OFFSET 0
-#define RTL8367B_RGMII_0_FORCE_MASK 0xFFF
-#define RTL8367B_REG_DIGITAL_INTERFACE1_FORCE 0x1311
-#define RTL8367B_GMII_1_FORCE_OFFSET 12
-#define RTL8367B_GMII_1_FORCE_MASK 0x1000
-#define RTL8367B_RGMII_1_FORCE_OFFSET 0
-#define RTL8367B_RGMII_1_FORCE_MASK 0xFFF
-#define RTL8367B_REG_DIGITAL_INTERFACE2_FORCE 0x13c4
-#define RTL8367B_GMII_2_FORCE_OFFSET 12
-#define RTL8367B_GMII_2_FORCE_MASK 0x1000
-#define RTL8367B_RGMII_2_FORCE_OFFSET 0
-#define RTL8367B_RGMII_2_FORCE_MASK 0xFFF
-#define RTK_INDRECT_ACCESS_CRTL 0x1f00
-#define RTK_INDRECT_ACCESS_STATUS 0x1f01
-#define RTK_INDRECT_ACCESS_ADDRESS 0x1f02
-#define RTK_INDRECT_ACCESS_WRITE_DATA 0x1f03
-#define RTK_INDRECT_ACCESS_READ_DATA 0x1f04
-#define RTK_INDRECT_ACCESS_DELAY 0x1f80
-#define RTK_INDRECT_ACCESS_BURST 0x1f81
-#define RTK_RW_MASK 0x2
-#define RTK_CMD_MASK 0x1
-#define RTK_PHY_BUSY_OFFSET 2
-#define RTK_IVL_MODE_FID 0xFFFF
-#define RTL8367B_REG_INDRECT_ACCESS_CTRL 0x1f00
-#define RTL8367B_RW_OFFSET 1
-#define RTL8367B_RW_MASK 0x2
-#define RTL8367B_CMD_OFFSET 0
-#define RTL8367B_CMD_MASK 0x1
-#define RTL8367B_REG_INDRECT_ACCESS_STATUS 0x1f01
-#define RTL8367B_INDRECT_ACCESS_STATUS_OFFSET 2
-#define RTL8367B_INDRECT_ACCESS_STATUS_MASK 0x4
-#define RTL8367B_REG_INDRECT_ACCESS_ADDRESS 0x1f02
-#define RTL8367B_REG_INDRECT_ACCESS_WRITE_DATA 0x1f03
-#define RTL8367B_REG_INDRECT_ACCESS_READ_DATA 0x1f04
-
-typedef uint32_t rtk_api_ret_t;
-typedef uint32_t ret_t;
-typedef uint64_t rtk_u_long_t;
-typedef uint32_t rtk_data_t;
-
-#define HERE do { if (0) printf("%s:%d:%s\n", __FILE__, __LINE__, __FUNCTION__); } while(0)
-#define MDIO_DEBUG 0
-#define RGMII_TIMING_DEBUG 0
-#define SMI_SWEEP_MAX 0x8000
-
-/*
- * Data Type Declaration
- */
-typedef enum rt_error_code_e
-{
- RT_ERR_FAILED = -1, /* General Error */
-
- /* 0x0000xxxx for common error code */
- RT_ERR_OK = 0, /* 0x00000000, OK */
- RT_ERR_INPUT, /* 0x00000001, invalid input parameter */
- RT_ERR_UNIT_ID, /* 0x00000002, invalid unit id */
- RT_ERR_PORT_ID, /* 0x00000003, invalid port id */
- RT_ERR_PORT_MASK, /* 0x00000004, invalid port mask */
- RT_ERR_PORT_LINKDOWN, /* 0x00000005, link down port status */
- RT_ERR_ENTRY_INDEX, /* 0x00000006, invalid entry index */
- RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */
- RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */
- RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */
- RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */
- RT_ERR_MAC, /* 0x0000000b, invalid mac address */
- RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */
- RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */
- RT_ERR_SMI, /* 0x0000000e, SMI error */
- RT_ERR_NOT_INIT, /* 0x0000000f, The module is not initial */
- RT_ERR_CHIP_NOT_FOUND, /* 0x00000010, The chip can not found */
- RT_ERR_NOT_ALLOWED, /* 0x00000011, actions not allowed by the function */
- RT_ERR_DRIVER_NOT_FOUND, /* 0x00000012, The driver can not found */
- RT_ERR_SEM_LOCK_FAILED, /* 0x00000013, Failed to lock semaphore */
- RT_ERR_SEM_UNLOCK_FAILED, /* 0x00000014, Failed to unlock semaphore */
- RT_ERR_ENABLE, /* 0x00000015, invalid enable parameter */
- RT_ERR_TBL_FULL, /* 0x00000016, input table full */
-
- /* 0x000exxxx for port ability */
- RT_ERR_PHY_PAGE_ID = 0x000e0000, /* 0x000e0000, invalid PHY page id */
- RT_ERR_PHY_REG_ID, /* 0x000e0001, invalid PHY reg id */
- RT_ERR_PHY_DATAMASK, /* 0x000e0002, invalid PHY data mask */
- RT_ERR_PHY_AUTO_NEGO_MODE, /* 0x000e0003, invalid PHY auto-negotiation mode*/
- RT_ERR_PHY_SPEED, /* 0x000e0004, invalid PHY speed setting */
- RT_ERR_PHY_DUPLEX, /* 0x000e0005, invalid PHY duplex setting */
- RT_ERR_PHY_FORCE_ABILITY, /* 0x000e0006, invalid PHY force mode ability parameter */
- RT_ERR_PHY_FORCE_1000, /* 0x000e0007, invalid PHY force mode 1G speed setting */
- RT_ERR_PHY_TXRX, /* 0x000e0008, invalid PHY tx/rx */
- RT_ERR_PHY_ID, /* 0x000e0009, invalid PHY id */
- RT_ERR_PHY_RTCT_NOT_FINISH, /* 0x000e000a, PHY RTCT in progress */
-} rt_error_code_t;
-
-typedef enum rtk_enable_e
-{
- DISABLED = 0,
- ENABLED,
- RTK_ENABLE_END
-} rtk_enable_t;
-
-typedef enum rtk_port_linkStatus_e
-{
- PORT_LINKDOWN = 0,
- PORT_LINKUP,
- PORT_LINKSTATUS_END
-} rtk_port_linkStatus_t;
-
-/* enum for port current link speed */
-enum SPEEDMODE
-{
- SPD_10M = 0,
- SPD_100M,
- SPD_1000M
-};
-
-/* enum for mac link mode */
-enum LINKMODE
-{
- MAC_NORMAL = 0,
- MAC_FORCE,
-};
-
-/* enum for port current link duplex mode */
-enum DUPLEXMODE
-{
- HALF_DUPLEX = 0,
- FULL_DUPLEX
-};
-
-/* enum for port current MST mode */
-enum MSTMODE
-{
- SLAVE_MODE= 0,
- MASTER_MODE
-};
-
-enum EXTMODE
-{
- EXT_DISABLE = 0,
- EXT_RGMII,
- EXT_MII_MAC,
- EXT_MII_PHY,
- EXT_TMII_MAC,
- EXT_TMII_PHY,
- EXT_GMII,
- EXT_RMII_MAC,
- EXT_RMII_PHY,
- EXT_END
-};
-
-typedef struct rtk_port_mac_ability_s
-{
- uint32_t forcemode;
- uint32_t speed;
- uint32_t duplex;
- uint32_t link;
- uint32_t nway;
- uint32_t txpause;
- uint32_t rxpause;
-} rtk_port_mac_ability_t;
-
-typedef enum rtk_mode_ext_e
-{
- MODE_EXT_DISABLE = 0,
- MODE_EXT_RGMII,
- MODE_EXT_MII_MAC,
- MODE_EXT_MII_PHY,
- MODE_EXT_TMII_MAC,
- MODE_EXT_TMII_PHY,
- MODE_EXT_GMII,
- MODE_EXT_RMII_MAC,
- MODE_EXT_RMII_PHY,
- MODE_EXT_RGMII_33V,
- MODE_EXT_END
-} rtk_mode_ext_t;
-
-typedef enum rtk_ext_port_e
-{
- EXT_PORT_0 = 0,
- EXT_PORT_1,
- EXT_PORT_2,
- EXT_PORT_END
-} rtk_ext_port_t;
-
-typedef struct rtl8367b_port_ability_s {
-#ifdef _LITTLE_ENDIAN
-uint16_t speed:2;
-uint16_t duplex:1;
-uint16_t reserve1:1;
-uint16_t link:1;
-uint16_t rxpause:1;
-uint16_t txpause:1;
-uint16_t nway:1;
-uint16_t mstmode:1;
-uint16_t mstfault:1;
-uint16_t reserve2:2;
-uint16_t forcemode:1;
-uint16_t reserve3:3;
-#else
-uint16_t reserve3:3;
-uint16_t forcemode:1;
-uint16_t reserve2:2;
-uint16_t mstfault:1;
-uint16_t mstmode:1;
-uint16_t nway:1;
-uint16_t txpause:1;
-uint16_t rxpause:1;
-uint16_t link:1;
-uint16_t reserve1:1;
-uint16_t duplex:1;
-uint16_t speed:2;
-#endif
-} rtl8367b_port_ability_t;
-
-#define RTK_MAX_NUM_OF_INTERRUPT_TYPE 2
-#define RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST 1
-#define RTK_MAX_NUM_OF_PRIORITY 8
-#define RTK_MAX_NUM_OF_QUEUE 8
-#define RTK_MAX_NUM_OF_TRUNK_HASH_VAL 1
-#define RTK_MAX_NUM_OF_PORT 8
-#define RTK_PORT_ID_MAX (RTK_MAX_NUM_OF_PORT-1)
-#define RTK_PHY_ID_MAX (RTK_MAX_NUM_OF_PORT-4)
-#define RTK_PORT_COMBO_ID 4
-#define RTK_MAX_NUM_OF_PROTO_TYPE 0xFFFF
-#define RTK_MAX_NUM_OF_MSTI 0xF
-#define RTK_MAX_NUM_OF_LEARN_LIMIT 0x840
-#define RTK_MAX_PORT_MASK 0xFF
-#define RTK_EFID_MAX 0x7
-#define RTK_FID_MAX 0xF
-#define RTK_MAX_NUM_OF_FILTER_TYPE 5
-#define RTK_MAX_NUM_OF_FILTER_FIELD 8
-#define RTL8367B_PHY_INTERNALNOMAX 0x4
-#define RTL8367B_PHY_REGNOMAX 0x1F
-#define RTL8367B_PHY_EXTERNALMAX 0x7
-#define RTL8367B_PHY_BASE 0x2000
-#define RTL8367B_PHY_EXT_BASE 0xA000
-#define RTL8367B_PHY_OFFSET 5
-#define RTL8367B_PHY_EXT_OFFSET 9
-#define RTL8367B_PHY_PAGE_ADDRESS 31
-
-#define RTL8367B_QTN_EXT_PHY_ADDR_MIN 1
-#define RTL8367B_QTN_EXT_PHY_ADDR_MAX 2
-
-rtk_api_ret_t rtk_port_macForceLinkExt_set(rtk_ext_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability);
-rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_ext_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay);
-rtk_api_ret_t rtk_switch_init(void);
-
-struct emac_private;
-ret_t rtl8367b_poll_linkup(struct emac_private *priv);
-ret_t rtl8367b_init(struct emac_private *priv, uint32_t emac_cfg);
-ret_t rtl8367b_setAsicRegBit(uint32_t reg, uint32_t bit, uint32_t value);
-ret_t rtl8367b_getAsicRegBit(uint32_t reg, uint32_t bit, uint32_t *pValue);
-ret_t rtl8367b_setAsicRegBits(uint32_t reg, uint32_t bits, uint32_t value);
-ret_t rtl8367b_getAsicRegBits(uint32_t reg, uint32_t bits, uint32_t *pValue);
-ret_t rtl8367b_setAsicReg(uint32_t reg, uint32_t value);
-ret_t rtl8367b_getAsicReg(uint32_t reg, uint32_t *pValue);
-ret_t rtl8367b_setAsicPortExtMode(uint32_t id, uint32_t mode);
-ret_t rtl8367b_getAsicPortForceLinkExt(uint32_t id, rtl8367b_port_ability_t *pPortAbility);
-ret_t rtl8367b_setAsicPortForceLinkExt(uint32_t id, rtl8367b_port_ability_t *pPortAbility);
-ret_t rtl8367b_setAsicPHYReg(uint32_t phyNo, uint32_t phyAddr, uint32_t regData);
-ret_t rtl8367b_getAsicPHYReg(uint32_t phyNo, uint32_t phyAddr, uint32_t* pRegData);
-void mdio_base_set(unsigned int mdio_base);
-
-#endif /* __RTL8367B_INIT_H__ */
diff --git a/board/ruby/rtl8367b/rtl8367b_smi.c b/board/ruby/rtl8367b/rtl8367b_smi.c
deleted file mode 100644
index 3ca2708..0000000
--- a/board/ruby/rtl8367b/rtl8367b_smi.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
-* Copyright c Realtek Semiconductor Corporation, 2006
-* All rights reserved.
-*
-* Program : Control smi connected RTL8366
-* Abstract :
-* Author : Yu-Mei Pan (ympan@realtek.com.cn)
-* $Id: smi.c 28599 2012-05-07 01:41:37Z kobe_wu $
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include "rtl8367b_smi.h"
-#include "rtl8367b_init.h"
-#include <asm/arch/platform.h>
-#include <asm/arch/arasan_emac_ahb.h>
-
-#define MDC_MDIO_DUMMY_ID 0
-#define MDC_MDIO_CTRL0_REG 31
-#define MDC_MDIO_START_REG 29
-#define MDC_MDIO_CTRL1_REG 21
-#define MDC_MDIO_ADDRESS_REG 23
-#define MDC_MDIO_DATA_WRITE_REG 24
-#define MDC_MDIO_DATA_READ_REG 25
-#define MDC_MDIO_PREAMBLE_LEN 32
-
-#define MDC_MDIO_START_OP 0xFFFF
-#define MDC_MDIO_ADDR_OP 0x000E
-#define MDC_MDIO_READ_OP 0x0001
-#define MDC_MDIO_WRITE_OP 0x0003
-
-#define MDC_MDIO_READ(len, phyId, regId, pData) mdio_read(len, phyId, regId, pData)
-#define MDC_MDIO_WRITE(len, phyId, regId, data) mdio_write(len, phyId, regId, data)
-
-static unsigned long cur_mdio_base = RUBY_ERROR_ADDR;
-
-/* Function Name:
- * mdio_read
- * Description:
- * MDIO read request
- * Input:
- * len - Data length read
- * phyId - Physical PHY (0-7)
- * regId - Physical register to write data
- * data - Data read from device
- * Return:
- * void
- * Note:
- * None
- */
-static void mdio_read(unsigned int len, unsigned int phyId, unsigned int regId, unsigned int *pData)
-{
- mdio_postrd_raw(cur_mdio_base, phyId, regId);
- *pData = mdio_rdval_raw(cur_mdio_base, 1);
- if (MDIO_DEBUG) {
- printf("%s: phy %u reg %u data %u\n",
- __FUNCTION__, phyId, regId, *pData);
- }
-}
-
-/* Function Name:
- * mdio_write
- * Description:
- * MDIO write request
- * Input:
- * len - Data length
- * phyId - Physical PHY (0-7)
- * regId - Physical register to write data
- * data - Data to be written
- * Return:
- * void
- * Note:
- * None
- */
-static void mdio_write(unsigned int len, unsigned int phyId, unsigned int regId, unsigned int data)
-{
- mdio_postwr_raw(cur_mdio_base, phyId, regId, data);
- if (MDIO_DEBUG) {
- printf("%s: phy %u reg %u data %u\n",
- __FUNCTION__, phyId, regId, data);
- }
-}
-
-/* Function Name:
- * mdio_base_set
- * Description:
- * Store mdio base address
- * Input:
- * mdio_base - mdio base address
- * Return:
- * void
- * Note:
- * None
- */
-void smi_mdio_base_set(unsigned long mdio_base)
-{
- cur_mdio_base = mdio_base;
-}
-
-/* Function Name:
- * smi_reset
- * Description:
- * SMI reset control
- * Input:
- * port - Physical port number (0-7)
- * pinRST - RST pin
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_FAILED - SMI access error
- * Note:
- * None
- */
-uint32_t smi_reset(uint32_t port, uint32_t pinRST)
-{
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * smi_init
- * Description:
- * SMI init control
- * Input:
- * port - Physical port number (0-7)
- * pinSCK - SCK pin
- * pinSDA - SDA pin
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_FAILED - SMI access error
- * Note:
- * None
- */
-uint32_t smi_init(uint32_t port, uint32_t pinSCK, uint32_t pinSDA)
-{
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * smi_read
- * Description:
- * SMI read control
- * Input:
- * mAddrs - SMI 32-bit address
- * rData - Data read from device
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_FAILED - SMI access error
- * Note:
- * None
- */
-uint32_t smi_read(uint32_t mAddrs, uint32_t *rData)
-{
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Write address control code to register 31 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);
-
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Write address to register 23 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_ADDRESS_REG, mAddrs);
-
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Write read control code to register 21 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP);
-
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Read data from register 25 */
- MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_READ_REG, rData);
-
- return RT_ERR_OK;
-}
-
-/* Function Name:
- * smi_write
- * Description:
- * SMI write control
- * Input:
- * mAddrs - SMI 32-bit address
- * rData - Data to be written
- * Return:
- * RT_ERR_OK - Success
- * RT_ERR_FAILED - SMI access error
- * Note:
- * None
- */
-uint32_t smi_write(uint32_t mAddrs, uint32_t rData)
-{
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Write address control code to register 31 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);
-
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Write address to register 23 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_ADDRESS_REG, mAddrs);
-
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Write data to register 24 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_DATA_WRITE_REG, rData);
-
- /* Write Start command to register 29 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
-
- /* Write data control code to register 21 */
- MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_DUMMY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP);
-
- return RT_ERR_OK;
-}
-
-int do_smi_read(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- uint32_t addr;
- uint32_t data;
-
- addr = simple_strtoul (argv[1], NULL, 16);
- smi_read(addr, &data);
- printf("smi_read: 0x%x = 0x%x\n", addr, data);
-
- return 0;
-}
-
-int do_smi_sweep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int i;
- uint32_t addr;
- uint32_t data;
-
- for (i = 0; i < SMI_SWEEP_MAX; i++) {
- if (ctrlc()) {
- break;
- }
- addr = i;
- smi_read(addr, &data);
- if ((data) && (data != 0xffff)) {
- printf("smi_sweep: 0x%x = 0x%x\n", addr, data);
- }
- }
-
- return 0;
-}
-
-int do_smi_write(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- uint32_t addr;
- uint32_t data;
-
- addr = simple_strtoul (argv[1], NULL, 16);
- data = simple_strtoul (argv[2], NULL, 16);
- printf("smi_write: 0x%x <- 0x%x\n", addr, data);
- smi_write(addr, data);
-
- return 0;
-}
-
-U_BOOT_CMD(smi_read, 6, 1, do_smi_read, "RTL8363EB smi read <reg>", "");
-U_BOOT_CMD(smi_write, 6, 2, do_smi_write, "RTL8363EB smi write <reg> <val>", "");
-U_BOOT_CMD(smi_sweep, 6, 1, do_smi_sweep, "RTL8363EB smi sweep", "");
-
diff --git a/board/ruby/rtl8367b/rtl8367b_smi.h b/board/ruby/rtl8367b/rtl8367b_smi.h
deleted file mode 100644
index 9b1e359..0000000
--- a/board/ruby/rtl8367b/rtl8367b_smi.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __RTL8367B_SMI_H__
-#define __RTL8367B_SMI_H__
-
-#include "rtl8367b_init.h"
-
-uint32_t smi_reset(uint32_t port, uint32_t pinRST);
-uint32_t smi_init(uint32_t port, uint32_t pinSCK, uint32_t pinSDA);
-uint32_t smi_read(uint32_t mAddrs, uint32_t *rData);
-uint32_t smi_write(uint32_t mAddrs, uint32_t rData);
-void smi_mdio_base_set(unsigned long addr);
-
-#endif /* __RTL8367B_SMI_H__ */
diff --git a/board/ruby/spi_flash.c b/board/ruby/spi_flash.c
index 618e346..3434892 100644
--- a/board/ruby/spi_flash.c
+++ b/board/ruby/spi_flash.c
@@ -32,6 +32,9 @@
#define SPI_PAGE_SIZE 256
#define ENV_BASE_SIZE (CONFIG_ENV_BASE_SIZE - ENV_HEADER_SIZE)
+#if defined(FLASH_SUPPORT_256KB)
+#define SPI_FLASH_256KB_SIZE (256 * 1024)
+#endif
#define SPI_FLASH_UBOOT_ADDR 0
@@ -163,6 +166,11 @@
return 0;
}
+#if defined (FLASH_SUPPORT_256KB)
+ if (flash_size == SPI_FLASH_256KB_SIZE)
+ return SPI_FLASH_MINI_UBOOT_SIZE;
+#endif
+
/*
* Bit of a hack. We don't have partition tables in uboot;
* Use flash size as a heuristic to determine how big
@@ -1075,13 +1083,20 @@
if (gd->env_valid == 0) {
env_addr = spi_flash_env_addr(0);
+
+ /* No ENV & CAL backup for mini-uboot */
+ if (spi_flash_uboot_size() == SPI_FLASH_FULL_UBOOT_SIZE) {
#if defined(FLASH_SUPPORT_256KB)
- env_addr_backup = spi_flash_env_addr(2);
- env_end = spi_flash_env_addr(4);
+ env_addr_backup = spi_flash_env_addr(2);
+ env_end = spi_flash_env_addr(4);
#else
- env_addr_backup = spi_flash_env_addr(1);
- env_end = spi_flash_env_addr(2);
+ env_addr_backup = spi_flash_env_addr(1);
+ env_end = spi_flash_env_addr(2);
#endif
+ } else {
+ env_addr_backup = 0;
+ env_end = spi_flash_env_addr(1);
+ }
if (env_verify(env_addr) == 0) {
printf("Valid CRC found in flash restoring env...\n");
diff --git a/board/ruby/start.S b/board/ruby/start.S
index 366e457..6974204 100644
--- a/board/ruby/start.S
+++ b/board/ruby/start.S
@@ -32,6 +32,7 @@
#include <asm/arcregs.h>
#include <asm/arch/platform.h>
#include <ruby_version.h>
+#include <topaz_platform.h>
#include <topaz_config.h>
#include <uboot_header.h>
#include "timestamp_autogenerated.h"
@@ -147,9 +148,9 @@
M_REMOVE_FROM_RESET
M_GOTO_IF_EXEC_REMAPPED_SRAM run_c
-#ifdef FLIPBIT
+#if defined(RUBY_SYS_CTL_MMAP_REGVAL)
M_IF_BOOT_FROM_FLASH
- bne ruby_flip_mmap /* if we are running not from flash call the flip routine to
+ bne topaz_unified_mmap /* if we are running not from flash call the flip routine to
* flip the bit in place; will return to ruby_boot label */
#endif
j ruby_boot - TEXT_BASE + RUBY_SPI_FLASH_ADDR /* jump to physical spi address */
@@ -158,7 +159,8 @@
.globl ruby_boot
M_IF_BOOT_FROM_FLASH
bne run_c
-#ifdef FLIPBIT
+
+#ifdef RUBY_SYS_CTL_MMAP_REGVAL
M_REMAP_MEM
#endif
M_COPY_UBOOT TEXT_BASE, RUBY_SPI_FLASH_ADDR
@@ -173,4 +175,7 @@
#endif
M_GOTO_C_CODE
+#if defined(RUBY_SYS_CTL_MMAP_REGVAL) && (defined(PIGGY_BUILD) || !defined(RUBY_MINI))
+#include <topaz_mmap.S>
+#endif
/*********************************************************************************************/
diff --git a/board/ruby/start.inl b/board/ruby/start.inl
index fe18641..c1c6cad 100644
--- a/board/ruby/start.inl
+++ b/board/ruby/start.inl
@@ -27,16 +27,8 @@
#include <config.h>
#include <asm/arch/platform.h>
+#include <topaz_platform.h>
-#if TOPAZ_MMAP_ALIAS
- #define FLIPBIT TOPAZ_SYS_CTL_UNIFIED_MAP | TOPAZ_SYS_CTL_ALIAS_MAP
-#elif TOPAZ_MMAP_UNIFIED
- #define FLIPBIT TOPAZ_SYS_CTL_UNIFIED_MAP
-#elif RUBY_MMAP_FLIP
- #define FLIPBIT RUBY_SYS_CTL_LINUX_MAP(0x1)
-#else
- #undef FLIPBIT
-#endif
#define U_BOOT_TYPE_LARGE "0"
#define U_BOOT_TYPE_MINI "1"
@@ -98,9 +90,9 @@
.macro M_REMAP_MEM
/* flip memmap and remap ddr */
mov r1, RUBY_SYS_CTL_BASE_ADDR_NOMAP
- mov r2, FLIPBIT | RUBY_SYS_CTL_REMAP(0x3)
+ mov r2, RUBY_SYS_CTL_MMAP_REGVAL | RUBY_SYS_CTL_REMAP(0x3)
st.di r2, [r1, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
- mov r2, FLIPBIT
+ mov r2, RUBY_SYS_CTL_MMAP_REGVAL
st.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR]
ld.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR] /* read back to clear pipeline */
sync /* wait for pipeline to flush */
diff --git a/board/ruby/u-boot.lds.S b/board/ruby/u-boot.lds.S
index 44308b6..e0b2e4a 100644
--- a/board/ruby/u-boot.lds.S
+++ b/board/ruby/u-boot.lds.S
@@ -10,7 +10,7 @@
ENTRY(_start)
-#if TOPAZ_MMAP_UNIFIED
+#if TOPAZ_MMAP_UNIFIED && TOPAZ_UBOOT_UNIFIED_MAP
#define SRAM_BEGIN RUBY_SRAM_BEGIN
#define SRAM_UC_BEGIN RUBY_SRAM_BEGIN
#else
diff --git a/board/ruby_mini/ruby_mini.c b/board/ruby_mini/ruby_mini.c
index a5b4215..00f4c9c 100644
--- a/board/ruby_mini/ruby_mini.c
+++ b/board/ruby_mini/ruby_mini.c
@@ -37,7 +37,6 @@
#include "ruby_board_db.h"
#include "ruby_version.h"
#include "ruby_mini_common.h"
-#include "rtl8367b/rtl8367b_init.h"
void *ar8236_init(unsigned long baseAddr, unsigned long phy_addr)
{
@@ -49,16 +48,6 @@
return NULL;
}
-ret_t rtl8367b_poll_linkup(struct emac_private *priv)
-{
- return 0;
-}
-
-ret_t rtl8367b_init(struct emac_private *priv, uint32_t emac_cfg)
-{
- return 0;
-}
-
void do_bootm(void){}
static void get_stage2(void)
diff --git a/board/ruby_mini/ruby_mini_common.c b/board/ruby_mini/ruby_mini_common.c
index c105fe4..bf1e3bf 100644
--- a/board/ruby_mini/ruby_mini_common.c
+++ b/board/ruby_mini/ruby_mini_common.c
@@ -128,6 +128,9 @@
"ipaddr=" MKSTR(CONFIG_IPADDR) "\0"
"serverip=" MKSTR(CONFIG_SERVERIP) "\0"
"bootfile=" MKSTR(CONFIG_BOOTFILE) "\0"
+#if TOPAZ_QFDR_VLAN > 1
+ "vlan=" MKSTR(TOPAZ_QFDR_VLAN) "\0"
+#endif
"\0"
};
@@ -202,6 +205,10 @@
extern void board_spi_flash_init(void);
board_spi_flash_init();
#endif
+
+#if TOPAZ_QFDR_VLAN > 1
+ printf("qfdr manage vlan %u\n",TOPAZ_QFDR_VLAN);
+#endif
return 0;
}
diff --git a/piggy.mk b/piggy.mk
index 090e18c..3c368f6 100644
--- a/piggy.mk
+++ b/piggy.mk
@@ -97,7 +97,6 @@
endif
OBJS = board/ruby/start.o \
- board/ruby/flip.o \
cpu/arc/cache.o \
${DEBUG_OBJS} \
board/ruby_mini/ruby_piggy.o \
diff --git a/quantenna/common/common_mem.h b/quantenna/common/common_mem.h
index 61b106e..7b785c4 100644
--- a/quantenna/common/common_mem.h
+++ b/quantenna/common/common_mem.h
@@ -35,7 +35,8 @@
/* Platform memory */
/* SRAM */
#define RUBY_SRAM_UNIFIED_BEGIN 0x98000000
-#define RUBY_SRAM_UNIFIED_NOCACHE_BEGIN 0xf8000000
+#define RUBY_SRAM_UNIFIED_NOCACHE_BEGIN 0x60000000
+#define RUBY_SRAM_ALIAS_NOCACHE_BEGIN 0xf8000000
#define RUBY_SRAM_FLIP_BEGIN 0x88000000
#define RUBY_SRAM_FLIP_NOCACHE_BEGIN 0x60000000
#define RUBY_SRAM_NOFLIP_BEGIN 0x80000000
@@ -47,15 +48,27 @@
/* DDR */
#define RUBY_DRAM_UNIFIED_BEGIN 0x80000000
-#define RUBY_DRAM_UNIFIED_NOCACHE_BEGIN 0xd0000000
+#define RUBY_DRAM_UNIFIED_NOCACHE_BEGIN 0x40000000
+#define RUBY_DRAM_ALIAS_NOCACHE_BEGIN 0xd0000000
#define RUBY_DRAM_FLIP_BEGIN 0x80000000
#define RUBY_DRAM_FLIP_NOCACHE_BEGIN 0x40000000
#define RUBY_DRAM_NOFLIP_BEGIN 0x0
#define RUBY_DRAM_NOFLIP_NOCACHE_BEGIN 0x40000000
+#if TOPAZ_MMAP_UNIFIED && TOPAZ_SUPPORT_256MB_DDR
+#define RUBY_MAX_DRAM_SIZE DDR_256MB
+#else
#define RUBY_MAX_DRAM_SIZE DDR_128MB
+#endif
#define RUBY_MIN_DRAM_SIZE DDR_64MB
-#if TOPAZ_MMAP_UNIFIED
+#if TOPAZ_MMAP_UNIFIED && TOPAZ_MMAP_ALIAS
+ #define RUBY_SRAM_BEGIN RUBY_SRAM_UNIFIED_BEGIN
+ #define RUBY_SRAM_BUS_BEGIN RUBY_SRAM_UNIFIED_BEGIN
+ #define RUBY_SRAM_NOCACHE_BEGIN RUBY_SRAM_ALIAS_NOCACHE_BEGIN
+ #define RUBY_DRAM_BEGIN RUBY_DRAM_UNIFIED_BEGIN
+ #define RUBY_DRAM_BUS_BEGIN RUBY_DRAM_UNIFIED_BEGIN
+ #define RUBY_DRAM_NOCACHE_BEGIN RUBY_DRAM_ALIAS_NOCACHE_BEGIN
+#elif TOPAZ_MMAP_UNIFIED
#define RUBY_SRAM_BEGIN RUBY_SRAM_UNIFIED_BEGIN
#define RUBY_SRAM_BUS_BEGIN RUBY_SRAM_UNIFIED_BEGIN
#define RUBY_SRAM_NOCACHE_BEGIN RUBY_SRAM_UNIFIED_NOCACHE_BEGIN
diff --git a/quantenna/common/current_platform.h b/quantenna/common/current_platform.h
index bcd3ab4..13899f3 100644
--- a/quantenna/common/current_platform.h
+++ b/quantenna/common/current_platform.h
@@ -5,6 +5,8 @@
#define PLATFORM_WMAC_MODE ap
#undef PLATFORM_DEFAULT_BOARD_ID
#define ARC_HW_REV_NEEDS_TLBMISS_FIX
+#define TOPAZ_SUPPORT_UMM 0
+#define TOPAZ_SUPPORT_256MB_DDR 0
#define FLASH_SUPPORT_64KB
#define WPA_TKIP_SUPPORT 0
#define SIGMA_TESTBED_SUPPORT 0
diff --git a/quantenna/common/ruby_config.h b/quantenna/common/ruby_config.h
index c50e98a..fc26ec6 100644
--- a/quantenna/common/ruby_config.h
+++ b/quantenna/common/ruby_config.h
@@ -110,6 +110,7 @@
#define EMAC_BONDED (BIT(20))
#define EMAC_PHY_RTL8365MB (BIT(21))
#define EMAC_PHY_RTL8211DS (BIT(22))
+#define EMAC_PHY_RTL8367RB (BIT(23))
#define EMAC_PHY_CUSTOM (BIT(31))
#define EMAC_MV88E6071 (EMAC_IN_USE | EMAC_PHY_MII | EMAC_PHY_NOT_IN_USE | \
diff --git a/quantenna/common/ruby_platform.h b/quantenna/common/ruby_platform.h
index 9708d63..4cc2ebb 100644
--- a/quantenna/common/ruby_platform.h
+++ b/quantenna/common/ruby_platform.h
@@ -477,6 +477,19 @@
#define RUBY_SPI_ADDRESS_MODE_4B 0x85
#define RUBY_SPI_BOUNDARY_4B 0x1000000
+#define RUBY_SPI_READ_LOCK (RUBY_SPI_BASE_ADDR + 0x2D00)
+#define RUBY_SPI_WRITE_LOCK (RUBY_SPI_BASE_ADDR + 0x2C00)
+#define RUBY_SPI_READ_CONFIG (RUBY_SPI_BASE_ADDR + 0x1500)
+#define RUBY_SPI_READ_SPB (RUBY_SPI_BASE_ADDR + 0xE200)
+#define RUBY_SPI_WRITE_SPB (RUBY_SPI_BASE_ADDR + 0xE300)
+#define RUBY_SPI_ERASE_SPB (RUBY_SPI_BASE_ADDR + 0xE400)
+
+#define RUBY_SPI_WRITE_PASWORD (RUBY_SPI_BASE_ADDR + 0x2800)
+#define RUBY_SPI_READ_PASSWORD (RUBY_SPI_BASE_ADDR + 0x2700)
+#define RUBY_SPI_UNLOCK_PASSWORD (RUBY_SPI_BASE_ADDR + 0x2900)
+#define RUBY_SPI_WRITE_SPBLOCK (RUBY_SPI_BASE_ADDR + 0xA600)
+#define RUBY_SPI_READ_SPBLOCK (RUBY_SPI_BASE_ADDR + 0xA700)
+
/*
* UBOOT_VERSION_LOCATION:
* This is hardwired in u-boot's start.S; the first instruction generates a
diff --git a/quantenna/common/ruby_spi_api.h b/quantenna/common/ruby_spi_api.h
index 1612a0d..ebd57f2 100644
--- a/quantenna/common/ruby_spi_api.h
+++ b/quantenna/common/ruby_spi_api.h
@@ -80,6 +80,19 @@
#define SPI_PROTECT_MODE_ENABLE "enable"
#define SPI_PROTECT_MODE_FLAG_DISABLE 1
#define SPI_PROTECT_MODE_FLAG_ENABLE 0
+
+#define RUBY_SPI_PASS_CMD_MASK(X) (((X) & 0xfffffff0) | 0x1)
+#define RUBY_SPI_PASS_ONE_MASK(X) (((X) & 0xfffffff0) | 0x2)
+#define RUBY_SPI_PASS_TWO_MASK(X) (((X) & 0xfffffff0) | 0x3)
+#define RUBY_SPI_PASS_FOUR_MASK(X) (((X) & 0xfffffff0) | 0x5)
+#define RUBY_SPI_PASS_EIGHT_MASK(X) (((X) & 0xfffffff0) | 0x9)
+#define RUBY_SPI_PASS_FIVE_MASK(X) (((X) & 0xfffffff0) | 0x6)
+#define RUBY_SPI_PASS_ONE_ADDR_MASK(X) (((X) & 0xfffffff0) | 0x6)
+#define RUBY_SPI_CMD_MASK(X) (((X) & 0xff) << 8)
+#define RUBY_SPI_READ_DATA_MASK (0xff)
+#define SPI_LOCK_SPM (BIT(1))
+#define SPI_LOCK_PPM (BIT(2))
+
/*
*
* Ruby uses 3 msb bytes to form addresses.
diff --git a/quantenna/common/ruby_spi_flash_data.h b/quantenna/common/ruby_spi_flash_data.h
index 3006f73..ba73b2f 100644
--- a/quantenna/common/ruby_spi_flash_data.h
+++ b/quantenna/common/ruby_spi_flash_data.h
@@ -85,6 +85,7 @@
/* Micron */
{ "N25Q032", 0x20ba16, 64 * 1024, 64, 0, FREQ_UNKNOWN, MICRON },
+ { "N25Q256", 0x20ba19, 64 * 1024, 512, 0, FREQ_MHZ(80), MICRON },
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
{ "sst25vf040b", 0xbf258d, 64 * 1024, 8, 0, FREQ_UNKNOWN, SST },
@@ -112,7 +113,7 @@
/* Winbond -- w25x "blocks" are 64K, except w25q128 is 4K */
{ "w25x05", 0xef3010, 4 * 1024, 16, SECTOR_ERASE_OP20, FREQ_MHZ(104), WINBOND },
{ "w25x10", 0xef3011, 64 * 1024, 2, 0, FREQ_UNKNOWN, WINBOND },
- { "w25x20", 0xef3012, 64 * 1024, 4, 0, FREQ_UNKNOWN, WINBOND },
+ { "w25x20", 0xef3012, 4 * 1024, 64, SECTOR_ERASE_OP20, FREQ_UNKNOWN, WINBOND },
{ "w25x40", 0xef3013, 64 * 1024, 8, 0, FREQ_UNKNOWN, WINBOND },
{ "w25x80", 0xef3014, 64 * 1024, 16, 0, FREQ_UNKNOWN, WINBOND },
{ "w25x16", 0xef3015, 64 * 1024, 32, 0, FREQ_UNKNOWN, WINBOND },
diff --git a/quantenna/common/ruby_version.h b/quantenna/common/ruby_version.h
index 7664b11..342d60e 100644
--- a/quantenna/common/ruby_version.h
+++ b/quantenna/common/ruby_version.h
@@ -12,6 +12,6 @@
// Defines
////////////////////////////////////////////////////////////////////////////
-#define RUBY_UBOOT_VERSION "v37.4.0.28"
+#define RUBY_UBOOT_VERSION "v37.4.0.29"
#endif // __RUBY_RELEASE_H__
diff --git a/quantenna/common/topaz_config.h b/quantenna/common/topaz_config.h
index 5be0113..a71a123 100644
--- a/quantenna/common/topaz_config.h
+++ b/quantenna/common/topaz_config.h
@@ -37,14 +37,40 @@
/*
* Control registers move depending on unified + alias bit
*/
-
+#if TOPAZ_SUPPORT_UMM
+#define TOPAZ_MMAP_UNIFIED 1
+#else
#define TOPAZ_MMAP_UNIFIED 0
+#endif
+
#define TOPAZ_MMAP_ALIAS 0
#define TOPAZ_RX_ACCELERATE 1
/* If MU-MIMO done in HDP or SDP */
#define QTN_HDP_MU 1
+#if TOPAZ_MMAP_UNIFIED
+ #define RUBY_MMAP_FLIP 0
+ #define TOPAZ_UBOOT_UNIFIED_MAP 1
+#else
+ #if !(defined(MUC_BUILD) || defined(DSP_BUILD) || defined(AUC_BUILD))
+ #define RUBY_MMAP_FLIP 1
+ #else
+ #define RUBY_MMAP_FLIP 0
+ #endif
+ #define TOPAZ_UBOOT_UNIFIED_MAP 0
+#endif
+
+#if TOPAZ_MMAP_ALIAS && (defined(__linux__) || TOPAZ_UBOOT_UNIFIED_MAP)
+ #define RUBY_SYS_CTL_MMAP_REGVAL (TOPAZ_SYS_CTL_UNIFIED_MAP | TOPAZ_SYS_CTL_ALIAS_MAP)
+#elif TOPAZ_MMAP_UNIFIED && (defined(__linux__) || TOPAZ_UBOOT_UNIFIED_MAP)
+ #define RUBY_SYS_CTL_MMAP_REGVAL TOPAZ_SYS_CTL_UNIFIED_MAP
+#elif RUBY_MMAP_FLIP || defined(TOPAZ_PLATFORM)
+ #define RUBY_SYS_CTL_MMAP_REGVAL RUBY_SYS_CTL_LINUX_MAP(0x1)
+#else
+ #undef RUBY_SYS_CTL_MMAP_REGVAL
+#endif
+
#if QTN_HDP_MU
#define QTN_HDP_MU_FCS_WORKROUND 1
#else
diff --git a/board/ruby/flip.S b/quantenna/common/topaz_mmap.S
similarity index 62%
rename from board/ruby/flip.S
rename to quantenna/common/topaz_mmap.S
index 3b160aa..12456bc 100644
--- a/board/ruby/flip.S
+++ b/quantenna/common/topaz_mmap.S
@@ -20,17 +20,17 @@
* MA 02111-1307 USA
*/
-#include <config.h>
-#include <asm/arcregs.h>
-#include <asm/arch/platform.h>
-#include "start.inl"
+#if defined(__linux__) && defined (__KERNEL__)
+#if defined (DC_CTRL_FLUSH_STATUS)
+ #define ARC_DC_FLUSH_STATUS_BIT DC_CTRL_FLUSH_STATUS
+#elif defined (BIT_DC_CTRL_FLUSH_STATUS)
+ #define ARC_DC_FLUSH_STATUS_BIT BIT_DC_CTRL_FLUSH_STATUS
+#endif
+#endif
-#if ((RUBY_MMAP_FLIP || TOPAZ_MMAP_UNIFIED)) && \
- (defined(PIGGY_BUILD) || !defined(RUBY_MINI))
-
-ruby_flip_mmap:
- .globl ruby_flip_mmap
+topaz_unified_mmap:
+ .globl topaz_unified_mmap
/* Code must be position-independent! */
/*
@@ -39,17 +39,17 @@
* d-cache are NOT used until flipping is done.
*/
/* Set flush mode for invalidate operation */
- lr r1, [ARC_REG_DC_CTRL]
- bset r1, r1, 0x6
- sr r1, [ARC_REG_DC_CTRL]
+ lr r3, [ARC_REG_DC_CTRL]
+ bset r3, r3, 0x6
+ sr r3, [ARC_REG_DC_CTRL]
/* Start invalidate operation */
- mov r1, 0x1
- sr r1, [ARC_REG_DC_IVDC]
+ mov r3, 0x1
+ sr r3, [ARC_REG_DC_IVDC]
/* Check while cache invalidating will be finished */
dcache_flush_continue:
- lr r1, [ARC_REG_DC_CTRL]
- and r1, r1, ARC_DC_FLUSH_STATUS_BIT
- brne r1, 0x0, dcache_flush_continue
+ lr r3, [ARC_REG_DC_CTRL]
+ and r3, r3, ARC_DC_FLUSH_STATUS_BIT
+ brne r3, 0x0, dcache_flush_continue
/* Prepare flipping.
* After code is finished, memory maps will change as follows:
@@ -60,35 +60,35 @@
* SRAM 0x8000_0000 -> 0x9800_0000
* DRAM 0x0 -> 0x8000_0000
*/
- mov r1, RUBY_SYS_CTL_BASE_ADDR_NOMAP
- mov r2, FLIPBIT | RUBY_SYS_CTL_REMAP(0x3)
- st.di r2, [r1, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
- mov r2, FLIPBIT
+ mov r3, RUBY_SYS_CTL_BASE_ADDR_NOMAP
+ mov r4, RUBY_SYS_CTL_MMAP_REGVAL
+ or r4, r4, RUBY_SYS_CTL_REMAP(0x3)
+ st.di r4, [r3, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
+ mov r4, RUBY_SYS_CTL_MMAP_REGVAL
-.align ARC_ICACHE_LINE_LEN
+.align 32 /*ARC_ICACHE_LINE_LEN*/
/* Do flipping.
* Align to cache line to ensure we don't hit memory during following instructions.
* Code must fit into 1 cache line (32 bytes).
*/
- st.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR]
- ld.di r2, [r1, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR] /* read back to clear pipeline */
+ st.di r4, [r3, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR]
+ ld.di r4, [r3, RUBY_SYS_CTL_CTRL - RUBY_SYS_CTL_BASE_ADDR] /* read back to clear pipeline */
sync
j boot_continue /* jump to absolute addr in sram */
/* Align to cache line so code occupy strictly 1 cache line. */
-.align ARC_ICACHE_LINE_LEN
+.align 32 /* ARC_ICACHE_LINE_LEN */
boot_continue:
/* Finalize flipping. */
- mov r2, 0x0
- st.di r2, [r1, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
+ mov r4, 0x0
+ st.di r4, [r3, RUBY_SYS_CTL_MASK - RUBY_SYS_CTL_BASE_ADDR]
/* Let's discard instruction cache.
*/
- mov r2, 0x1
- sr r2, [ARC_REG_IC_IVIC] /* invalidate i-cache */
- lr r2, [ARC_REG_IC_CTRL] /* read will be not completed until i-cache is invalidated */
+ mov r4, 0x1
+ sr r4, [ARC_REG_IC_IVIC] /* invalidate i-cache */
+ lr r4, [ARC_REG_IC_CTRL] /* read will be not completed until i-cache is invalidated */
/* Done. We are now sitting in different addresses. */
b ruby_boot
-#endif /* RUBY_MMAP_FLIP TOPAZ_MMAP_UNIFIED PIGGY_BUILD RUBY_MINI*/
diff --git a/quantenna/common/topaz_platform.h b/quantenna/common/topaz_platform.h
new file mode 100644
index 0000000..be27da5
--- /dev/null
+++ b/quantenna/common/topaz_platform.h
@@ -0,0 +1,498 @@
+/*
+ * (C) Copyright 2010 Quantenna Communications Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Header file which describes Topaz platform.
+ * Has to be used by both kernel and bootloader.
+ */
+
+#ifndef __TOPAZ_PLATFORM_H
+#define __TOPAZ_PLATFORM_H
+
+#include "ruby_platform.h"
+
+#ifndef MS
+#define MS(_v, _f) (((_v) & _f) >> _f##_S)
+#endif
+#ifndef SM
+#define SM(_v, _f) (((_v) << _f##_S) & _f)
+#endif
+
+/*
+ * The following macro couldn't be defined via SM because of issues with nesting ##
+ * i.e. the following define does not work
+ * do{ where = (where) & (~(bitmask)) | SM(new_value, bitmask); }while(0)
+ */
+#define UPDATE_BITSET(where, bitmask, new_value) \
+ do{ where = ((where) & (~(bitmask))) | (((new_value) << bitmask##_S) & bitmask); }while(0)
+
+/* Extra reset bits */
+#define TOPAZ_SYS_CTL_RESET_AUC (RUBY_BIT(10))
+#define TOPAZ_SYS_CTL_ALIAS_MAP (RUBY_BIT(29))
+#define TOPAZ_SYS_CTL_UNIFIED_MAP (RUBY_BIT(30))
+
+/* Extra system controller bits */
+#define TOPAZ_SYS_CTL_DDRCLK_S 22
+#define TOPAZ_SYS_CTL_DDRCLK (0x7 << TOPAZ_SYS_CTL_DDRCLK_S)
+#define TOPAZ_SYS_CTL_DDRCLK_400MHZ SM(0, TOPAZ_SYS_CTL_DDRCLK)
+#define TOPAZ_SYS_CTL_DDRCLK_320MHZ SM(1, TOPAZ_SYS_CTL_DDRCLK)
+#define TOPAZ_SYS_CTL_DDRCLK_250MHZ SM(2, TOPAZ_SYS_CTL_DDRCLK)
+#define TOPAZ_SYS_CTL_DDRCLK_200MHZ SM(3, TOPAZ_SYS_CTL_DDRCLK)
+#define TOPAZ_SYS_CTL_DDRCLK_160MHZ SM(4, TOPAZ_SYS_CTL_DDRCLK)
+
+/* Extra system controller registers */
+#define TOPAZ_SYS_CTL_M2D_2_INT (RUBY_SYS_CTL_BASE_ADDR + 0x0184)
+#define TOPAZ_SYS_CTL_M2D_2_INT_MASK (RUBY_SYS_CTL_BASE_ADDR + 0x0188)
+#define TOPAZ_SYS_CTL_M2D_3_INT (RUBY_SYS_CTL_BASE_ADDR + 0x018C)
+#define TOPAZ_SYS_CTL_M2D_3_INT_MASK (RUBY_SYS_CTL_BASE_ADDR + 0x0190)
+
+/* Temperature control registers */
+#define TOPAZ_SYS_CTL_TEMPSENS_CTL (RUBY_SYS_CTL_BASE_ADDR + 0x0108)
+#define TOPAZ_SYS_CTL_TEMPSENS_CTL_START_CONV 0x00000001
+#define TOPAZ_SYS_CTL_TEMPSENS_CTL_SHUTDWN 0x00000002
+
+#define TOPAZ_SYS_CTL_TEMP_SENS_TEST_CTL (RUBY_SYS_CTL_BASE_ADDR + 0x010C)
+
+#define TOPAZ_SYS_CTL_TEMP_SENS_DATA (RUBY_SYS_CTL_BASE_ADDR + 0x0110)
+#define TOPAZ_SYS_CTL_TEMP_SENS_DATA_TEMP 0x00000FFF
+#define TOPAZ_SYS_CTL_TEMP_SENS_DATA_END_CONV 0x00001000
+#define TOPAZ_SYS_CTL_TEMP_SENS_DATA_END_CONV_S 11
+
+/* AuC SoC interrupt controller registers */
+#define TOPAZ_AUC_INT_MASK (RUBY_SYS_CTL_BASE_ADDR + 0x0174)
+#define TOPAZ_AUC_IPC_INT (RUBY_SYS_CTL_BASE_ADDR + 0x0178)
+#define TOPAZ_AUC_IPC_INT_MASK(val) ((val & 0xFFFF) << 16)
+#define TOPAZ_AUC_INT_STATUS (RUBY_SYS_CTL_BASE_ADDR + 0x00D0)
+
+/* Linux Host interrupt controller registers */
+#define TOPAZ_LH_IPC3_INT (RUBY_SYS_CTL_BASE_ADDR + 0x14C)
+#define TOPAZ_LH_IPC3_INT_MASK (RUBY_SYS_CTL_BASE_ADDR + 0x150)
+#define TOPAZ_IPC4_INT(base) ((base) + 0x13C)
+#define TOPAZ_IPC4_INT_MASK(base) ((base) + 0x140)
+#define TOPAZ_LH_IPC4_INT (TOPAZ_IPC4_INT(RUBY_SYS_CTL_BASE_ADDR))
+#define TOPAZ_LH_IPC4_INT_MASK (TOPAZ_IPC4_INT_MASK(RUBY_SYS_CTL_BASE_ADDR))
+
+/* Multi-processor hardware semahpore */
+#define TOPAZ_MPROC_SEMA (RUBY_SYS_CTL_BASE_ADDR + 0x0170)
+
+/* MuC SoC Interrupt controller registers */
+#define TOPAZ_SYS_CTL_A2M_INT (RUBY_SYS_CTL_BASE_ADDR + 0x0144)
+#define TOPAZ_SYS_CTL_A2M_INT_MASK (RUBY_SYS_CTL_BASE_ADDR + 0x0148)
+
+/* PCIE SoC Interrupt controller registers */
+#define TOPAZ_SYS_CTL_PCIE_INT_STATUS (RUBY_SYS_CTL_BASE_ADDR + 0x017c)
+#define TOPAZ_SYS_CTL_TQE_INT_STATS_BIT (RUBY_BIT(10))
+
+#define TOPAZ_SWITCH_BASE_ADDR 0xE1000000
+#define TOPAZ_SWITCH_OUT_NODE_BITS 7 /* Up to 128 output nodes */
+#define TOPAZ_SWITCH_OUT_NODE_MAX (1 << TOPAZ_SWITCH_OUT_NODE_BITS)
+#define TOPAZ_SWITCH_OUT_NODE_MASK ((1 << TOPAZ_SWITCH_OUT_NODE_BITS) - 1)
+#define TOPAZ_SWITCH_OUT_PORT_BITS 4 /* Up to 16 output ports. 8 are used */
+#define TOPAZ_SWITCH_OUT_PORT_MAX (1 << TOPAZ_SWITCH_OUT_PORT_BITS)
+#define TOPAZ_SWITCH_OUT_PORT_MASK ((1 << TOPAZ_SWITCH_OUT_PORT_BITS) - 1)
+
+/* TQE */
+#define TOPAZ_TQE_BASE_ADDR (TOPAZ_SWITCH_BASE_ADDR + 0x30000)
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL (TOPAZ_TQE_BASE_ADDR + 0x0000)
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL_VAL 0x000000FF
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL_VAL_S 0
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL_SHIFT 24 /* reg bits [7:0] become emac ctrl [31:24] */
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL_MCAST_APPEND_CNTR_EN_S 16
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL_MCAST_APPEND_CNTR_EN 0x00010000
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL_PRI_MODE 0x0F000000
+#define TOPAZ_TQE_EMAC_TDES_1_CNTL_PRI_MODE_S 24
+#define TOPAZ_TQE_MISC (TOPAZ_TQE_BASE_ADDR + 0x0004)
+#define TOPAZ_TQE_MISC_CLR_DONE_DLY_CYCLE_NUM 0x000003FF /* q_avail_clr_done delay cycles */
+#define TOPAZ_TQE_MISC_CLR_DONE_DLY_CYCLE_NUM_S 0
+#define TOPAZ_TQE_MISC_RFLCT_OUT_PORT 0x000F0000 /* dest port for reflected pkts */
+#define TOPAZ_TQE_MISC_RFLCT_OUT_PORT_S 16
+#define TOPAZ_TQE_MISC_RFLCT_OUT_PORT_ENABLE 0x00100000 /* redirect emac0<->emac0 or emac1<->emac1 reflected pkts */
+#define TOPAZ_TQE_MISC_RFLCT_OUT_PORT_ENABLE_S 20
+#define TOPAZ_TQE_MISC_RFLCT_2_OUT_PORT_ENABLE 0x00200000 /* redirect emac0<->emac0/emac1 or emac1<->emac0/emac1 reflected pkts */
+#define TOPAZ_TQE_MISC_RFLCT_2_OUT_PORT_ENABLE_S 21
+#define TOPAZ_TQE_MISC_CLR_DONE_DLY_ENABLE 0x80000000 /* enable q_avail_clr_done delay */
+#define TOPAZ_TQE_MISC_CLR_DONE_DLY_ENABLE_S 31
+#define TOPAZ_TQE_WMAC_Q_STATUS_PTR (TOPAZ_TQE_BASE_ADDR + 0x0008)
+#define TOPAZ_TQE_CPU_SEM (TOPAZ_TQE_BASE_ADDR + 0x000c)
+#define TOPAZ_TQE_OUTPORT_EMAC0_CNT (TOPAZ_TQE_BASE_ADDR + 0x0010)
+#define TOPAZ_TQE_OUTPORT_EMAC1_CNT (TOPAZ_TQE_BASE_ADDR + 0x0014)
+#define TOPAZ_TQE_OUTPORT_WMAC_CNT (TOPAZ_TQE_BASE_ADDR + 0x0018)
+#define TOPAZ_TQE_OUTPORT_LHOST_CNT (TOPAZ_TQE_BASE_ADDR + 0x001c)
+#define TOPAZ_TQE_OUTPORT_MUC_CNT (TOPAZ_TQE_BASE_ADDR + 0x0020)
+#define TOPAZ_TQE_OUTPORT_DSP_CNT (TOPAZ_TQE_BASE_ADDR + 0x0024)
+#define TOPAZ_TQE_OUTPORT_AUC_CNT (TOPAZ_TQE_BASE_ADDR + 0x0028)
+#define TOPAZ_TQE_OUTPORT_PCIE_CNT (TOPAZ_TQE_BASE_ADDR + 0x002c)
+#define TOPAZ_TQE_Q_AVAIL_CLR_CNTL (TOPAZ_TQE_BASE_ADDR + 0x0030)
+#define TOPAZ_TQE_Q_AVAIL_CLR_CNTL_TID 0xF
+#define TOPAZ_TQE_Q_AVAIL_CLR_CNTL_TID_S 0
+#define TOPAZ_TQE_Q_AVAIL_CLR_CNTL_NODE 0x7F00
+#define TOPAZ_TQE_Q_AVAIL_CLR_CNTL_NODE_S 8
+#define TOPAZ_TQE_Q_AVAIL_CLR_CNTL_CLEAR RUBY_BIT(30)
+#define TOPAZ_TQE_Q_AVAIL_CLR_CNTL_CLEAR_DONE RUBY_BIT(31)
+#define TOPAZ_TQE_DROP_CNT (TOPAZ_TQE_BASE_ADDR + 0x0034)
+#define TOPAZ_TQE_DROP_EMAC0_CNT (TOPAZ_TQE_BASE_ADDR + 0x0040)
+#define TOPAZ_TQE_DROP_EMAC1_CNT (TOPAZ_TQE_BASE_ADDR + 0x0044)
+#define TOPAZ_TQE_DROP_WMAC_CNT (TOPAZ_TQE_BASE_ADDR + 0x0048)
+#define TOPAZ_TQE_DROP_LHOST_CNT (TOPAZ_TQE_BASE_ADDR + 0x004c)
+#define TOPAZ_TQE_DROP_MUC_CNT (TOPAZ_TQE_BASE_ADDR + 0x0050)
+#define TOPAZ_TQE_DROP_DSP_CNT (TOPAZ_TQE_BASE_ADDR + 0x0054)
+#define TOPAZ_TQE_DROP_AUC_CNT (TOPAZ_TQE_BASE_ADDR + 0x0058)
+#define TOPAZ_TQE_DROP_PCIE_CNT (TOPAZ_TQE_BASE_ADDR + 0x005c)
+
+/* TQE-CPU interface */
+#define TOPAZ_TQE_CPUIF_BASE(num) (TOPAZ_TQE_BASE_ADDR + 0x4000 + 0x1000 * (num)) // For FPGA build 72 and earlier need to use (0xE1040000 + 0x10000 * (num))
+#define TOPAZ_TQE_CPUIF_CSR(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0000)
+#define TOPAZ_TQE_CPUIF_RX_RING_SIZE(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0004)
+#define TOPAZ_TQE_CPUIF_RX_RING(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0008)
+#define TOPAZ_TQE_CPUIF_RX_CURPTR(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x000c)
+#define TOPAZ_TQE_CPUIF_PKT_FINISH(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0010)
+#define TOPAZ_TQE_CPUIF_Q_PTR_STATUS(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0014)
+#define TOPAZ_TQE_CPUIF_PPCTL0(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0020)
+#define TOPAZ_TQE_CPUIF_PPCTL1(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0024)
+#define TOPAZ_TQE_CPUIF_PPCTL2(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0028)
+#define TOPAZ_TQE_CPUIF_PPCTL3(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x002c)
+#define TOPAZ_TQE_CPUIF_PPCTL4(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0030)
+#define TOPAZ_TQE_CPUIF_PPCTL5(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0034)
+#define TOPAZ_TQE_CPUIF_TXSTART(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x0038)
+#define TOPAZ_TQE_CPUIF_STATUS(num) (TOPAZ_TQE_CPUIF_BASE(num) + 0x003C)
+/* Some bits definitions */
+#define TOPAZ_TQE_CPUIF_CSR_IRQ_EN RUBY_BIT(0)
+#define TOPAZ_TQE_CPUIF_CSR_IRQ_THRESHOLD(num) (((num) & 0x7F) << 8)
+#define TOPAZ_TQE_CPUIF_CSR_IRQ_THRESHOLD_EN RUBY_BIT(15)
+#define TOPAZ_TQE_CPUIF_CSR_RESET RUBY_BIT(31)
+/* Aux definitions */
+#define TOPAZ_TQE_CPUIF_RXDESC_ALIGN 8 /* TQE CPU rx descriptors must be 64 bit aligned */
+
+/**
+ * Hardware Buffer Manager
+ */
+#define TOPAZ_HBM_BASE_ADDR (TOPAZ_SWITCH_BASE_ADDR + 0x20000)
+#define TOPAZ_HBM_CSR_REG (TOPAZ_HBM_BASE_ADDR + 0x0000)
+#define TOPAZ_HBM_CSR_Q_EN(x) (BIT(0 + (x)))
+#define TOPAZ_HBM_CSR_INT_EN (BIT(7))
+#define TOPAZ_HBM_CSR_OFLOW_INT_MASK(x) (BIT(8 + (x)))
+#define TOPAZ_HBM_CSR_UFLOW_INT_MASK(x) (BIT(12 + (x)))
+#define TOPAZ_HBM_CSR_OFLOW_INT_RAW(x) (BIT(16 + (x)))
+#define TOPAZ_HBM_CSR_UFLOW_INT_RAW(x) (BIT(20 + (x)))
+#define TOPAZ_HBM_CSR_INT_MSK_RAW (0xff << 16)
+#define TOPAZ_HBM_CSR_OFLOW_INT_STATUS(x) (BIT(24 + (x)))
+#define TOPAZ_HBM_CSR_UFLOW_INT_STATUS(x) (BIT(28 + (x)))
+
+#define TOPAZ_HBM_BASE_REG(x) (TOPAZ_HBM_BASE_ADDR + 0x0004 + ((x) * 0x10))
+#define TOPAZ_HBM_LIMIT_REG(x) (TOPAZ_HBM_BASE_ADDR + 0x0008 + ((x) * 0x10))
+#define TOPAZ_HBM_WR_PTR(x) (TOPAZ_HBM_BASE_ADDR + 0x000c + ((x) * 0x10))
+#define TOPAZ_HBM_RD_PTR(x) (TOPAZ_HBM_BASE_ADDR + 0x0010 + ((x) * 0x10))
+
+#define TOPAZ_HBM_POOL(x) (TOPAZ_HBM_BASE_ADDR + 0x0100 + ((x) * 0x4))
+#define TOPAZ_HBM_POOL_REQ(x) (TOPAZ_HBM_BASE_ADDR + 0x0110 + ((x) * 0x4))
+#define TOPAZ_HBM_POOL_DATA(x) (TOPAZ_HBM_BASE_ADDR + 0x0140 + ((x) * 0x4))
+
+#define TOPAZ_HBM_OVERFLOW_CNT (TOPAZ_HBM_BASE_ADDR + 0x0190)
+#define TOPAZ_HBM_UNDERFLOW_CNT (TOPAZ_HBM_BASE_ADDR + 0x0194)
+
+#define TOPAZ_HBM_MASTER_COUNT 9
+#define TOPAZ_HBM_POOL_COUNT 4
+#define TOPAZ_HBM_POOL_REQUEST_CNT(master, pool) (TOPAZ_HBM_BASE_ADDR + 0x0200 + (master) * 0x20 + (pool) * 0x4)
+#define TOPAZ_HBM_POOL_RELEASE_CNT(master, pool) (TOPAZ_HBM_BASE_ADDR + 0x0210 + (master) * 0x20 + (pool) * 0x4)
+
+#define TOPAZ_HBM_RELEASE_BUF (BIT(0))
+#define TOPAZ_HBM_REQUEST_BUF (BIT(1))
+#define TOPAZ_HBM_POOL_NUM(x) ((x) << 2)
+#define TOPAZ_HBM_DONE (BIT(31))
+
+/* SoC interrupts */
+#define TOPAZ_SYS_CTL_M2L_HI_INT PLATFORM_REG_SWITCH(RUBY_SYS_CTL_M2L_INT, (RUBY_SYS_CTL_BASE_ADDR + 0xFC))
+
+/**
+ * Forwarding Table
+ */
+#define TOPAZ_FWT_BASE_ADDR (TOPAZ_SWITCH_BASE_ADDR + 0x0)
+#define TOPAZ_FWT_SIZE (BIT(12))
+
+#define TOPAZ_FWT_TABLE_BASE (TOPAZ_FWT_BASE_ADDR)
+
+#define TOPAZ_FWT_VLAN_TABLE_BASE (TOPAZ_FWT_BASE_ADDR + 0x10000)
+#define TOPAZ_FWT_VLAN_TABLE_LIMIT (TOPAZ_FWT_BASE_ADDR + 0x14000)
+
+#define TOPAZ_FWT_CTRL_BASE_ADDR (TOPAZ_FWT_BASE_ADDR + 0xA000)
+
+#define TOPAZ_FWT_CPU_ACCESS (TOPAZ_FWT_CTRL_BASE_ADDR + 0x0000)
+#define TOPAZ_FWT_CPU_ACCESS_STATE 0x0000000F
+#define TOPAZ_FWT_CPU_ACCESS_STATE_S 0
+#define TOPAZ_FWT_CPU_ACCESS_STATE_GRANTED 0x3
+#define TOPAZ_FWT_CPU_ACCESS_REQ BIT(31)
+#define TOPAZ_FWT_TIME_STAMP_CTRL (TOPAZ_FWT_CTRL_BASE_ADDR + 0x0004)
+#define TOPAZ_FWT_TIME_STAMP_CTRL_UNIT 0x0000001F
+#define TOPAZ_FWT_TIME_STAMP_CTRL_UNIT_S 0
+#define TOPAZ_FWT_TIME_STAMP_CTRL_SCALE 0x000003e0
+#define TOPAZ_FWT_TIME_STAMP_CTRL_SCALE_S 5
+#define TOPAZ_FWT_TIME_STAMP_DIS_AUTO_UPDATE_S (16)
+#define TOPAZ_FWT_TIME_STAMP_CTRL_CLEAR BIT(31)
+#define TOPAZ_FWT_TIME_STAMP_CNT (TOPAZ_FWT_CTRL_BASE_ADDR + 0x0008)
+#define TOPAZ_FWT_HASH_CTRL (TOPAZ_FWT_CTRL_BASE_ADDR + 0x000c)
+#define TOPAZ_FWT_HASH_CTRL_ENABLE BIT(15)
+
+#define TOPAZ_FWT_LOOKUP_LHOST 0
+#define TOPAZ_FWT_LOOKUP_MUC 1
+#define TOPAZ_FWT_LOOKUP_DSP 2
+#define TOPAZ_FWT_LOOKUP_AUC 3
+
+#define __TOPAZ_FWT_LOOKUP_REG(x) (TOPAZ_FWT_CTRL_BASE_ADDR + 0x0010 + ((x) * 0x10))
+#define __TOPAZ_FWT_LOOKUP_MAC_LO(x) (TOPAZ_FWT_CTRL_BASE_ADDR + 0x0014 + ((x) * 0x10))
+#define __TOPAZ_FWT_LOOKUP_MAC_HI(x) (TOPAZ_FWT_CTRL_BASE_ADDR + 0x0018 + ((x) * 0x10))
+
+#define TOPAZ_FWT_LOOKUP_TRIG 0x00000001
+#define TOPAZ_FWT_LOOKUP_TRIG_S 0
+#define TOPAZ_FWT_LOOKUP_ENTRY_ADDR 0x7FF00000
+#define TOPAZ_FWT_LOOKUP_ENTRY_ADDR_S 20
+#define TOPAZ_FWT_LOOKUP_HASH_ADDR 0x0003FF00
+#define TOPAZ_FWT_LOOKUP_HASH_ADDR_S 8
+#define TOPAZ_FWT_LOOKUP_VALID 0x80000000
+#define TOPAZ_FWT_LOOKUP_VALID_S 31
+
+#define TOPAZ_FWT_PORT_EMAC0 (0)
+#define TOPAZ_FWT_PORT_EMAC1 (1)
+#define TOPAZ_FWT_PORT_WMAC (2)
+#define TOPAZ_FWT_PORT_PCIE (3)
+#define TOPAZ_FWT_PORT_LH (4)
+#define TOPAZ_FWT_PORT_MUC (5)
+#define TOPAZ_FWT_PORT_DSP (6)
+#define TOPAZ_FWT_PORT_AUC (7)
+
+#define TOPAZ_FWT_ENTRY_NXT_ENTRY 0x0FFE0000
+#define TOPAZ_FWT_ENTRY_NXT_ENTRY_S 17
+#define TOPAZ_FWT_ENTRY_VALID 0x80000000
+#define TOPAZ_FWT_ENTRY_VALID_S 31
+#define TOPAZ_FWT_ENTRY_PORTAL 0x40000000
+#define TOPAZ_FWT_ENTRY_PORTAL_S 30
+
+#define TOPAZ_FWT_ENTRY_OUT_NODE_0 0x0000007F
+#define TOPAZ_FWT_ENTRY_OUT_NODE_0_S 0
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_0 0x00000080
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_0_S 7
+#define TOPAZ_FWT_ENTRY_OUT_NODE_1 0x00007F00
+#define TOPAZ_FWT_ENTRY_OUT_NODE_1_S 8
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_1 0x00008000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_1_S 15
+#define TOPAZ_FWT_ENTRY_OUT_NODE_2 0x007F0000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_2_S 16
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_2 0x00800000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_2_S 23
+#define TOPAZ_FWT_ENTRY_OUT_NODE_3 0x7F000000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_3_S 24
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_3 0x80000000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_3_S 31
+#define TOPAZ_FWT_ENTRY_OUT_NODE_4 0x007F0000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_4_S 16
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_4 0x00800000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_4_S 23
+#define TOPAZ_FWT_ENTRY_OUT_NODE_5 0x7F000000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_5_S 24
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_5 0x80000000
+#define TOPAZ_FWT_ENTRY_OUT_NODE_VLD_5_S 31
+
+#define TOPAZ_FWT_ENTRY_OUT_PORT 0x00003C00
+#define TOPAZ_FWT_ENTRY_OUT_PORT_S 10
+
+#define TOPAZ_FWT_ENTRY_TIMESTAMP 0x000003FF
+#define TOPAZ_FWT_ENTRY_TIMESTAMP_S 0
+
+#define TOPAZ_FWT_HW_HASH_SHIFT 10
+#define TOPAZ_FWT_HW_HASH_MASK ((1 << TOPAZ_FWT_HW_HASH_SHIFT) - 1)
+#define TOPAZ_FWT_HW_LEVEL1_ENTRIES (1 << TOPAZ_FWT_HW_HASH_SHIFT)
+#define TOPAZ_FWT_HW_LEVEL2_ENTRIES 1024
+#define TOPAZ_FWT_HW_TOTAL_ENTRIES (TOPAZ_FWT_HW_LEVEL1_ENTRIES + TOPAZ_FWT_HW_LEVEL2_ENTRIES)
+
+/*
+ * VLAN table
+ */
+#define TOPAZ_VLAN_BASE_ADDR (TOPAZ_SWITCH_BASE_ADDR + 0x10000)
+#define TOPAZ_VLAN_ENTRIES (1 << 12) /* 802.1Q VLAN ID */
+#define TOPAZ_VLAN_ENTRY_ADDR(x) (TOPAZ_VLAN_BASE_ADDR + 4 * (x))
+#define TOPAZ_VLAN_OUT_NODE 0x0000007F
+#define TOPAZ_VLAN_OUT_NODE_S 0
+#define TOPAZ_VLAN_OUT_PORT 0x00000380
+#define TOPAZ_VLAN_OUT_PORT_S 7
+#define TOPAZ_VLAN_VALID 0x00000400
+#define TOPAZ_VLAN_VALID_S 10
+#define TOPAZ_VLAN_HW_BITMASK 0x000007ff
+
+/* TX AGG */
+#define TOPAZ_TX_AGG_BASE_ADDR 0xE5090000
+#define TOPAZ_TX_AGG_NODE_N_TID_Q_AVAIL(node) (TOPAZ_TX_AGG_BASE_ADDR + 0x000 + 4 * (node))
+#define TOPAZ_TX_AGG_NODE_N_TID_Q_AVAIL_MASK(val) ((val & 0xFFFF) << 16)
+#define TOPAZ_TX_AGG_NODE_N_TID_Q_AVAIL_SUP(node) (TOPAZ_TX_AGG_BASE_ADDR + 0x200 + 4 * (node))
+#define TOPAZ_TX_AGG_NODE_N_TID_Q_AVAIL_SUP_MASK(val) ((val & 0xFFFF) << 16)
+#define TOPAZ_TX_AGG_CSR (TOPAZ_TX_AGG_BASE_ADDR + 0x460)
+#define TOPAZ_TX_AGG_TAC_MAP_MODE_64 0
+#define TOPAZ_TX_AGG_TAC_MAP_MODE_128 1
+#define TOPAZ_TX_AGG_AC 0xF0000000
+#define TOPAZ_TX_AGG_AC_S 28
+#define TOPAZ_TX_AGG_CPU_Q_ACCESS_SEM (TOPAZ_TX_AGG_BASE_ADDR + 0x464)
+#define TOPAZ_TX_AGG_UC_Q_ACCESS_SEM (TOPAZ_TX_AGG_BASE_ADDR + 0x468)
+#define TOPAZ_TX_AGG_TAC_CNTL (TOPAZ_TX_AGG_BASE_ADDR + 0x46C)
+#ifdef TOPAZ_128_NODE_MODE
+#define TOPAZ_TX_AGG_TAC_CNTL_NODE(node) ((node) & 0x7F)
+#else
+#define TOPAZ_TX_AGG_TAC_CNTL_NODE(node) ((node) & 0x3F)
+#endif
+#define TOPAZ_TX_AGG_TAC_CNTL_TID(tid) (((tid) & 0xF) << 8)
+#define TOPAZ_TX_AGG_TAC_CNTL_READ_CMD(cmd) (((cmd) & 0x3) << 12)
+#define TOPAZ_TX_AGG_TAC_CNTL_READ_DATA_VLD RUBY_BIT(29)
+#define TOPAZ_TX_AGG_TAC_CNTL_READ RUBY_BIT(30)
+#define TOPAZ_TX_AGG_TAC_CNTL_WRITE RUBY_BIT(31)
+#define TOPAZ_TX_AGG_TAC_DATA (TOPAZ_TX_AGG_BASE_ADDR + 0x470)
+#define TOPAZ_TX_AGG_TAC_DATA_AC(__ac) ((__ac) & 0x3)
+#define TOPAZ_TX_AGG_TAC_DATA_PRIORITY(__pri) (((__pri) & 0xFF) << 2)
+#ifdef TOPAZ_128_NODE_MODE
+#define TOPAZ_TX_AGG_TAC_DATA_AC_LO 0x00000003
+#define TOPAZ_TX_AGG_TAC_DATA_AC_LO_S 0
+#define TOPAZ_TX_AGG_TAC_DATA_PRIORITY_LO 0x0000001c
+#define TOPAZ_TX_AGG_TAC_DATA_PRIORITY_LO_S 2
+#define TOPAZ_TX_AGG_TAC_DATA_AC_HI 0x00000060
+#define TOPAZ_TX_AGG_TAC_DATA_AC_HI_S 5
+#define TOPAZ_TX_AGG_TAC_DATA_PRIORITY_HI 0x00000380
+#define TOPAZ_TX_AGG_TAC_DATA_PRIORITY_HI_S 7
+#endif
+#define TOPAZ_TX_AGG_AC_N_NODE_TID(ac) (TOPAZ_TX_AGG_BASE_ADDR + 0x478 + 4 * (ac))
+#define TOPAZ_TX_AGG_AC_N_STAT_PTR(ac) (TOPAZ_TX_AGG_BASE_ADDR + 0x488 + 4 * (ac))
+#define TOPAZ_TX_AGG_Q_FULL_THRESH (TOPAZ_TX_AGG_BASE_ADDR + 0x498)
+#define TOPAZ_TX_AGG_Q_FULL_THRESH_VAL(q0, q1, q2, q3) (((q0) & 0xF) | (((q1) & 0xF) << 4) | (((q2) & 0xF) << 8) | (((q3) & 0xF) << 12))
+#define TOPAZ_TX_AGG_CPU_IRQ_CSR (TOPAZ_TX_AGG_BASE_ADDR + 0x49C)
+#define TOPAZ_TX_AGG_STATUS_IRQ (TOPAZ_TX_AGG_BASE_ADDR + 0x4A0)
+#define TOPAZ_TX_AGG_AC_N_NODE_TID_NO_SEL(ac) (TOPAZ_TX_AGG_BASE_ADDR + 0x4A4 + 4 * (ac))
+#define TOPAZ_TX_AGG_TAC_CNTL_READ_CMD_NODE_TAB 0
+#define TOPAZ_TX_AGG_TAC_CNTL_READ_CMD_AVAIL_LO 1
+#define TOPAZ_TX_AGG_TAC_CNTL_READ_CMD_AVAIL_HI 3
+#define TOPAZ_TX_AGG_MAX_NODE_NUM 128
+#define TOPAZ_TX_AGG_HALF_MAX_NODE_NUM (TOPAZ_TX_AGG_MAX_NODE_NUM >> 1)
+
+/*
+ * MuC/Lhost new interrupts.
+ * Old interrupts (even changed number) are in ruby_platform, RUBY_IRQ_*
+ */
+#define TOPAZ_IRQ_TQE (5)
+#define TOPAZ_IRQ_HDMA0 (RUBY_IRQ_DMA0)
+#define TOPAZ_IRQ_HBM (RUBY_IRQ_DMA1)
+#define TOPAZ_IRQ_HDMA1 (RUBY_IRQ_DMA3)
+#define TOPAZ_IRQ_PCIE (28)
+#define TOPAZ_IRQ_IPC_A2M (18)
+#define TOPAZ_IQR_TQE_DSP (19)
+#define TOPAZ_IRQ_PCIE_DMA (RUBY_IRQ_DMA2)
+#define TOPAZ_IRQ_IPC4 (29)
+#define TOPAZ_MUC_IRQ_BB_PER_PKT (31)
+#define TOPAZ_HBM_INT_EN RUBY_BIT(31)
+#define TOPAZ_PCIE_INTX_CLR_MASK RUBY_BIT(11)
+#define TOPAZ_PCIE_INT_MASK RUBY_PCIE_INT_MASK
+#define TOPAZ_PCIE_MSI_MASK RUBY_PCIE_MSI_MASK
+#define TOPAZ_PCIE_MSI_EN RUBY_BIT(0)
+#define TOPAZ_PCIE_MSI_BASE 0xE9000050
+#define TOPAZ_PCIE_MSI_CAP (TOPAZ_PCIE_MSI_BASE + 0x0)
+
+#define TOPAZ_PCIE_EXP_DEVCTL (0xE9000078)
+
+/* MSI defines to be used in Topaz PCIe host driver */
+#define TOPAZ_PCIE_MSI_REGION RUBY_PCIE_MSI_REGION
+#define TOPAZ_MSI_ADDR_LOWER RUBY_MSI_ADDR_LOWER
+#define TOPAZ_MSI_ADDR_UPPER RUBY_MSI_ADDR_UPPER
+#define TOPAZ_MSI_INT_ENABLE RUBY_MSI_INT_ENABLE
+
+/* AHB Bus monitors */
+#define TOPAZ_BUSMON_INTR_STATUS (RUBY_SYS_CTL_BASE_ADDR + 0x015c)
+#define TOPAZ_BUSMON_INTR_MASK (RUBY_SYS_CTL_BASE_ADDR + 0x0160)
+#define TOPAZ_BUSMON_INTR_MASK_TIMEOUT_EN(master) BIT((master) * 2 + 0)
+#define TOPAZ_BUSMON_INTR_MASK_RANGE_CHECK_EN(master) BIT((master) * 2 + 1)
+#define TOPAZ_BUSMON_DEBUG_VIEW (RUBY_SYS_CTL_BASE_ADDR + 0x0164)
+#define TOPAZ_BUSMON_DEBUG_VIEW_MASTER(x) (((x) & 0x3) << 0)
+#define TOPAZ_BUSMON_DEBUG_VIEW_DATA_SEL(x) (((x) & 0x7) << 2)
+#define TOPAZ_BUSMON_DEBUG_STATUS (RUBY_SYS_CTL_BASE_ADDR + 0x0168)
+#define TOPAZ_BUSMON_CTL_BASE_ADDR (RUBY_SYS_CTL_BASE_ADDR + 0x0200)
+#define TOPAZ_BUSMON_CTL(core) (TOPAZ_BUSMON_CTL_BASE_ADDR + ((core) * 0x40))
+#define __TOPAZ_BUSMON_CTL_RANGE(core, range) (TOPAZ_BUSMON_CTL(core) + 0x8 + ((range) * 0x8))
+#define TOPAZ_BUSMON_CTL_RANGE_LOW(core, range) (__TOPAZ_BUSMON_CTL_RANGE((core), (range)) + 0x0)
+#define TOPAZ_BUSMON_CTL_RANGE_HIGH(core, range) (__TOPAZ_BUSMON_CTL_RANGE((core), (range)) + 0x4)
+#define TOPAZ_BUSMON_HREADY_EN BIT(0)
+#define TOPAZ_BUSMON_TIMER_INT_EN BIT(1)
+#define TOPAZ_BUSMON_TIMER_ERROR_EN BIT(2)
+#define TOPAZ_BUSMON_ADDR_CHECK_EN BIT(3)
+#define TOPAZ_BUSMON_REGION_VALID(x) (((x) & 0xF) << 4)
+#define TOPAZ_BUSMON_TIMEOUT(cycles) (((cycles) & 0x3FF) << 8)
+#define TOPAZ_BUSMON_BLOCK_TRANS_EN BIT(18)
+#define TOPAZ_BUSMON_OUTSIDE_ADDR_CHECK BIT(19)
+
+/* AHB Bus monitor masters */
+#define TOPAZ_BUSMON_LHOST 0
+#define TOPAZ_BUSMON_MUC 1
+#define TOPAZ_BUSMON_DSP 2
+#define TOPAZ_BUSMON_AUC 3
+#define TOPAZ_BUSMON_WMAC 4
+#define TOPAZ_BUSMON_PCIE 5
+#define TOPAZ_BUSMON_SWE 6
+#define TOPAZ_BUSMON_EMAC 7
+
+#define TOPAZ_BUSMON_MASTER_NAMES { "lhost", "muc", "dsp", "auc", "wmac", "pcie", "swe", "emac" }
+
+/* AHB Bus monitor debug data select */
+#define TOPAZ_BUSMON_ADDR 0
+#define TOPAZ_BUSMON_WR_L32 1
+#define TOPAZ_BUSMON_WR_H32 2
+#define TOPAZ_BUSMON_RD_L32 3
+#define TOPAZ_BUSMON_RD_H32 4
+#define TOPAZ_BUSMON_CTRL0 5
+#define TOPAZ_BUSMON_CTRL1 6
+#define TOPAZ_BUSMON_CTRL2 7
+#define TOPAZ_BUSMON_DEBUG_MAX 8
+
+/* GPIO Registers */
+#define RUBY_GPIO3_PWM1 (RUBY_GPIO1_PWM0 + 4)
+#define RUBY_GPIO12_PWM3 (RUBY_GPIO1_PWM0 + 12)
+#define RUBY_GPIO13_PWM4 (RUBY_GPIO1_PWM0 + 16)
+#define RUBY_GPIO15_PWM5 (RUBY_GPIO1_PWM0 + 20)
+#define RUBY_GPIO16_PWM6 (RUBY_GPIO1_PWM0 + 24)
+#define RUBY_GPIO_PWM_LOW_SHIFT (0)
+#define RUBY_GPIO_PWM_HIGH_SHIFT (8)
+#define RUBY_GPIO_PWM_ENABLE (BIT(16))
+#define RUBY_GPIO_PWM_MAX_COUNT (255)
+
+#ifdef TOPAZ_AMBER_IP
+#define AMBER_GPIO11_PWM0 (RUBY_GPIO_REGS_ADDR + 0x20)
+#define AMBER_GPIO12_PWM1 (RUBY_GPIO_REGS_ADDR + 0x24)
+#define AMBER_GPIO13_PWM2 (RUBY_GPIO_REGS_ADDR + 0x28)
+#define AMBER_GPIO14_PWM3 (RUBY_GPIO_REGS_ADDR + 0x2C)
+#define AMBER_GPIO15_PWM4 (RUBY_GPIO_REGS_ADDR + 0x30)
+#define AMBER_GPIO16_PWM5 (RUBY_GPIO_REGS_ADDR + 0x34)
+#define AMBER_GPIO17_PWM6 (RUBY_GPIO_REGS_ADDR + 0x38)
+#endif
+
+/* Interrupt lines */
+#define TOPAZ_IRQ_MISC_WDT (57)
+#define TOPAZ_IRQ_MISC_SPI1 (58)
+#define TOPAZ_IRQ_MISC_AHB_MON (61)
+#define TOPAZ_IRQ_MISC_HBM (62)
+#define TOPAZ_IRQ_MISC_FWT (63)
+#define TOPAZ_IRQ_MISC_EXT_IRQ_COUNT (8)
+#define TOPAZ_IRQ_MISC_RST_CAUSE_START (9)
+
+/* RESET CAUSE */
+#define TOPAZ_SYS_CTL_INTR_TIMER_MSK(t) (1 << (3 + (t)))
+
+#endif /* #ifndef __TOPAZ_PLATFORM_H */
