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#ifndef __INCmvDramIfConfigh
#define __INCmvDramIfConfigh
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* includes */
/* defines */
/* registers defaults values */
#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30)
#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \
(SDRAM_SRCLK_KEPT | \
SDRAM_CLK1DRV_NORMAL | \
(BIT28 | BIT29))
#define SDRAM_ADDR_CTRL_DV 2
#define SDRAM_TIMING_CTRL_LOW_REG_DV \
((0x2 << SDRAM_TRCD_OFFS) | \
(0x2 << SDRAM_TRP_OFFS) | \
(0x1 << SDRAM_TWR_OFFS) | \
(0x0 << SDRAM_TWTR_OFFS) | \
(0x5 << SDRAM_TRAS_OFFS) | \
(0x1 << SDRAM_TRRD_OFFS))
/* Note: value of 0 in register means one cycle, 1 means two and so on */
#define SDRAM_TIMING_CTRL_HIGH_REG_DV \
((0x0 << SDRAM_TR2R_OFFS) | \
(0x0 << SDRAM_TR2W_W2R_OFFS) | \
(0x1 << SDRAM_TW2W_OFFS))
#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN
/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */
/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */
/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */
/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */
/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */
#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000
#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000
#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F
#ifdef MV78XX0
#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040
#else
#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440
#endif
#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C
#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000
#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F
#ifdef MV78XX0
#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004
#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044
#else
#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404
#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444
#endif
/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */
#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \
(3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \
(3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS)
/* DDR SDRAM Mode Register default value */
#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC)
/* DDR SDRAM Timing parameter default values */
#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552
#define SDRAM_TRFC_DEFAULT_VALUE 0x34
#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE
#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS)
#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT)
#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800
#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800
#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __INCmvDramIfh */