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| *******************************************************************************/ |
| |
| #ifndef __INCmvDramIfStaticInith |
| #define __INCmvDramIfStaticInith |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifdef MV_STATIC_DRAM_ON_BOARD |
| #define STATIC_DRAM_BANK_1 |
| #undef STATIC_DRAM_BANK_2 |
| #undef STATIC_DRAM_BANK_3 |
| #undef STATIC_DRAM_BANK_4 |
| |
| #ifdef MV_DIMM_TS256MLQ72V5U |
| #define STATIC_DRAM_BANK_2 |
| #define STATIC_DRAM_BANK_3 |
| #undef STATIC_DRAM_BANK_4 |
| |
| #define STATIC_SDRAM_CONFIG_REG 0x4724481A /* offset 0x1400 - DMA reg-0xf1000814 */ |
| #define STATIC_SDRAM_DUNIT_CTRL_REG 0x37707450 /* offset 0x1404 - DMA reg-0xf100081c */ |
| #define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11A13330 /* offset 0x1408 - DMA reg-0xf1000824 */ |
| #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000601 /* offset 0x140c - DMA reg-0xf1000828 */ |
| #define STATIC_SDRAM_ADDR_CTRL_REG 0x00001CB2 /* offset 0x1410 - DMA reg-0xf1000820 */ |
| #define STATIC_SDRAM_MODE_REG 0x00000642 /* offset 0x141c - DMA reg-0xf1000818 */ |
| #define STATIC_SDRAM_ODT_CTRL_LOW 0x030C030C /* 0x1494 */ |
| #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ |
| #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000740F /* 0x149c */ |
| #define STATIC_SDRAM_EXT_MODE 0x00000404 /* 0x1420 */ |
| #define STATIC_SDRAM_DDR2_TIMING_LO 0x00074410 /* 0x1428 */ |
| #define STATIC_SDRAM_DDR2_TIMING_HI 0x00007441 /* 0x147C */ |
| |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x3FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */ |
| #define STATIC_SDRAM_RANK1_SIZE_DIMM0 0x3FFF /* size bank1 dimm0 */ |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x3FFF /* size bank0 dimm1 */ |
| #define STATIC_SDRAM_RANK1_SIZE_DIMM1 0x0 /* size bank1 dimm1 */ |
| |
| #endif /* TS256MLQ72V5U */ |
| |
| #ifdef MV_MT9VDDT3272AG |
| /* one DIMM 256M */ |
| #define STATIC_SDRAM_CONFIG_REG 0x5820040d /* offset 0x1400 - DMA reg-0xf1000814 */ |
| #define STATIC_SDRAM_DUNIT_CTRL_REG 0xC4000540 /* offset 0x1404 - DMA reg-0xf100081c */ |
| #define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01602220 /* offset 0x1408 - DMA reg-0xf1000824 */ |
| #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x0000000b /* offset 0x140c - DMA reg-0xf1000828 */ |
| #define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */ |
| #define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */ |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0fff /* size bank0 dimm0 - DMA reg-0xf1000810 */ |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0 /* size bank0 dimm1 */ |
| |
| #endif /* MV_MT9VDDT3272AG */ |
| |
| #ifdef MV_D27RB12P |
| /* |
| Two DIMM 512M + ECC enabled, Registered DIMM CAS Latency 2.5 |
| */ |
| |
| #define STATIC_SDRAM_CONFIG_REG 0x6826081E /* offset 0x1400 - DMA reg-0xf1000814 */ |
| #define STATIC_SDRAM_DUNIT_CTRL_REG 0xC5000540 /* offset 0x1404 - DMA reg-0xf100081c */ |
| #define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x01501220 /* offset 0x1408 - DMA reg-0xf1000824 */ |
| #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000009 /* offset 0x140c - DMA reg-0xf1000828 */ |
| #define STATIC_SDRAM_ADDR_CTRL_REG 0x00000012 /* offset 0x1410 - DMA reg-0xf1000820 */ |
| #define STATIC_SDRAM_MODE_REG 0x00000062 /* offset 0x141c - DMA reg-0xf1000818 */ |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x0FFF /* size bank0 dimm0 - DMA reg-0xf1000810 */ |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM1 0x0FFF /* size bank0 dimm1 */ |
| |
| #define STATIC_DRAM_BANK_2 |
| |
| #define STATIC_DRAM_BANK_3 |
| #define STATIC_DRAM_BANK_4 |
| |
| #endif /* mv_D27RB12P */ |
| |
| #ifdef RD_MV645XX |
| |
| #define STATIC_MEM_TYPE MEM_TYPE_DDR2 |
| #define STATIC_DIMM_INFO_BANK0_SIZE 256 |
| /* DDR2 boards 256 MB*/ |
| |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000fff /* size bank0 dimm0 - DMA reg-0xf1000810 */ |
| #define STATIC_SDRAM_CONFIG_REG 0x07190618 |
| #define STATIC_SDRAM_MODE_REG 0x00000432 |
| #define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440 |
| #define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022 |
| #define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220 |
| #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504 |
| #define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 |
| #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 |
| #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f |
| #define STATIC_SDRAM_EXT_MODE 0x00000440 |
| #define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300 |
| #define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330 |
| #endif /* RD_MV645XX */ |
| |
| #ifdef MV_DIMM_M3783354CZ3_CE6 |
| |
| #define STATIC_SDRAM_RANK0_SIZE_DIMM0 0x00000FFF /* 0x2010 size bank0 dimm0 - DMA reg-0xf1000810 */ |
| #define STATIC_SDRAM_CONFIG_REG 0x07190618 /* 0x1400 */ |
| #define STATIC_SDRAM_MODE_REG 0x00000432 /* 0x141c */ |
| #define STATIC_SDRAM_DUNIT_CTRL_REG 0xf4a03440 /* 0x1404 */ |
| #define STATIC_SDRAM_ADDR_CTRL_REG 0x00000022 /* 0x1410 */ |
| #define STATIC_SDRAM_TIMING_CTRL_LOW_REG 0x11712220 /* 0x1408 */ |
| #define STATIC_SDRAM_TIMING_CTRL_HIGH_REG 0x00000504 /* 0x140c */ |
| #define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ |
| #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ |
| #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000780f /* 0x149c */ |
| #define STATIC_SDRAM_EXT_MODE 0x00000440 /* 0x1420 */ |
| #define STATIC_SDRAM_DDR2_TIMING_LO 0x00063300 /* 0x1428 */ |
| #define STATIC_SDRAM_DDR2_TIMING_HI 0x00006330 /* 0x147C */ |
| |
| #endif /* MV_DIMM_M3783354CZ3_CE6 */ |
| |
| #endif /* MV_STATIC_DRAM_ON_BOARD */ |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif /* __INCmvDramIfStaticInith */ |