prism: initial board config.

Added config gflt200.

Change-Id: I19931b0b543c50d3069709b8ac7b99a0df259975
diff --git a/Makefile b/Makefile
index 9dd6c3f..448392c 100644
--- a/Makefile
+++ b/Makefile
@@ -2670,6 +2670,7 @@
 rd88f6530mdu_config \
 db88f6601bp_config \
 rd88f6601mc_config \
+gflt200_config \
 kw2_test:
 	@$(MAKE) -s mv_kw2 RULE=$@
 mv_kw2:	unconfig
@@ -2699,6 +2700,9 @@
 	elif [ "$(findstring test,$(RULE))" ] ; then \
 		echo "#define MV88F6192" > $(obj)include/config.h ;	\
 		echo "  * Configured for MV88F6192"; \
+	elif [ "$(findstring gflt200,$(RULE))" ] ; then \
+		echo "#define MV88F6601" > $(obj)include/config.h ;	\
+		echo "  * Configured for MV88F6601"; \
 	else \
 		echo "  * Error Marvell SoC not configured!"; \
 	fi;
@@ -2768,6 +2772,12 @@
 		echo "#define MV_BOOTROM" >> $(obj)include/config.h ;	\
 		echo "MV_DDR_FREQ=400rd_kw2" >> $(obj)include/config.mk ;	\
 		echo "  * Configured for DB-88F6192A-BP"; \
+	elif [ "$(findstring gflt200_config,$(RULE))" ] ; then\
+		echo "#define GFLT200" >> $(obj)include/config.h ;	\
+		echo "#define MV_BOOTSIZE_512K" >> $(obj)include/config.h ; \
+		echo "#define MV_BOOTROM" >> $(obj)include/config.h ;	\
+		echo "MV_DDR_FREQ=400rd_A-MC" >> $(obj)include/config.mk ;\
+		echo "  * Configured for GFLT200"; \
 	else \
 		echo "  * Error no board was configured"; \
 	fi;
diff --git a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c
index 39a1f74..7fdff75 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvLib.c
@@ -152,19 +152,22 @@
 	/* Set GPP Out value */
 	MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow);
 	MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValMid);
-	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID))
+	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID)
+		&& (boardId != GFLT200_ID))
 		MV_REG_WRITE(GPP_DATA_OUT_REG(2), BOARD_INFO(boardId)->gppOutValHigh);
 
 	/* set GPP polarity */
 	mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow);
 	mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValMid);
-	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID))
+	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID)
+		&& (boardId != GFLT200_ID))
 		mvGppPolaritySet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh);
 
 	/* Set GPP Out Enable */
 	mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow);
 	mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValMid);
-	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID))
+	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID)
+		&& (boardId != GFLT200_ID))
 		mvGppTypeSet(2, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh);
 
 	/* Nand CE */
@@ -348,7 +351,8 @@
 		return MV_FALSE;
 	}
 
-	if (RD_88F6601_MC_ID == mvBoardIdGet())
+	if ((RD_88F6601_MC_ID == mvBoardIdGet())
+		|| (GFLT200_ID == mvBoardIdGet()))
 		return MV_FALSE;
 
 	if ((ethPortNum > 0) || (ethCompOpt & ESC_OPT_SGMII_2_SW_P1))
@@ -646,7 +650,8 @@
 		mvOsPrintf("mvBoardSwitchNumPortsGet: Board unknown.\n");
 		return MV_ERROR;
 	}
-	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId))
+	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)
+		|| (GFLT200_ID == boardId))
 	{
 		return 0;
 	}
@@ -1247,7 +1252,8 @@
 	MV_U32 boardId = mvBoardIdGet();
 
 	tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET(0));
-	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)){
+	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)
+		|| (GFLT200_ID == boardId)){
 		tmpTClkRate &= MSAR_TCLCK_6601_MASK;
 		if (tmpTClkRate ) 
 			return MV_BOARD_TCLK_200MHZ;
@@ -1302,7 +1308,8 @@
 	sar0 = MV_REG_READ(MPP_SAMPLE_AT_RESET(0));
 	clockSatr = MSAR_CPU_DDR_L2_CLCK_EXTRACT(sar0);
 	i = 0;
-	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)){
+	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)
+		|| (GFLT200_ID == boardId)){
 		while (cpuDdrTbl6601[i].satrValue != -1) {
 			if (cpuDdrTbl6601[i].satrValue == clockSatr) {
 				res = i;
@@ -1690,7 +1697,8 @@
 	/* Set ethernet complex configuration. */
 	BOARD_INFO(boardId)->pBoardMppTypeValue->ethSataComplexOpt = ethConfig;
 
-	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID))
+	if ((boardId != DB_88F6601_BP_ID) && (boardId != RD_88F6601_MC_ID)
+		&& (boardId != GFLT200_ID))
 	{	/* KW2 only */
 		/* Update link speed for MAC0 / 1 */
 		/* If MAC 0 is connected to switch, then set to speed 1000Mbps */
@@ -2320,7 +2328,8 @@
 			return MV_TRUE;
 		return MV_FALSE;
 	}
-	if (RD_88F6601_MC_ID == mvBoardIdGet()) {
+	if ((RD_88F6601_MC_ID == mvBoardIdGet())
+		|| (GFLT200_ID == mvBoardIdGet())) {
 		if (ethPortNum == 0)
 			return MV_TRUE;
 		return MV_FALSE;
@@ -2723,6 +2732,8 @@
 		tmpBoardId = RD_88F6601_MC_ID;
 #elif defined(DB_CUSTOMER)
 		tmpBoardId = DB_CUSTOMER_ID;
+#elif defined(GFLT200)
+		tmpBoardId = GFLT200_ID;
 #endif
 		gBoardId = tmpBoardId;
 	}
diff --git a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
index f90b770..56eccef 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.c
@@ -1155,6 +1155,134 @@
 MV_BOARD_INFO dbCustomerInfo = { };
 
 
+/***************************************************************************
+** gflt200 prism
+****************************************************************************/
+/* NAND not supported  */
+
+MV_BOARD_TWSI_INFO gflt200InfoBoardTwsiDev[] = {
+	/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+};
+
+MV_BOARD_MAC_INFO gflt200InfoBoardMacInfo[] = {
+	/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */
+	{BOARD_MAC_SPEED_AUTO, 0x0},
+	{BOARD_MAC_SPEED_AUTO, 0x1},
+	{N_A,N_A}
+};
+
+MV_BOARD_MPP_TYPE_INFO gflt200InfoBoardMppTypeInfo[] = {
+	{
+		.boardMppTdm = MV_BOARD_AUTO,
+		.ethSataComplexOpt = ESC_OPT_GEPHY_MAC0,
+		.ethPortsMode = 0x0
+	}
+};
+
+MV_BOARD_GPP_INFO gflt200InfoBoardGppInfo[] = {
+	/* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */
+	{BOARD_GPP_PON_XVR_TX, 17},
+};
+
+MV_DEV_CS_INFO gflt200InfoBoardDeCsInfo[] = {
+	/*{deviceCS, params, devType, devWidth} */
+#ifdef MV_SPI
+	{SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8},		/* SPI DEV */
+#endif
+#if !defined(MV_SPI)
+	{N_A, N_A, N_A, N_A}			/* No device */
+#endif
+};
+
+MV_BOARD_MPP_INFO gflt200InfoBoardMppConfigValue[] = {
+	{{
+	  GFLT200_MPP0_7,
+	  GFLT200_MPP8_15,
+	  GFLT200_MPP16_23,
+	  GFLT200_MPP24_31,
+	  GFLT200_MPP32_37
+	  }
+	 }
+};
+
+/*
+MV_BOARD_SPEC_INIT gflt200BoardSpecInit[] = {
+	{
+		.reg = PMU_POWER_IF_POLARITY_REG,
+		.mask = (BIT1),
+		.val = 0
+	},
+	{
+		.reg = TBL_TERM,
+		.val = TBL_TERM
+	}
+};
+*/
+MV_BOARD_INFO gflt200Info = {
+	.boardName = "GFLT200",
+	.numBoardMppTypeValue = MV_ARRAY_SIZE(gflt200InfoBoardMppTypeInfo),
+	.pBoardMppTypeValue = gflt200InfoBoardMppTypeInfo,
+	.numBoardMppConfigValue = MV_ARRAY_SIZE(gflt200InfoBoardMppConfigValue),
+	.pBoardMppConfigValue = gflt200InfoBoardMppConfigValue,
+	.intsGppMaskLow = 0,
+	.intsGppMaskMid = 0,
+	.intsGppMaskHigh = 0,
+	.numBoardDeviceIf = MV_ARRAY_SIZE(gflt200InfoBoardDeCsInfo),
+	.pDevCsInfo = gflt200InfoBoardDeCsInfo,
+	.numBoardTwsiDev = MV_ARRAY_SIZE(gflt200InfoBoardTwsiDev),
+	.pBoardTwsiDev = gflt200InfoBoardTwsiDev,
+	.numBoardMacInfo = MV_ARRAY_SIZE(gflt200InfoBoardMacInfo),
+	.pBoardMacInfo = gflt200InfoBoardMacInfo,
+	.numBoardGppInfo = MV_ARRAY_SIZE(gflt200InfoBoardGppInfo),
+	.pBoardGppInfo = gflt200InfoBoardGppInfo,
+	.activeLedsNumber = 0,
+	.pLedGppPin = NULL,
+	.ledsPolarity = 0,
+
+	/* GPP values */
+	.gppOutEnValLow = GFLT200_GPP_OUT_ENA_LOW,
+	.gppOutEnValMid = GFLT200_GPP_OUT_ENA_MID,
+	.gppOutEnValHigh = 0,
+	.gppOutValLow = GFLT200_GPP_OUT_VAL_LOW,
+	.gppOutValMid = GFLT200_GPP_OUT_VAL_MID,
+	.gppOutValHigh = 0,
+	.gppPolarityValLow = GFLT200_GPP_POL_LOW,
+	.gppPolarityValMid = GFLT200_GPP_POL_MID,
+	.gppPolarityValHigh = 0,
+
+	/* External Switch Configuration */
+	.pSwitchInfo = NULL,
+	.switchInfoNum = 0,
+
+	/* PON configuration. */
+	.ponConfigValue = BOARD_GPON_CONFIG,
+
+	/* TDM configuration */
+	/* We hold a different configuration array for each possible slic that
+	 ** can be connected to board.
+	 ** When modules are scanned, then we select the index of the relevant
+	 ** slic's information array.
+	 ** For RD and Customers boards we only need to initialize a single
+	 ** entry of the arrays below, and set the boardTdmInfoIndex to 0.
+	 */
+	.numBoardTdmInfo = {0},
+	.pBoardTdmInt2CsInfo = {NULL},
+	.boardTdmInfoIndex = -1,
+
+	.pBoardSpecInit = NULL,			/* gflt200BoardSpecInit, */
+
+	.deepIdlePwrUpDelay = 2400,	/* 12uS */
+
+	/* NAND init params */
+	.nandFlashParamsValid = MV_FALSE,
+	.nandFlashReadParams = 0,
+	.nandFlashWriteParams = 0,
+	.nandFlashControl = 0,
+	.pBoardTdmSpiInfo = NULL,
+
+	/* Enable modules auto-detection. */
+	.moduleAutoDetect = MV_FALSE
+};
 
 MV_BOARD_INFO *boardInfoTbl[] = {
 	&db88f6535Info,
@@ -1164,6 +1292,6 @@
 	&db88f6560PCACPInfo,
 	&db88f6601Info,
 	&rd88f6601Info,
-	&dbCustomerInfo,
+	&gflt200Info,
 };
 
diff --git a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h
index ffe4375..45be7ae 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_feroceon/mv_kw2/kw2_family/boardEnv/mvBoardEnvSpec.h
@@ -108,6 +108,7 @@
 #define DB_88F6601_BP_ID		(BOARD_ID_BASE+0x5)
 #define RD_88F6601_MC_ID		(BOARD_ID_BASE+0x6)
 #define DB_CUSTOMER_ID			(BOARD_ID_BASE+0x7)
+#define GFLT200_ID			DB_CUSTOMER_ID
 #define MV_MAX_BOARD_ID			(DB_CUSTOMER_ID + 1)
 
 /***************************************************************************
@@ -461,5 +462,52 @@
 #define RD_88F6601_GPP_POL_LOW		(BIT23)
 #define RD_88F6601_GPP_POL_MID		0x0
 
+/***************************************************************************
+** GFLT200
+****************************************************************************/
+#define GFLT200_MPP0_7			0x22222220
+#define GFLT200_MPP8_15			0x00000002
+#define GFLT200_MPP16_23		0x00000000
+#define GFLT200_MPP24_31		0x40000000
+#define GFLT200_MPP32_37		0x00000004
+
+/* GPPs
+ 1 SPI_MOSI (out)
+ 2 SPI_SCK (out)
+ 3 SPI_CS_L (out)
+ 4 SPI_MISO (in)
+ 5 I2C_SDA (inout)
+ 6 I2C_SCLK (inout)
+ 7 UART0_TX (out)
+ 8 UART0_RX (in)
+ 9 VDD_MARGIN_EN (out)
+10 VDD_MARGIN_CTRL (out)
+11 PON_LINK_LED (out)
+12 PON_ERROR_LED (out)
+13 BOARD_VER[0] (in)
+15 BOARD_VER[1] (in)
+17 SW_RESET (out)
+18 BOARD_VER[2] (in)
+21 PON_TX_DIS (out)
+23 GE_DATA_LED (out)
+24 GE_LINK_LED (out)
+26 PON_C2_DATA (out)
+27 PON_C2_CLK (out)
+28 SPI_WP_L (out)
+29 PON_RX_LOS (in)
+31 UART1_RX (out)
+32 UART2_TX (in)
+36 PON_RX_PMON (in)
+37 PON_PWR_EN_L (out)
+*/
+
+#define GFLT200_GPP_OUT_ENA_LOW		(BIT13 | BIT15 | BIT18 | BIT29)
+#define GFLT200_GPP_OUT_ENA_MID		(BIT4)
+
+#define GFLT200_GPP_OUT_VAL_LOW		(BIT9 | BIT10 | BIT21 | BIT26 | BIT27 | BIT28)
+#define GFLT200_GPP_OUT_VAL_MID		0x0
+
+#define GFLT200_GPP_POL_LOW		0x0
+#define GFLT200_GPP_POL_MID		0x0
 
 #endif /* __INCmvBoardEnvSpech */
diff --git a/board/mv_feroceon/mv_kw2/kw2_family/cpu/mvCpu.c b/board/mv_feroceon/mv_kw2/kw2_family/cpu/mvCpu.c
index 8f1d3e5..dbb62fa 100644
--- a/board/mv_feroceon/mv_kw2/kw2_family/cpu/mvCpu.c
+++ b/board/mv_feroceon/mv_kw2/kw2_family/cpu/mvCpu.c
@@ -111,7 +111,8 @@
 
 	/* Search for a matching entry */
 	i = 0;
-	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)){
+	if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)
+		|| (GFLT200_ID == boardId)){
 		while (cpuDdrTbl6601[i].satrValue != -1) {
 			if (cpuDdrTbl6601[i].satrValue == clockSatr) {
 				res = i;
@@ -159,7 +160,8 @@
 	if (idx == 0xFFFFFFFF)
 		return 0;
 	else {
-		if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId))
+		if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)
+			|| (GFLT200_ID == boardId))
 			return cpuDdrTbl6601[idx].cpuClk;
 		else
 			return cpuDdrL2Tbl[idx].cpuClk;
@@ -192,7 +194,8 @@
 	if (idx == 0xFFFFFFFF)
 		return 0;
 	else {
-		if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId))
+		if ((RD_88F6601_MC_ID == boardId) || (DB_88F6601_BP_ID == boardId)
+			|| (GFLT200_ID == boardId))
 			return cpuDdrTbl6601[idx].l2Clk;
 		else
 			return cpuDdrL2Tbl[idx].l2Clk;
@@ -220,7 +223,8 @@
 
 	if ((RD_88F6510_SFU_ID == mvBoardId) ||
 		(RD_88F6601_MC_ID == mvBoardId) ||
-		(DB_88F6601_BP_ID == mvBoardId))
+		(DB_88F6601_BP_ID == mvBoardId) ||
+		(GFLT200_ID == mvBoardId))
 		return MV_FALSE;
 
 	/* Read S@R register value */