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| this list of conditions and the following disclaimer. |
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| *******************************************************************************/ |
| |
| #ifndef __INCmvSpiSpecH |
| #define __INCmvSpiSpecH |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #include "mvSysSpiConfig.h" |
| |
| /* Constants */ |
| #define MV_SPI_WAIT_RDY_MAX_LOOP 100000 |
| #define MV_SPI_16_BIT_CHUNK_SIZE 2 |
| #define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF |
| #define MV_SPI_DUMMY_WRITE_8BITS 0xFF |
| |
| /* Marvell Flash Device Controller Registers */ |
| #define MV_SPI_IF_CTRL_REG(spiId) (MV_SPI_REGS_BASE(spiId) + 0x00) |
| #define MV_SPI_IF_CONFIG_REG(spiId) (MV_SPI_REGS_BASE(spiId) + 0x04) |
| #define MV_SPI_DATA_OUT_REG(spiId) (MV_SPI_REGS_BASE(spiId) + 0x08) |
| #define MV_SPI_DATA_IN_REG(spiId) (MV_SPI_REGS_BASE(spiId) + 0x0c) |
| #define MV_SPI_INT_CAUSE_REG(spiId) (MV_SPI_REGS_BASE(spiId) + 0x10) |
| #define MV_SPI_INT_CAUSE_MASK_REG(spiId) (MV_SPI_REGS_BASE(spiId) + 0x14) |
| #define MV_SPI_TMNG_PARAMS_REG(spiId) (MV_SPI_REGS_BASE(spiId) + 0x18) |
| |
| /* Serial Memory Interface Control Register Masks */ |
| #define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ |
| #define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ |
| #define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) |
| #define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) |
| #define MV_SPI_CS_NUM_OFFSET 2 |
| #define MV_SPI_CS_NUM_MASK (0x7 << MV_SPI_CS_NUM_OFFSET) |
| |
| /* SPI Timing Parameters Register */ |
| #define MV_SPI_TCSH_OFFSET 0 |
| #define MV_SPI_TCSH_MASK (0x7F << MV_SPI_TCSH_OFFSET) |
| #define MV_SPI_TMISO_SAMPLE_OFFSET 6 |
| #define MV_SPI_TMISO_SAMPLE_MASK (0x3 << MV_SPI_TMISO_SAMPLE_OFFSET) |
| #define MV_SPI_TCS_SETUP_OFFSET 8 |
| #define MV_SPI_TCS_SETUP_MASK (0xF << MV_SPI_TCS_SETUP_OFFSET) |
| #define MV_SPI_TCS_HOLD_OFFSET 12 |
| #define MV_SPI_TCS_HOLD_MASK (0xF << MV_SPI_TCS_HOLD_OFFSET) |
| |
| |
| /* Serial Memory Interface Configuration Register Masks */ |
| #define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ |
| #define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ |
| #define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ |
| #define MV_SPI_DIRECT_READ_OFFSET 10 |
| #define MV_SPI_DIRECT_READ_MASK (1 << MV_SPI_DIRECT_READ_OFFSET) |
| #define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) |
| #define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) |
| #define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) |
| #define MV_SPI_CPOL_OFFSET 11 |
| #define MV_SPI_CPOL_MASK (0x1 << MV_SPI_CPOL_OFFSET) |
| #define MV_SPI_CPHA_OFFSET 12 |
| #define MV_SPI_CPHA_MASK (0x1 << MV_SPI_CPHA_OFFSET) |
| #define MV_SPI_TXLSBF_OFFSET 13 |
| #define MV_SPI_TXLSBF_MASK (0x1 << MV_SPI_TXLSBF_OFFSET) |
| #define MV_SPI_RXLSBF_OFFSET 14 |
| #define MV_SPI_RXLSBF_MASK (0x1 << MV_SPI_RXLSBF_OFFSET) |
| |
| #define MV_SPI_SPR_OFFSET 0 |
| #define MV_SPI_SPR_MASK (0xF << MV_SPI_SPR_OFFSET) |
| #define MV_SPI_SPPR_0_OFFSET 4 |
| #define MV_SPI_SPPR_0_MASK (0x1 << MV_SPI_SPPR_0_OFFSET) |
| #define MV_SPI_SPPR_HI_OFFSET 6 |
| #define MV_SPI_SPPR_HI_MASK (0x3 << MV_SPI_SPPR_HI_OFFSET) |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __INCmvSpiSpecH */ |
| |
