| /* |
| * (C) Copyright 2002 |
| * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| * Marius Groeger <mgroeger@sysgo.de> |
| * Gary Jennejohn <gj@denx.de> |
| * David Mueller <d.mueller@elsoft.ch> |
| * |
| * Modified for the friendly-arm SBC-2410X by |
| * (C) Copyright 2005 |
| * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> |
| * |
| * Configuation settings for the friendly-arm SBC-2410X board. |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #ifndef __CONFIG_H |
| #define __CONFIG_H |
| |
| /* |
| * If we are developing, we might want to start armboot from ram |
| * so we MUST NOT initialize critical regs like mem-timing ... |
| */ |
| #undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */ |
| |
| /* |
| * High Level Configuration Options |
| * (easy to change) |
| */ |
| #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ |
| #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ |
| #define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ |
| |
| /* input clock of PLL */ |
| #define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */ |
| |
| |
| #define USE_920T_MMU 1 |
| #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| |
| /* |
| * Size of malloc() pool |
| */ |
| #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
| #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| |
| /* |
| * Hardware drivers |
| */ |
| #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ |
| #define CS8900_BASE 0x19000300 |
| #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ |
| |
| /* |
| * select serial console configuration |
| */ |
| #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */ |
| |
| /************************************************************ |
| * RTC |
| ************************************************************/ |
| #define CONFIG_RTC_S3C24X0 1 |
| |
| /* allow to overwrite serial and ethaddr */ |
| #define CONFIG_ENV_OVERWRITE |
| |
| #define CONFIG_BAUDRATE 115200 |
| |
| /*********************************************************** |
| * Command definition |
| ***********************************************************/ |
| #define CONFIG_COMMANDS \ |
| (CONFIG_CMD_DFL | \ |
| CFG_CMD_CACHE | \ |
| /*CFG_CMD_NAND |*/ \ |
| /*CFG_CMD_EEPROM |*/ \ |
| /*CFG_CMD_I2C |*/ \ |
| /*CFG_CMD_USB |*/ \ |
| CFG_CMD_REGINFO | \ |
| CFG_CMD_DATE | \ |
| CFG_CMD_PING | \ |
| CFG_CMD_DHCP | \ |
| CFG_CMD_ELF) |
| |
| /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| #include <cmd_confdefs.h> |
| |
| #define CONFIG_BOOTDELAY 3 |
| #define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off" |
| #define CONFIG_ETHADDR 08:00:3e:26:0a:5b |
| #define CONFIG_NETMASK 255.255.255.0 |
| #define CONFIG_IPADDR 192.168.0.69 |
| #define CONFIG_SERVERIP 192.168.0.1 |
| /*#define CONFIG_BOOTFILE "elinos-lart" */ |
| #define CONFIG_BOOTCOMMAND "dhcp; bootm" |
| |
| #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
| /* what's this ? it's not used anywhere */ |
| #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
| #endif |
| |
| /* |
| * Miscellaneous configurable options |
| */ |
| #define CFG_LONGHELP /* undef to save memory */ |
| #define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */ |
| #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| #define CFG_MAXARGS 16 /* max number of command args */ |
| #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| |
| #define CFG_MEMTEST_START 0x30000000 /* memtest works on */ |
| #define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ |
| |
| #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
| |
| #define CFG_LOAD_ADDR 0x33000000 /* default load address */ |
| |
| /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ |
| /* it to wrap 100 times (total 1562500) to get 1 sec. */ |
| #define CFG_HZ 1562500 |
| |
| /* valid baudrates */ |
| #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| |
| /*----------------------------------------------------------------------- |
| * Stack sizes |
| * |
| * The stack sizes are set up in start.S using the settings below |
| */ |
| #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
| #ifdef CONFIG_USE_IRQ |
| #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
| #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
| #endif |
| |
| /*----------------------------------------------------------------------- |
| * Physical Memory Map |
| */ |
| #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ |
| #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
| |
| #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| |
| #define CFG_FLASH_BASE PHYS_FLASH_1 |
| |
| /*----------------------------------------------------------------------- |
| * FLASH and environment organization |
| */ |
| /* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */ |
| |
| #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ |
| |
| #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| |
| #ifdef CONFIG_AMD_LV800 |
| #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ |
| #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ |
| #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ |
| #endif |
| |
| #ifdef CONFIG_AMD_LV400 |
| #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ |
| #define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ |
| #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ |
| #endif |
| |
| /* timeout values are in ticks */ |
| #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ |
| #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ |
| |
| #define CFG_ENV_IS_IN_FLASH 1 |
| #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
| |
| /*----------------------------------------------------------------------- |
| * NAND flash settings |
| */ |
| #if (CONFIG_COMMANDS & CFG_CMD_NAND) |
| #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
| #define SECTORSIZE 512 |
| |
| #define ADDR_COLUMN 1 |
| #define ADDR_PAGE 2 |
| #define ADDR_COLUMN_PAGE 3 |
| |
| #define NAND_ChipID_UNKNOWN 0x00 |
| #define NAND_MAX_FLOORS 1 |
| #define NAND_MAX_CHIPS 1 |
| |
| #define NAND_WAIT_READY(nand) NF_WaitRB() |
| #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) |
| #define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) |
| #define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) |
| #define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) |
| #define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) |
| #define WRITE_NAND(d, adr) NF_Write(d) |
| #define READ_NAND(adr) NF_Read() |
| /* the following functions are NOP's because S3C24X0 handles this in hardware */ |
| #define NAND_CTL_CLRALE(nandptr) |
| #define NAND_CTL_SETALE(nandptr) |
| #define NAND_CTL_CLRCLE(nandptr) |
| #define NAND_CTL_SETCLE(nandptr) |
| /* #undef CONFIG_MTD_NAND_VERIFY_WRITE */ |
| #endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ |
| |
| #define CONFIG_SETUP_MEMORY_TAGS |
| #define CONFIG_INITRD_TAG |
| #define CONFIG_CMDLINE_TAG |
| |
| #define CFG_HUSH_PARSER |
| #define CFG_PROMPT_HUSH_PS2 "> " |
| |
| #define CONFIG_CMDLINE_EDITING |
| |
| #ifdef CONFIG_CMDLINE_EDITING |
| #undef CONFIG_AUTO_COMPLETE |
| #else |
| #define CONFIG_AUTO_COMPLETE |
| #endif |
| |
| #endif /* __CONFIG_H */ |
