ddr3libv2: bobk: WA to avoid DDR training stucking
Decrease max pooling number and add delay
before DUNIT access.
Change-Id: I624fb969c332e281e6990cc46eec465819496983
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/22467
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24146
Tested-by: Star_Automation <star@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
index 8bfb913..53bf008 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
@@ -306,8 +306,11 @@
MV_HWS_EdgeCompare trainEdgeCompare;
GT_U32 trainCsNum;
GT_U32 trainIfAcess, trainIfId, trainPupAccess;
-GT_U32 maxPollingForDone = 1000000;
-
+#ifdef CONFIG_BOBK
+GT_U32 maxPollingForDone = 1000; /*1000000; oferb */
+#else
+GT_U32 maxPollingForDone = 1000000;
+#endif
extern MV_HWS_RESULT trainingResult[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
extern AUTO_TUNE_STAGE trainingStage;
@@ -558,6 +561,10 @@
break;
}
}
+#ifdef CONFIG_BOBK
+ /* WA to avoid training stucking */
+ hwsOsExactDelayPtr((GT_U8)devNum, devNum, 50); /* 50 mSec */
+#endif
if (pollCnt == maxPollingForDone)
{
trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_TIMEOUT;
@@ -601,6 +608,10 @@
break;
}
}
+#ifdef CONFIG_BOBK
+ /* WA to avoid training stucking */
+ hwsOsExactDelayPtr((GT_U8)devNum, devNum, 50);
+#endif
if (pollCnt == maxPollingForDone)
{
trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_TIMEOUT;