ddrlibv2: Dynamic TIP mode configuration( Bump 0.18, 0.38)
In training code replaced ifdefs separated different TIP machine triggering with dynamic flags
Change-Id: I6cd1f56ee0e187f74caf0e5856e73648d148f3f4
Signed-off-by: Igor Petrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19039
Reviewed-on: http://vgitil04.il.marvell.com:8080/24118
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIp.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIp.h
index f3d6152..0e1da5d 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIp.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIp.h
@@ -52,9 +52,9 @@
#endif
#ifdef CONFIG_DDR4
-#define DDR3_TIP_VERSION_STRING "DDR4 Training Sequence - Ver TIP-0.19."
+#define DDR3_TIP_VERSION_STRING "DDR4 Training Sequence - Ver TIP-0.18."
#else
-#define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.39."
+#define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.38."
#endif
#define MAX_CS_NUM (4)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpEngine.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpEngine.h
index 7663517..458323e 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpEngine.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpEngine.h
@@ -121,21 +121,6 @@
);
/******************************************************************************
-* Name: ddr3TipLoadPatternToMemByCpu.
-* Desc: Load expected Pattern to external memory
-* Args:
-* Notes:
-* Returns: OK if success, other error code if fail.
-*/
-GT_STATUS ddr3TipLoadPatternToMemByCpu
-(
- GT_U32 devNum,
- MV_HWS_PATTERN pattern,
- GT_U32 offset
-);
-
-
-/******************************************************************************
* load pattern to memory using ODPG
*/
GT_STATUS ddr3TipLoadAllPatternToMem
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
index d04b3d8..0bacc9e 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
@@ -136,14 +136,14 @@
#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
#define ODPG_TRAINING_STATUS_REG (0x18488)
+#else
+#define ODPG_TRAINING_STATUS_REG (0x1030)
+#endif
#define ODPG_TRAINING_TRIGGER_REG (0x1030)
#define ODPG_STATUS_DONE_REG (0x16FC)
#define ODPG_ENABLE_REG (0x186D4)
#define ODPG_ENABLE_OFFS (0)
#define ODPG_DISABLE_OFFS (8)
-#else
-#define ODPG_TRAINING_STATUS_REG (0x1030)
-#endif
#define ODPG_TRAINING_CONTROL_REG (0x1034)
#define ODPG_OBJ1_OPCODE_REG (0x103C)
@@ -214,7 +214,8 @@
#define ODPG_BIST_DONE (0x16FC)
#endif
#define ODPG_BIST_DONE_BIT_OFFS (0)
-#define ODPG_BIST_DONE_BIT_VALUE (0)
+#define ODPG_BIST_DONE_BIT_VALUE_REV2 (1)
+#define ODPG_BIST_DONE_BIT_VALUE_REV3 (0)
#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
#define RESULT_CONTROL_BYTE_PUP_0_REG (0x1830)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
index 71d24ca..3b78111 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/mvDdrTrainingIpDb.h
@@ -71,7 +71,6 @@
typedef enum
{
MV_ATTR_TIP_REV,
- MV_ATTR_TRAINING_CONTROLLER,
MV_ATTR_PHY_EDGE,
MV_ATTR_OCTET_PER_INTERFACE,
MV_ATTR_PLL_BEFORE_INIT,
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 592c691..0241646 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -111,11 +111,6 @@
extern GT_U8 vrefCalibrationWA; /*1 means SSTL & POD gets the same Vref and a WA is needed*/
#endif
-#if defined (CONFIG_ALLEYCAT3)
-GT_U32 mvHwsmemSize[] = { ADDR_SIZE_512Mb, ADDR_SIZE_1Gb, ADDR_SIZE_2Gb, ADDR_SIZE_4Gb ,ADDR_SIZE_8Gb };
-#define MV_DEVICE_MAX_DRAM_ADDRESS_SIZE ADDR_SIZE_2Gb
-#endif
-
GT_U32 vrefInitialValue = 0x4;
GT_U32 ckDelay = MV_PARAMS_UNDEFINED;
@@ -168,7 +163,7 @@
extern GT_U16 rfcTable[];
extern GT_U32 speedBinTableTRc[];
extern GT_U32 speedBinTableTRcdTRp[];
-
+extern GT_U32 mvMemSize[];
/************************** pre-declarations ******************************/
static GT_STATUS ddr3TipDDR3Ddr3TrainingMainFlow
@@ -733,9 +728,7 @@
{
#ifdef STATIC_ALGO_SUPPORT
CHECK_STATUS(ddr3TipStaticInitController(devNum));
-#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ARMADA_39X)
CHECK_STATUS(ddr3TipStaticPhyInitController(devNum));
-#endif
#endif/*STATIC_ALGO_SUPPORT*/
}
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
@@ -3157,32 +3150,31 @@
GT_STATUS mvHwsDdr3CsBaseAdrCalc(GT_U32 interfaceId, GT_U32 uiCs, GT_U32 *csBaseAddr)
{
-
- GT_U32 uiCsMemSize = 0;
+ GT_U32 uiCsMemSize = 0;
#ifdef MV_DEVICE_MAX_DRAM_ADDRESS_SIZE
- GT_U32 physicalMemSize;
- GT_U32 maxMemSize = MV_DEVICE_MAX_DRAM_ADDRESS_SIZE;
+ GT_U32 physicalMemSize;
+ GT_U32 maxMemSize = MV_DEVICE_MAX_DRAM_ADDRESS_SIZE;
#endif
- if (mvHwsDdr3CalcMemCsSize(interfaceId,uiCs, &uiCsMemSize) != GT_OK)
- return GT_FAIL;
+ if (mvHwsDdr3CalcMemCsSize(interfaceId,uiCs, &uiCsMemSize) != GT_OK)
+ return GT_FAIL;
#ifdef MV_DEVICE_MAX_DRAM_ADDRESS_SIZE
- /* if number of address pins doesn't allow to use max mem size that is defined in topology
- mem size is defined by MV_DEVICE_MAX_DRAM_ADDRESS_SIZE*/
- physicalMemSize = mvHwsmemSize [topologyMap->interfaceParams[0].memorySize];
+ /* if number of address pins doesn't allow to use max mem size that is defined in topology
+ mem size is defined by MV_DEVICE_MAX_DRAM_ADDRESS_SIZE*/
+ physicalMemSize = mvMemSize[topologyMap->interfaceParams[0].memorySize];
- if (mvHwsDdr3GetDeviceWidth(uiCs) == 16)
- maxMemSize = MV_DEVICE_MAX_DRAM_ADDRESS_SIZE * 2; /* 16bit mem device can be twice more - no need in less significant pin*/
+ if (mvHwsDdr3GetDeviceWidth(uiCs) == 16)
+ maxMemSize = MV_DEVICE_MAX_DRAM_ADDRESS_SIZE * 2; /* 16bit mem device can be twice more - no need in less significant pin*/
- if (physicalMemSize > maxMemSize ){
- uiCsMemSize = maxMemSize * (mvHwsDdr3GetBusWidth() / mvHwsDdr3GetDeviceWidth(interfaceId)) ;
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("Updated Physical Mem size is from 0x%x to %x\n", physicalMemSize, MV_DEVICE_MAX_DRAM_ADDRESS_SIZE));
- }
+ if (physicalMemSize > maxMemSize ){
+ uiCsMemSize = maxMemSize * (mvHwsDdr3GetBusWidth() / mvHwsDdr3GetDeviceWidth(interfaceId)) ;
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("Updated Physical Mem size is from 0x%x to %x\n", physicalMemSize, MV_DEVICE_MAX_DRAM_ADDRESS_SIZE));
+ }
#endif
- /*calculate CS base addr */
- *csBaseAddr = ((uiCsMemSize) * uiCs) & 0xFFFF0000;
- return GT_OK;
+ /*calculate CS base addr */
+ *csBaseAddr = ((uiCsMemSize) * uiCs) & 0xFFFF0000;
+ return GT_OK;
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
index 119197b..ca8c251 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
@@ -291,7 +291,7 @@
)
{
- GT_U32 maskDqNumOfRegs, maskPupNumOfRegs, indexCnt,pollCnt, regData, pupId;
+ GT_U32 maskDqNumOfRegs, maskPupNumOfRegs, indexCnt,pollCnt, regData, pupId, triggerRegAddr;
GT_U32 txBurstSize;
GT_U32 delayBetweenBurst;
GT_U32 rdMode;
@@ -460,48 +460,47 @@
}
/*Start Training Trigger */
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceNum, ODPG_TRAINING_TRIGGER_REG, 1, 1));
-#else
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceNum, ODPG_TRAINING_STATUS_REG, 1, 1));
-#endif
+ triggerRegAddr = (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3)?(ODPG_TRAINING_TRIGGER_REG):(ODPG_TRAINING_STATUS_REG);
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceNum, triggerRegAddr, 1, 1));
+
/*wait for all RFU tests to finish (or timeout)*/
/*WA for 16 bit mode, more investigation needed*/
hwsOsExactDelayPtr((GT_U8)devNum, devNum, 1); /* 1 mSec */
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- /* Training "Done ?" */
- for(indexCnt=0; indexCnt < MAX_INTERFACE_NUM;indexCnt++)
+ /* Training "Done ?" for CPU contolled TIP*/
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3)
{
- if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, indexCnt) == 0)
- {
- continue;
- }
- if (interfaceMask & (1<<indexCnt))
- {
- /*need to check results for this Dunit */
- for(pollCnt=0;pollCnt < maxPollingForDone;pollCnt++)
- {
- CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, indexCnt, ODPG_TRAINING_STATUS_REG, ®Data, MASK_ALL_BITS));
- if ((regData & 0x2) != 0)
- {
- /*done */
- trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_SUCCESS;
- break;
- }
- }
- if (pollCnt == maxPollingForDone)
- {
- trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_TIMEOUT;
- }
- }
- /*Be sure that ODPG done*/
- CHECK_STATUS(isOdpgAccessDone(devNum, indexCnt));
- }
+ for(indexCnt=0; indexCnt < MAX_INTERFACE_NUM;indexCnt++)
+ {
+ if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, indexCnt) == 0)
+ {
+ continue;
+ }
+ if (interfaceMask & (1<<indexCnt))
+ {
+ /*need to check results for this Dunit */
+ for(pollCnt=0;pollCnt < maxPollingForDone;pollCnt++)
+ {
+ CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, indexCnt, ODPG_TRAINING_STATUS_REG, ®Data, MASK_ALL_BITS));
+ if ((regData & 0x2) != 0)
+ {
+ /*done */
+ trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_SUCCESS;
+ break;
+ }
+ }
+ if (pollCnt == maxPollingForDone)
+ {
+ trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_TIMEOUT;
+ }
+ }
+ /*Be sure that ODPG done*/
+ CHECK_STATUS(isOdpgAccessDone(devNum, indexCnt));
+ }
- /*Write ODPG done in Dunit*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_STATUS_DONE_REG, 0, 0x1));
-#endif
+ /*Write ODPG done in Dunit*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_STATUS_DONE_REG, 0, 0x1));
+ }
/*wait for all Dunit tests to finish (or timeout)*/
/* Training "Done ?" */
@@ -510,18 +509,14 @@
{
if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, indexCnt) == 0)
{
- continue;
+ continue;
}
if (interfaceMask & (1<<indexCnt))
{
/*need to check results for this Dunit */
for(pollCnt=0;pollCnt < maxPollingForDone;pollCnt++)
{
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, indexCnt, ODPG_TRAINING_TRIGGER_REG, readData, MASK_ALL_BITS));
-#else
- CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, indexCnt, ODPG_TRAINING_STATUS_REG, readData, MASK_ALL_BITS));
-#endif
+ CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, indexCnt, triggerRegAddr, readData, MASK_ALL_BITS));
regData = readData[indexCnt];
if ((regData & 0x2) != 0)
{
@@ -532,10 +527,10 @@
}
else
{
- trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_FAIL;
+ trainStatus[indexCnt] = MV_HWS_TrainingIpStatus_FAIL;
}
- break;
- }
+ break;
+ }
}
if (pollCnt == maxPollingForDone)
{
@@ -853,18 +848,16 @@
GT_U32 interfaceId
)
{
- GT_U32 pollCnt = 0, dataValue;
+ GT_U32 pollCnt = 0, dataValue, expectedVal;
GT_U32 readData[MAX_INTERFACE_NUM];
for (pollCnt = 0; pollCnt < MAX_POLLING_ITERATIONS ; pollCnt++)
{
CHECK_STATUS(mvHwsDdr3TipIFRead(devNum,ACCESS_TYPE_UNICAST, interfaceId, ODPG_BIST_DONE, readData, MASK_ALL_BITS));
dataValue = readData[interfaceId];
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- if (((dataValue >> ODPG_BIST_DONE_BIT_OFFS )& 0x1) == ODPG_BIST_DONE_BIT_VALUE)
-#else
- if ((dataValue & 0x1) == 0x1)
-#endif
+
+ expectedVal = (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) < MV_TIP_REV_3)?(ODPG_BIST_DONE_BIT_VALUE_REV2):(ODPG_BIST_DONE_BIT_VALUE_REV3);
+ if (((dataValue >> ODPG_BIST_DONE_BIT_OFFS )& 0x1) == expectedVal)
{
dataValue = dataValue & 0xfffffffe;
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_BIST_DONE, dataValue, MASK_ALL_BITS));
@@ -905,18 +898,20 @@
/* load pattern to ODPG */
ddr3TipLoadPatternToOdpg(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, pattern, patternTable[pattern].startAddr);
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- for(interfaceId = 0; interfaceId < MAX_INTERFACE_NUM ; interfaceId++)
- {
- if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, interfaceId) == 0)
- continue;
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x1498, 0x3 , 0xf));
- }
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3)
+ {
+ for(interfaceId = 0; interfaceId < MAX_INTERFACE_NUM ; interfaceId++)
+ {
+ if (IS_INTERFACE_ACTIVE(topologyMap->interfaceActiveMask, interfaceId) == 0)
+ continue;
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, SDRAM_ODT_CONTROL_HIGH_REG, 0x3 , 0xf));
+ }
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_ENABLE_REG, 0x1 << ODPG_ENABLE_OFFS, (0x1 << ODPG_ENABLE_OFFS)));
-#else
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_ENABLE_REG, 0x1 << ODPG_ENABLE_OFFS, (0x1 << ODPG_ENABLE_OFFS)));
+ }
+ else {
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CONTROL_REG, (GT_U32)(0x1 << 31), (GT_U32)(0x1 << 31)));
-#endif
+ }
hwsOsExactDelayPtr((GT_U8)devNum, devNum, 1); /* 1 mSec */
@@ -931,10 +926,10 @@
/* return to default */
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- /*disable odt0 for CS0 training - need to adjust for multy CS*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST,PARAM_NOT_CARE , 0x1498, 0x0 , 0xf));
-#endif
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3){
+ /*disable odt0 for CS0 training - need to adjust for multy CS*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST,PARAM_NOT_CARE , 0x1498, 0x0 , 0xf));
+ }
/* temporary added */
hwsOsExactDelayPtr((GT_U8)devNum, devNum, 1);
@@ -942,26 +937,6 @@
}
/*****************************************************************************
-Load specific pattern to memory using CPU
-******************************************************************************/
-GT_STATUS ddr3TipLoadPatternToMemByCpu
-(
- GT_U32 devNum,
- MV_HWS_PATTERN pattern,
- GT_U32 offset
-)
-{
- /* avoid warnings */
- devNum = devNum;
- pattern = pattern;
- offset = offset;
-
- /* eranba - TBD */
- return GT_OK;
-}
-
-
-/*****************************************************************************
Training search routine
******************************************************************************/
GT_STATUS ddr3TipIpTrainingWrapperInt
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
index d2af762..0bc14f3 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
@@ -235,38 +235,36 @@
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_REG, (1 << 24) | (1 << 20), (1 << 24) | (1 << 20)));
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_REG, (GT_U32)(1 << 31), (GT_U32)(1 << 31)));
/********* trigger training *******************/
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X) /* Trigger, poll on status and disable ODPG */
-/* CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1)); */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3){
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
- /*check for training done + results pass*/
- if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x2, 0x2, ODPG_TRAINING_STATUS_REG, MAX_POLLING_ITERATIONS) != GT_OK)
- {
- DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Done Failed\n"));
- return GT_FAIL;
- }
- for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
- {
- VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- CHECK_STATUS(mvHwsDdr3TipIFRead( devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_TRIGGER_REG, dataRead, 0x4));
- data = dataRead[interfaceId];
- if(data != 0x0) {
- DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Result Failed\n"));
- }
- }
- /*disable ODPG - Back to functional mode*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_ENABLE_REG, 0x1 << ODPG_DISABLE_OFFS, (0x1 << ODPG_DISABLE_OFFS)));
- if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x0, 0x1, ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != GT_OK)
+ /*check for training done + results pass*/
+ if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x2, 0x2, ODPG_TRAINING_STATUS_REG, MAX_POLLING_ITERATIONS) != GT_OK)
{
- DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("ODPG disable failed "));
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Done Failed\n"));
return GT_FAIL;
}
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
-#else /* Just trigger and go check for results */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
-#endif
-
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ CHECK_STATUS(mvHwsDdr3TipIFRead( devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_TRIGGER_REG, dataRead, 0x4));
+ data = dataRead[interfaceId];
+ if(data != 0x0) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Result Failed\n"));
+ }
+ }
+ /*disable ODPG - Back to functional mode*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_ENABLE_REG, 0x1 << ODPG_DISABLE_OFFS, (0x1 << ODPG_DISABLE_OFFS)));
+ if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x0, 0x1, ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != GT_OK)
+ {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("ODPG disable failed "));
+ return GT_FAIL;
+ }
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
+ }
+ else {
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
+ }
/************ double loop on bus, pup *********/
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
@@ -532,37 +530,36 @@
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_REG, (1 << 24) | (1 << 20), (1 << 24) | (1 << 20)));
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_REG, (GT_U32)(1 << 31), (GT_U32)(1 << 31)));
/********* trigger training *******************/
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) || defined(CONFIG_ALLEYCAT3) /* Trigger, poll on status and disable ODPG */
-/* CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1)); */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3){
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
- /*check for training done + results pass*/
- if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x2, 0x2, ODPG_TRAINING_STATUS_REG, MAX_POLLING_ITERATIONS) != GT_OK)
+ /*check for training done + results pass*/
+ if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x2, 0x2, ODPG_TRAINING_STATUS_REG, MAX_POLLING_ITERATIONS) != GT_OK)
+ {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Done Failed\n"));
+ return GT_FAIL;
+ }
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
- DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Done Failed\n"));
- return GT_FAIL;
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_TRIGGER_REG, dataRead, 0x4));
+ data = dataRead[interfaceId];
+ if(data != 0x0) {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Result Failed\n"));
+ }
}
- for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
- {
- VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_TRIGGER_REG, dataRead, 0x4));
- data = dataRead[interfaceId];
- if(data != 0x0) {
- DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("Training Result Failed\n"));
+ /*disable ODPG - Back to functional mode*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_ENABLE_REG, 0x1 << ODPG_DISABLE_OFFS, (0x1 << ODPG_DISABLE_OFFS)));
+ if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x0, 0x1, ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != GT_OK)
+ {
+ DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("ODPG disable failed "));
+ return GT_FAIL;
+ }
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
}
- }
- /*disable ODPG - Back to functional mode*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_ENABLE_REG, 0x1 << ODPG_DISABLE_OFFS, (0x1 << ODPG_DISABLE_OFFS)));
- if (ddr3TipIfPolling(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x0, 0x1, ODPG_ENABLE_REG, MAX_POLLING_ITERATIONS) != GT_OK)
- {
- DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("ODPG disable failed "));
- return GT_FAIL;
+ else {
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
}
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS));
-#else /* Just trigger and go check for results */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
-#endif
/************ double loop on bus, pup *********/
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
@@ -732,7 +729,7 @@
******************************************************************************/
GT_STATUS ddr3TipDynamicWriteLeveling(GT_U32 devNum)
{
- GT_U32 regData = 0, iter, interfaceId, busCnt;
+ GT_U32 regData = 0, iter, interfaceId, busCnt, triggerRegAddr;
GT_U32 csEnableRegVal[MAX_INTERFACE_NUM] = {0};
GT_U32 csMask[MAX_INTERFACE_NUM];
GT_U32 readDataSampleDelayVals[MAX_INTERFACE_NUM] = {0};
@@ -759,10 +756,11 @@
/* save current cs reg val */
CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, CS_ENABLE_REG, csEnableRegVal, MASK_ALL_BITS));
-#if !defined(CONFIG_ARMADA_38X) && !defined(CONFIG_ALLEYCAT3) && !defined(CONFIG_ARMADA_39X)
- /* enable multi cs */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, CS_ENABLE_REG, 0, (1 << 3)));
-#endif
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) < MV_TIP_REV_3)
+ {
+ /* enable multi cs */
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, CS_ENABLE_REG, 0, (1 << 3)));
+ }
}
/************************************************************************/
@@ -800,16 +798,17 @@
ddr3TipCalcCsMask(devNum, interfaceId, effective_cs, &csMask[interfaceId]);
}
- #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- /*Enable Output buffer to relevant CS - Q on , WL on*/
- CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS1_CMD, 0x80, 0x1080));
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3)
+ {
+ /*Enable Output buffer to relevant CS - Q on , WL on*/
+ CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS1_CMD, 0x80, 0x1080));
- /*enable odt for relevant CS*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x1498, (0x3<<(effective_cs*2)) , 0xf));
-
- #else
- CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS1_CMD, 0xC0, 0x12C4));
- #endif
+ /*enable odt for relevant CS*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x1498, (0x3<<(effective_cs*2)) , 0xf));
+ }
+ else {
+ CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask, MRS1_CMD, 0xC0, 0x12C4)); /*FIXME should be same as _CPU case*/
+ }
/************************************************************************/
/* Phase 2: Set training IP to write leveling mode */
@@ -819,14 +818,12 @@
/************************************************************************/
/* Phase 3: Trigger training */
/************************************************************************/
- #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_TRIGGER_REG, 0x1, 0x1));
- #else
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_TRAINING_STATUS_REG, 0x1, 0x1));
- #endif
+ triggerRegAddr = (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) < MV_TIP_REV_3)?(ODPG_TRAINING_STATUS_REG):(ODPG_TRAINING_TRIGGER_REG);
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, triggerRegAddr, 0x1, 0x1));
- #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3)
+ {
for(interfaceId = 0; interfaceId < MAX_INTERFACE_NUM; interfaceId++)
{
VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
@@ -836,7 +833,6 @@
{
DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("WL: DDR3 poll (4) failed (Data: 0x%x)\n", regData));
}
- #if !defined(CONFIG_ARMADA_38X) /*Disabled. JIRA #1498*/
else
{
CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_TRIGGER_REG, ®Data, (1 << 2)));
@@ -845,10 +841,8 @@
DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("WL: WL failed IF %d regData=0x%x\n",interfaceId,regData));
}
}
- #endif
}
- #endif
-
+ }
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
@@ -859,14 +853,12 @@
}
else
{
- #if !defined(CONFIG_ARMADA_38X) /*Disabled. JIRA #1498*/
CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_STATUS_REG, dataRead, (1 << 2)));
regData = dataRead[interfaceId];
if (regData != 0)
{
DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("WL: WL failed IF %d regData=0x%x\n",interfaceId,regData));
}
- #endif
/* check for training completion per bus */
for (busCnt=0; busCnt<octetsPerInterfaceNum; busCnt++)
@@ -921,11 +913,13 @@
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, WR_LEVELING_DQS_PATTERN_REG, 0x0, 0x1));
/* Update MRS 1 (WL off) */
- #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask0, MRS1_CMD , 0x1000, 0x1080)); // nklein 24.10.13
- #else
- CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask0, MRS1_CMD, 0x1000, 0x12C4));
- #endif
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3)
+ {
+ CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask0, MRS1_CMD , 0x1000, 0x1080));
+ }
+ else {
+ CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask0, MRS1_CMD, 0x1000, 0x12C4)); /*FIXME should be same as _CPU case*/
+ }
/* Update MRS 1 (return to functional mode - Q on , WL off) */
CHECK_STATUS(ddr3TipWriteMRSCmd(devNum, csMask0, MRS1_CMD, 0x0, 0x1080));
@@ -989,10 +983,10 @@
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, CS_ENABLE_REG, csEnableRegVal[interfaceId], MASK_ALL_BITS));
}
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_39X)
- /*disable modt0 for CS0 training - need to adjust for multy CS*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x1498, 0x0 , 0xf));
-#endif
+ if(ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3){
+ /*disable modt0 for CS0 training - need to adjust for multy CS*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x1498, 0x0 , 0xf));
+ }
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c
index 1346c54..dcfbbb9 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingStatic.c
@@ -368,7 +368,7 @@
GT_U32 indexCnt = 0;
DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("ddr3TipStaticInitController\n"));
-// for(indexCnt = 0; indexCnt < staticInitControllerConfigLen[devNum]; indexCnt++)
+
while(staticInitControllerConfig[devNum][indexCnt].regAddr != 0)
{
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
@@ -388,28 +388,12 @@
GT_U32 devNum
)
{
- //DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("CLK to CTRL skew\n"));
- //CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_UNICAST, 0x2, DDR_PHY_CONTROL, 0x90, 0x20da));
-
- //DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("CTRL Ref Delay\n")); /* motib does not efect*/
- //CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL, 0x1, 0xf));
-
- DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("Phy Init Controller 2\n"));
CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xA4, 0x3dfe));
-
- DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("Phy Init Controller 3\n"));
CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xA6, 0xCB2));
-
- DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("Phy Init Controller 4\n"));
CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xA9, 0));
-
- DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("Static Receiver Calibration\n"));
CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xD0, 0x1F));
-
- DEBUG_TRAINING_STATIC_IP(DEBUG_LEVEL_TRACE, ("Static V-REF Calibration\n"));
CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0xA8, 0x434));
-
return GT_OK;
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
index 6eb24b8..467ea1d 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Ac3.c
@@ -423,7 +423,7 @@
/*Set device attributes*/
ddr3TipDevAttrInit(devNum);
- ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_CPU);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_TIP_REV, MV_TIP_REV_3);
ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, numOfBusPerInterface);
ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
index c45f640..2687275 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
@@ -780,7 +780,7 @@
/*Set device attributes*/
ddr3TipDevAttrInit(devNum);
- ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_TIP);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_TIP_REV, MV_TIP_REV_2);
ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, BC2_NUMBER_OF_PUP);
ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
index b8de52f..81ab0a3 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3NP5.c
@@ -920,7 +920,7 @@
/*Set device attributes*/
ddr3TipDevAttrInit(devNum);
- ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_TIP);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_TIP_REV, MV_TIP_REV_1);
ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, numOfBusPerInterface);
ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index 28dac14..ca0263e 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -289,16 +289,6 @@
61
};
-#ifdef CONFIG_ARMADA_38X_Z1_OBSOLETE
-GT_U32 DQbitMap2Phypin[] =
-{
- 1, 0, 2, 3, 6, 7, 8, 9, //0
- 0, 1, 10, 3, 6, 7, 8, 9, //1
- 8, 1, 2, 0, 10, 9, 6, 7, //2
- 0, 1, 2, 3, 7, 8, 6, 10, //3
- 0, 1, 2, 3, 6, 7, 8, 9, //4
-};
-#else
GT_U32 DQbitMap2Phypin[] =
{
1, 0, 2, 6, 9, 8, 3, 7, //0
@@ -307,7 +297,6 @@
1, 0, 6, 2, 8, 3, 7, 9, //3
0, 1, 2, 9, 7, 8, 3, 6, //4
};
-#endif
/**********************************************************************************/
@@ -554,7 +543,7 @@
/*Set device attributes*/
ddr3TipDevAttrInit(devNum);
- ddr3TipDevAttrSet(devNum, MV_ATTR_TRAINING_CONTROLLER, MV_DDR_TRAINING_CONTROLLER_CPU);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_TIP_REV, MV_TIP_REV_4);
ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_POSITIVE);
ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, numOfBusPerInterface);
#ifdef CONFIG_ARMADA_39X
