commit ed77129544e05dfacb4d9c26d34bffa93f3cc5ee
author Konstantin Porotchkin <kostap@marvell.com> Fri Oct 02 12:09:37 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree 3723da7c30075f9861ac708197a0d8aa95c6b0a5
parent b81725e0308460bdd04f73d5e7c8bb80880abac2

fix: efuse: a38x, a39x: Fix the reserved rows invalidation pattern

- Change the pattern used for filling tester reserved efuse
  rows 0-23. Instead of using all zeros in bits[63:0] and bit[64]=1,
  set now bits[55:0] to ones, bits[63:56] to zeros and leave bit[64]=1.

- Using zeros as a content of efuse rows 0-23 causes HW engine make
  unnecessary changes in configuration of internal SRAM regions
  that belongs to SATA unit 0 port 0.
  These changes prevent SATA port 0 from a normal operation.

- Ensure that the reserved efuse row written only if not previously
  set by tester and skip rows already modified by tester.

Change-Id: I095ec4b050e4dfeb980f570e3749951a144adb29
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/23817
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>

board/mv_ebu/a38x/cmd_efuse.c

diff --git a/board/mv_ebu/a38x/cmd_efuse.c b/board/mv_ebu/a38x/cmd_efuse.c
index b70fb7d..fafeec0 100644
--- a/board/mv_ebu/a38x/cmd_efuse.c
+++ b/board/mv_ebu/a38x/cmd_efuse.c
@@ -251,13 +251,19 @@
 				val[2] = MV_EFUSE_REG_READ(EFUSE_BIT_64_ADDR(line));
 				DBPR("Read from %08X: [%08X]\n", EFUSE_BIT_64_ADDR(line), val[2]);
 
-				MV_EFUSE_REG_WRITE(EFUSE_BIT_31_0_ADDR(line), val[0]);
-				DBPR("Write to  %08X: [%08X]\n", EFUSE_BIT_31_0_ADDR(line), val[0]);
-				MV_EFUSE_REG_WRITE(EFUSE_BIT_63_32_ADDR(line), val[1]);
-				DBPR("Write to  %08X: [%08X]\n", EFUSE_BIT_63_32_ADDR(line), val[1]);
-				MV_EFUSE_REG_BIT_SET(EFUSE_BIT_64_ADDR(line), 0x1);
-				DBPR("Write to  %08X: [%08X]\n", EFUSE_BIT_64_ADDR(line), 0x1);
-				mvOsDelay(5);
+				if (val[2] == 0) { /* If the eFuse not yet burned by tester */
+					/* invalidate eFuse data before validating the row */
+					val[0] = 0xFFFFFFFF;
+					val[1] = 0x00FFFFFF;
+
+					MV_EFUSE_REG_WRITE(EFUSE_BIT_31_0_ADDR(line), val[0]);
+					DBPR("Write to  %08X: [%08X]\n", EFUSE_BIT_31_0_ADDR(line), val[0]);
+					MV_EFUSE_REG_WRITE(EFUSE_BIT_63_32_ADDR(line), val[1]);
+					DBPR("Write to  %08X: [%08X]\n", EFUSE_BIT_63_32_ADDR(line), val[1]);
+					MV_EFUSE_REG_BIT_SET(EFUSE_BIT_64_ADDR(line), 0x1);
+					DBPR("Write to  %08X: [%08X]\n", EFUSE_BIT_64_ADDR(line), 0x1);
+					mvOsDelay(5);
+				}
 			}
 		}