Add preliminary support for Caelum DB.
- Update all Bobk structure to Bobk_Cetus, add new definition for Bobk_Caelum
- Update the name of customer boards of BOBK.
bobk_customer0-->bobk_cetus_customer0,
bobk_customer1-->bobk_caelun_customer1
- The devID of Cealum is 0xBC00, and Cetus is 0xBE00, the higher 6bits
are the same, update flavor mask to 0x3FF, for BC2 and AC3 flavors,
the higher 6bits are also the same, so can work normally after update.
- Update the BOBK family ID to 0xBC00 since we use 0x3FF as mask
- Add BobK device matrix, also update for common/15t1,common/15t2,LK2.6 & LK3.4
- Add separate definition of CoreClock and CPU/DDR freq for Cetus/Caelum.
distinguish the definition with board ID in runtime.
- Add Hardware service topology for Caelum (same with Cetus)
Change-Id: If419da6baaa002843c31fdd0d7ec0a3d55671ba8
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/22934
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/board/mv_ebu/common/common/mvDeviceId.h b/board/mv_ebu/common/common/mvDeviceId.h
index 58f7726..f9bddea 100644
--- a/board/mv_ebu/common/common/mvDeviceId.h
+++ b/board/mv_ebu/common/common/mvDeviceId.h
@@ -442,10 +442,14 @@
MV_BOBCAT2_B0_NAME,\
}
- /* BobK Family */
-#define MV_BOBK_DEV_ID 0xBE00
+/* BobK Family */
+#define MV_BOBK_DEV_ID 0xBC00
- /* BobK Revisions */
+/* BobK deivces matrix */
+#define MV_BOBK_CETUS_98DX4235_DEV_ID 0xBC00
+#define MV_BOBK_CAELUM_98DX4203_DEV_ID 0xBE00
+
+/* BobK Revisions */
#define MV_BOBK_A0_ID 0x0
#define MV_BOBK_A0_NAME "A0"
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
index 7d290fe..9cd7b33 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
@@ -629,7 +629,8 @@
MV_U32 idx;
MV_U32 freq_tbl_bc2[] = MV_CORE_CLK_TBL_BC2;
MV_U32 freq_tbl_ac3[] = MV_CORE_CLK_TBL_AC3;
- MV_U32 freq_tbl_bobk[] = MV_CORE_CLK_TBL_BOBK;
+ MV_U32 freq_tbl_bobk_cetus[] = MV_CORE_CLK_TBL_BOBK_CETUS;
+ MV_U32 freq_tbl_bobk_caelum[] = MV_CORE_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
if (family == MV_78460_DEV_ID)
@@ -643,9 +644,20 @@
return freq_tbl_bc2[idx] * 1000000;
else if (family == MV_ALLEYCAT3_DEV_ID)
return freq_tbl_ac3[idx] * 1000000;
- else if (family == MV_BOBK_DEV_ID)
- return freq_tbl_bobk[idx] * 1000000;
- else
+ else if (family == MV_BOBK_DEV_ID) {
+ /* BobK family has two different flavors(Cetus/Caelum) with different settings */
+ switch (mvCtrlModelGet() & ~BOBK_FLAVOR_MASK) {
+ case MV_BOBK_CETUS_98DX4235_DEV_ID:
+ return freq_tbl_bobk_cetus[idx] * 1000000;
+ break;
+ case MV_BOBK_CAELUM_98DX4203_DEV_ID:
+ return freq_tbl_bobk_caelum[idx] * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown Device ID %d, CORE freq get failed\n", mvCtrlModelGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
}
@@ -1382,7 +1394,7 @@
gBoardId = BC2_CUSTOMER_BOARD_ID0;
board = customerBC2BoardInfoTbl[gBoardId];
#else
- gBoardId = BOBK_CUSTOMER_BOARD_ID0;
+ gBoardId = BOBK_CETUS_CUSTOMER_BOARD_ID0;
board = customerBOBKBoardInfoTbl[gBoardId];
#endif
mvOsPrintf("Applying default Customer board ID (%d: %s)\n", gBoardId, board->boardName);
@@ -1428,9 +1440,9 @@
#endif
#else /* BOBK */
#ifdef CONFIG_CUSTOMER_BOARD_0
- gBoardId = BOBK_CUSTOMER_BOARD_ID0;
+ gBoardId = BOBK_CETUS_CUSTOMER_BOARD_ID0;
#elif CONFIG_CUSTOMER_BOARD_1
- gBoardId = BOBK_CUSTOMER_BOARD_ID1;
+ gBoardId = BOBK_CAELUM_CUSTOMER_BOARD_ID1;
#endif
#endif
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
index dd3a549..0e204a9 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.c
@@ -184,17 +184,17 @@
};
/*******************************************************************************
- BobK board - Based on BOBK-DB-98DX4235
+ BobK Cetus customer board - Based on BOBK-CETUS-DB-98DX4235-12XG
*******************************************************************************/
-#define BOBK_CUSTOMER_0_BOARD_NAND_READ_PARAMS 0x000C0282
-#define BOBK_CUSTOMER_0_BOARD_NAND_WRITE_PARAMS 0x00010305
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NAND_READ_PARAMS 0x000C0282
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NAND_WRITE_PARAMS 0x00010305
/*NAND care support for small page chips*/
-#define BOBK_CUSTOMER_0_BOARD_NAND_CONTROL 0x01c00543
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NAND_CONTROL 0x01c00543
-#define BOBK_CUSTOMER_0_BOARD_NOR_READ_PARAMS 0x403E07CF
-#define BOBK_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS 0x000F0F0F
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NOR_READ_PARAMS 0x403E07CF
+#define BOBK_CETUS_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS 0x000F0F0F
-MV_BOARD_TWSI_INFO bobk_customer_board_0_InfoBoardTwsiDev[] = {
+MV_BOARD_TWSI_INFO bobk_cetus_customer_board_0_InfoBoardTwsiDev[] = {
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
{BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
@@ -208,19 +208,19 @@
{BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
};
-MV_BOARD_MAC_INFO bobk_customer_board_0_InfoBoardMacInfo[] = {
+MV_BOARD_MAC_INFO bobk_cetus_customer_board_0_InfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
{BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
{BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
};
-MV_BOARD_MODULE_TYPE_INFO bobk_customer_board_0_InfoBoardModTypeInfo[] = {
+MV_BOARD_MODULE_TYPE_INFO bobk_cetus_customer_board_0_InfoBoardModTypeInfo[] = {
{
.boardMppMod = MV_BOARD_AUTO,
}
};
-MV_DEV_CS_INFO bobk_customer_board_0_InfoBoardDeCsInfo[] = {
+MV_DEV_CS_INFO bobk_cetus_customer_board_0_InfoBoardDeCsInfo[] = {
/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
#if defined(MV_INCLUDE_SPI)
{SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
@@ -233,31 +233,31 @@
#endif
};
-MV_BOARD_MPP_INFO bobk_customer_board_0_InfoBoardMppConfigValue[] = {
+MV_BOARD_MPP_INFO bobk_cetus_customer_board_0_InfoBoardMppConfigValue[] = {
{ {
- BOBK_CUSTOMER_0_MPP0_7,
- BOBK_CUSTOMER_0_MPP8_15,
- BOBK_CUSTOMER_0_MPP16_23,
- BOBK_CUSTOMER_0_MPP24_31,
- BOBK_CUSTOMER_0_MPP32_39,
+ BOBK_CETUS_CUSTOMER_0_MPP0_7,
+ BOBK_CETUS_CUSTOMER_0_MPP8_15,
+ BOBK_CETUS_CUSTOMER_0_MPP16_23,
+ BOBK_CETUS_CUSTOMER_0_MPP24_31,
+ BOBK_CETUS_CUSTOMER_0_MPP32_39,
} },
};
-MV_BOARD_INFO bobk_customer_board_0_Info = {
- .boardName = "BOBK-Customer-Board-0",
- .numBoardMppTypeValue = ARRSZ(bobk_customer_board_0_InfoBoardModTypeInfo),
- .pBoardModTypeValue = bobk_customer_board_0_InfoBoardModTypeInfo,
- .numBoardMppConfigValue = ARRSZ(bobk_customer_board_0_InfoBoardMppConfigValue),
- .pBoardMppConfigValue = bobk_customer_board_0_InfoBoardMppConfigValue,
+MV_BOARD_INFO bobk_cetus_customer_board_0_Info = {
+ .boardName = "BOBK-Cetus-Customer-Board-0",
+ .numBoardMppTypeValue = ARRSZ(bobk_cetus_customer_board_0_InfoBoardModTypeInfo),
+ .pBoardModTypeValue = bobk_cetus_customer_board_0_InfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(bobk_cetus_customer_board_0_InfoBoardMppConfigValue),
+ .pBoardMppConfigValue = bobk_cetus_customer_board_0_InfoBoardMppConfigValue,
.intsGppMaskLow = 0,
.intsGppMaskMid = 0,
.intsGppMaskHigh = 0,
- .numBoardDeviceIf = ARRSZ(bobk_customer_board_0_InfoBoardDeCsInfo),
- .pDevCsInfo = bobk_customer_board_0_InfoBoardDeCsInfo,
- .numBoardTwsiDev = ARRSZ(bobk_customer_board_0_InfoBoardTwsiDev),
- .pBoardTwsiDev = bobk_customer_board_0_InfoBoardTwsiDev,
- .numBoardMacInfo = ARRSZ(bobk_customer_board_0_InfoBoardMacInfo),
- .pBoardMacInfo = bobk_customer_board_0_InfoBoardMacInfo,
+ .numBoardDeviceIf = ARRSZ(bobk_cetus_customer_board_0_InfoBoardDeCsInfo),
+ .pDevCsInfo = bobk_cetus_customer_board_0_InfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(bobk_cetus_customer_board_0_InfoBoardTwsiDev),
+ .pBoardTwsiDev = bobk_cetus_customer_board_0_InfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(bobk_cetus_customer_board_0_InfoBoardMacInfo),
+ .pBoardMacInfo = bobk_cetus_customer_board_0_InfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = NULL,
.activeLedsNumber = 0,
@@ -265,14 +265,14 @@
.ledsPolarity = 0,
/* GPP values */
- .gppOutEnValLow = BOBK_CUSTOMER_0_GPP_OUT_ENA_LOW,
- .gppOutEnValMid = BOBK_CUSTOMER_0_GPP_OUT_ENA_MID,
+ .gppOutEnValLow = BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_MID,
.gppOutEnValHigh = 0,
- .gppOutValLow = BOBK_CUSTOMER_0_GPP_OUT_VAL_LOW,
- .gppOutValMid = BOBK_CUSTOMER_0_GPP_OUT_VAL_MID,
+ .gppOutValLow = BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_LOW,
+ .gppOutValMid = BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_MID,
.gppOutValHigh = 0,
- .gppPolarityValLow = BOBK_CUSTOMER_0_GPP_POL_LOW,
- .gppPolarityValMid = BOBK_CUSTOMER_0_GPP_POL_MID,
+ .gppPolarityValLow = BOBK_CETUS_CUSTOMER_0_GPP_POL_LOW,
+ .gppPolarityValMid = BOBK_CETUS_CUSTOMER_0_GPP_POL_MID,
.gppPolarityValHigh = 0,
/* External Switch Configuration */
@@ -280,20 +280,129 @@
.switchInfoNum = 0,
/* NAND init params */
- .nandFlashReadParams = BOBK_CUSTOMER_0_BOARD_NAND_READ_PARAMS,
- .nandFlashWriteParams = BOBK_CUSTOMER_0_BOARD_NAND_WRITE_PARAMS,
- .nandFlashControl = BOBK_CUSTOMER_0_BOARD_NAND_CONTROL,
+ .nandFlashReadParams = BOBK_CETUS_CUSTOMER_0_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = BOBK_CETUS_CUSTOMER_0_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = BOBK_CETUS_CUSTOMER_0_BOARD_NAND_CONTROL,
/* NOR init params */
- .norFlashReadParams = BOBK_CUSTOMER_0_BOARD_NOR_READ_PARAMS,
- .norFlashWriteParams = BOBK_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS,
+ .norFlashReadParams = BOBK_CETUS_CUSTOMER_0_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = BOBK_CETUS_CUSTOMER_0_BOARD_NOR_WRITE_PARAMS,
.isSmiExternalPp = MV_TRUE,
.smiExternalPpIndex = 0,
.isSdMmcConnected = MV_TRUE
};
+/*******************************************************************************
+ BobK Caelum customer board - Based on BOBK-CAELUM-DB-98DX4203-12XG
+*******************************************************************************/
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_READ_PARAMS 0x000C0282
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_WRITE_PARAMS 0x00010305
+/*NAND care support for small page chips*/
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_CONTROL 0x01c00543
+
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_READ_PARAMS 0x403E07CF
+#define BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_WRITE_PARAMS 0x000F0F0F
+
+MV_BOARD_TWSI_INFO bobk_caelum_customer_board_1_InfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, /* SatR bios 0 */
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, /* SatR bios 1 */
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, /* SatR bios 2 */
+ {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT}, /* SatR bios 3 */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Init EPROM */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x70, ADDR7_BIT}, /* PCA9548 I2C mux 0 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x71, ADDR7_BIT}, /* PCA9548 I2C mux 1 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
+};
+
+MV_BOARD_MAC_INFO bobk_caelum_customer_board_1_InfoBoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO bobk_caelum_customer_board_1_InfoBoardModTypeInfo[] = {
+ {
+ .boardMppMod = MV_BOARD_AUTO,
+ }
+};
+
+MV_DEV_CS_INFO bobk_caelum_customer_board_1_InfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO bobk_caelum_customer_board_1_InfoBoardMppConfigValue[] = {
+ { {
+ BOBK_CAELUM_CUSTOMER_1_MPP0_7,
+ BOBK_CAELUM_CUSTOMER_1_MPP8_15,
+ BOBK_CAELUM_CUSTOMER_1_MPP16_23,
+ BOBK_CAELUM_CUSTOMER_1_MPP24_31,
+ BOBK_CAELUM_CUSTOMER_1_MPP32_39,
+ } },
+};
+
+MV_BOARD_INFO bobk_caelum_customer_board_1_Info = {
+ .boardName = "BOBK-Caelum-Customer-Board-1",
+ .numBoardMppTypeValue = ARRSZ(bobk_caelum_customer_board_1_InfoBoardModTypeInfo),
+ .pBoardModTypeValue = bobk_caelum_customer_board_1_InfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(bobk_caelum_customer_board_1_InfoBoardMppConfigValue),
+ .pBoardMppConfigValue = bobk_caelum_customer_board_1_InfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(bobk_caelum_customer_board_1_InfoBoardDeCsInfo),
+ .pDevCsInfo = bobk_caelum_customer_board_1_InfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(bobk_caelum_customer_board_1_InfoBoardTwsiDev),
+ .pBoardTwsiDev = bobk_caelum_customer_board_1_InfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(bobk_caelum_customer_board_1_InfoBoardMacInfo),
+ .pBoardMacInfo = bobk_caelum_customer_board_1_InfoBoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = NULL,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = 0,
+ .gppOutValLow = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_LOW,
+ .gppOutValMid = BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_MID,
+ .gppOutValHigh = 0,
+ .gppPolarityValLow = BOBK_CAELUM_CUSTOMER_1_GPP_POL_LOW,
+ .gppPolarityValMid = BOBK_CAELUM_CUSTOMER_1_GPP_POL_MID,
+ .gppPolarityValHigh = 0,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = BOBK_CAELUM_CUSTOMER_1_BOARD_NAND_CONTROL,
+ /* NOR init params */
+ .norFlashReadParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = BOBK_CAELUM_CUSTOMER_1_BOARD_NOR_WRITE_PARAMS,
+ .isSmiExternalPp = MV_TRUE,
+ .smiExternalPpIndex = 1,
+ .isSdMmcConnected = MV_TRUE
+};
+
+
MV_BOARD_INFO *customerBOBKBoardInfoTbl[] = {
- &bobk_customer_board_0_Info,
- &bobk_customer_board_0_Info,
+ &bobk_cetus_customer_board_0_Info,
+ &bobk_caelum_customer_board_1_Info,
};
/*******************************************************************************
@@ -704,9 +813,9 @@
};
/*********************************************************************************/
-/*******************************/
-/* BOBK-DB-98DX4235-12XG BOARD */
-/*******************************/
+/*************************************/
+/* BOBK-CETUS-DB-98DX4235-12XG BOARD */
+/*************************************/
#define DB_DX_BOBK_BOARD_NAND_READ_PARAMS 0x000C0282
#define DB_DX_BOBK_BOARD_NAND_WRITE_PARAMS 0x00010305
/*NAND care support for small page chips*/
@@ -716,7 +825,7 @@
#define DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS 0x000F0F0F
/* TODO */
-MV_BOARD_TWSI_INFO db_dx_bobkInfoBoardTwsiDev[] = {
+MV_BOARD_TWSI_INFO db_dx_bobkCetusInfoBoardTwsiDev[] = {
/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
{BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
{BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
@@ -730,20 +839,20 @@
{BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
};
-MV_BOARD_MAC_INFO db_dx_bobkInfoBoardMacInfo[] = {
+MV_BOARD_MAC_INFO db_dx_bobkCetusInfoBoardMacInfo[] = {
/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
{BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
{BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
};
-MV_BOARD_MODULE_TYPE_INFO db_dx_bobkInfoBoardModTypeInfo[] = {
+MV_BOARD_MODULE_TYPE_INFO db_dx_bobkCetusInfoBoardModTypeInfo[] = {
{
.boardMppMod = MV_BOARD_AUTO,
}
};
/* TO DE */
-MV_DEV_CS_INFO db_dx_bobkInfoBoardDeCsInfo[] = {
+MV_DEV_CS_INFO db_dx_bobkCetusInfoBoardDeCsInfo[] = {
/*{deviceCS, params, devType, devWidth, busWidth }*/
#if defined(MV_INCLUDE_SPI)
{SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
@@ -756,36 +865,36 @@
#endif
};
-MV_BOARD_MPP_INFO db_dx_bobkInfoBoardMppConfigValue[] = {
+MV_BOARD_MPP_INFO db_dx_bobkCetusInfoBoardMppConfigValue[] = {
{ {
#if defined(MV_INCLUDE_NOR)
- DB_DX_BOBK_NOR_MPP0_7,
- DB_DX_BOBK_NOR_MPP8_15,
+ DB_DX_BOBK_CETUS_NOR_MPP0_7,
+ DB_DX_BOBK_CETUS_NOR_MPP8_15,
#else
- DB_DX_BOBK_MPP0_7,
- DB_DX_BOBK_MPP8_15,
+ DB_DX_BOBK_CETUS_MPP0_7,
+ DB_DX_BOBK_CETUS_MPP8_15,
#endif
- DB_DX_BOBK_MPP16_23,
- DB_DX_BOBK_MPP24_31,
- DB_DX_BOBK_MPP32_39,
+ DB_DX_BOBK_CETUS_MPP16_23,
+ DB_DX_BOBK_CETUS_MPP24_31,
+ DB_DX_BOBK_CETUS_MPP32_39,
} },
};
-MV_BOARD_INFO db_dx_bobkInfo = {
+MV_BOARD_INFO db_dx_bobkCetusInfo = {
.boardName = "DB-98DX4235-12XG",
- .numBoardMppTypeValue = ARRSZ(db_dx_bobkInfoBoardModTypeInfo),
- .pBoardModTypeValue = db_dx_bobkInfoBoardModTypeInfo,
- .numBoardMppConfigValue = ARRSZ(db_dx_bobkInfoBoardMppConfigValue),
- .pBoardMppConfigValue = db_dx_bobkInfoBoardMppConfigValue,
+ .numBoardMppTypeValue = ARRSZ(db_dx_bobkCetusInfoBoardModTypeInfo),
+ .pBoardModTypeValue = db_dx_bobkCetusInfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(db_dx_bobkCetusInfoBoardMppConfigValue),
+ .pBoardMppConfigValue = db_dx_bobkCetusInfoBoardMppConfigValue,
.intsGppMaskLow = 0,
.intsGppMaskMid = 0,
.intsGppMaskHigh = 0,
- .numBoardDeviceIf = ARRSZ(db_dx_bobkInfoBoardDeCsInfo),
- .pDevCsInfo = db_dx_bobkInfoBoardDeCsInfo,
- .numBoardTwsiDev = ARRSZ(db_dx_bobkInfoBoardTwsiDev),
- .pBoardTwsiDev = db_dx_bobkInfoBoardTwsiDev,
- .numBoardMacInfo = ARRSZ(db_dx_bobkInfoBoardMacInfo),
- .pBoardMacInfo = db_dx_bobkInfoBoardMacInfo,
+ .numBoardDeviceIf = ARRSZ(db_dx_bobkCetusInfoBoardDeCsInfo),
+ .pDevCsInfo = db_dx_bobkCetusInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(db_dx_bobkCetusInfoBoardTwsiDev),
+ .pBoardTwsiDev = db_dx_bobkCetusInfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(db_dx_bobkCetusInfoBoardMacInfo),
+ .pBoardMacInfo = db_dx_bobkCetusInfoBoardMacInfo,
.numBoardGppInfo = 0,
.pBoardGppInfo = NULL,
.activeLedsNumber = 0,
@@ -793,14 +902,14 @@
.ledsPolarity = 0,
/* GPP values */
- .gppOutEnValLow = DB_DX_BOBK_GPP_OUT_ENA_LOW,
- .gppOutEnValMid = DB_DX_BOBK_GPP_OUT_ENA_MID,
+ .gppOutEnValLow = DB_DX_BOBK_CETUS_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = DB_DX_BOBK_CETUS_GPP_OUT_ENA_MID,
.gppOutEnValHigh = 0,
- .gppOutValLow = DB_DX_BOBK_GPP_OUT_VAL_LOW,
- .gppOutValMid = DB_DX_BOBK_GPP_OUT_VAL_MID,
+ .gppOutValLow = DB_DX_BOBK_CETUS_GPP_OUT_VAL_LOW,
+ .gppOutValMid = DB_DX_BOBK_CETUS_GPP_OUT_VAL_MID,
.gppOutValHigh = 0,
- .gppPolarityValLow = DB_DX_BOBK_GPP_POL_LOW,
- .gppPolarityValMid = DB_DX_BOBK_GPP_POL_MID,
+ .gppPolarityValLow = DB_DX_BOBK_CETUS_GPP_POL_LOW,
+ .gppPolarityValMid = DB_DX_BOBK_CETUS_GPP_POL_MID,
.gppPolarityValHigh = 0,
/* External Switch Configuration */
@@ -816,7 +925,116 @@
.norFlashWriteParams = DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS,
.isSmiExternalPp = MV_TRUE,
.smiExternalPpIndex = 0,
- .modelName = "BobK Development Board",
+ .modelName = "BobK Cetus Development Board",
+ .isSdMmcConnected = MV_TRUE
+};
+
+/*********************************************************************************/
+/**************************************/
+/* BOBK-CAELUM-DB-98DX4203-12XG BOARD */
+/**************************************/
+
+MV_BOARD_TWSI_INFO db_dx_bobkCaelumInfoBoardTwsiDev[] = {
+/* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */
+ {BOARD_DEV_TWSI_PLD, 0x18, ADDR7_BIT}, /* Access to control PLD reg file */
+ {BOARD_DEV_TWSI_ZARLINK, 0x1B, ADDR7_BIT}, /* Access to Zarlink */
+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, /* SatR bios 0 */
+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, /* SatR bios 1 */
+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, /* SatR bios 2 */
+ {BOARD_DEV_TWSI_SATR, 0x4F, ADDR7_BIT}, /* SatR bios 3 */
+ {BOARD_DEV_TWSI_INIT_EPROM, 0x50, ADDR7_BIT}, /* Serial Init EPROM */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x70, ADDR7_BIT}, /* PCA9548 I2C mux 0 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x71, ADDR7_BIT}, /* PCA9548 I2C mux 1 */
+ {BOARD_DEV_TWSI_PCA9548_IO_MUX, 0x75, ADDR7_BIT} /* PCA9548 I2C mux 2 */
+};
+
+MV_BOARD_MAC_INFO db_dx_bobkCaelumInfoBoardMacInfo[] = {
+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr , MV_32 boardEthSmiAddr0;}} */
+ {BOARD_MAC_SPEED_AUTO, -1, -1, MV_FALSE},
+ {BOARD_MAC_SPEED_AUTO, 0x0, 0x0, MV_TRUE},
+};
+
+MV_BOARD_MODULE_TYPE_INFO db_dx_bobkCaelumInfoBoardModTypeInfo[] = {
+ {
+ .boardMppMod = MV_BOARD_AUTO,
+ }
+};
+
+/* TO DE */
+MV_DEV_CS_INFO db_dx_bobkCaelumInfoBoardDeCsInfo[] = {
+ /*{deviceCS, params, devType, devWidth, busWidth }*/
+#if defined(MV_INCLUDE_SPI)
+ {SPI_CS0, N_A, BOARD_DEV_SPI_FLASH, 8, 8, 0, MV_TRUE}, /* SPI DEV */
+#endif
+#if defined(MV_INCLUDE_NOR)
+ {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16, 16, 0, MV_TRUE} /* NOR DEV */
+#endif
+#if defined(MV_INCLUDE_NAND)
+ {DEVICE_CS0, N_A, BOARD_DEV_NAND_FLASH, 8, 8, 0, MV_TRUE} /* NAND DEV */
+#endif
+};
+
+MV_BOARD_MPP_INFO db_dx_bobkCaelumInfoBoardMppConfigValue[] = {
+ { {
+#if defined(MV_INCLUDE_NOR)
+ DB_DX_BOBK_CAELUM_NOR_MPP0_7,
+ DB_DX_BOBK_CAELUM_NOR_MPP8_15,
+#else
+ DB_DX_BOBK_CAELUM_MPP0_7,
+ DB_DX_BOBK_CAELUM_MPP8_15,
+#endif
+ DB_DX_BOBK_CAELUM_MPP16_23,
+ DB_DX_BOBK_CAELUM_MPP24_31,
+ DB_DX_BOBK_CAELUM_MPP32_39,
+ } },
+};
+
+MV_BOARD_INFO db_dx_bobkCaelumInfo = {
+ .boardName = "DB-98DX4203-12XG",
+ .numBoardMppTypeValue = ARRSZ(db_dx_bobkCaelumInfoBoardModTypeInfo),
+ .pBoardModTypeValue = db_dx_bobkCaelumInfoBoardModTypeInfo,
+ .numBoardMppConfigValue = ARRSZ(db_dx_bobkCaelumInfoBoardMppConfigValue),
+ .pBoardMppConfigValue = db_dx_bobkCaelumInfoBoardMppConfigValue,
+ .intsGppMaskLow = 0,
+ .intsGppMaskMid = 0,
+ .intsGppMaskHigh = 0,
+ .numBoardDeviceIf = ARRSZ(db_dx_bobkCaelumInfoBoardDeCsInfo),
+ .pDevCsInfo = db_dx_bobkCaelumInfoBoardDeCsInfo,
+ .numBoardTwsiDev = ARRSZ(db_dx_bobkCaelumInfoBoardTwsiDev),
+ .pBoardTwsiDev = db_dx_bobkCaelumInfoBoardTwsiDev,
+ .numBoardMacInfo = ARRSZ(db_dx_bobkCaelumInfoBoardMacInfo),
+ .pBoardMacInfo = db_dx_bobkCaelumInfoBoardMacInfo,
+ .numBoardGppInfo = 0,
+ .pBoardGppInfo = NULL,
+ .activeLedsNumber = 0,
+ .pLedGppPin = NULL,
+ .ledsPolarity = 0,
+
+ /* GPP values */
+ .gppOutEnValLow = DB_DX_BOBK_CAELUM_GPP_OUT_ENA_LOW,
+ .gppOutEnValMid = DB_DX_BOBK_CAELUM_GPP_OUT_ENA_MID,
+ .gppOutEnValHigh = 0,
+ .gppOutValLow = DB_DX_BOBK_CAELUM_GPP_OUT_VAL_LOW,
+ .gppOutValMid = DB_DX_BOBK_CAELUM_GPP_OUT_VAL_MID,
+ .gppOutValHigh = 0,
+ .gppPolarityValLow = DB_DX_BOBK_CAELUM_GPP_POL_LOW,
+ .gppPolarityValMid = DB_DX_BOBK_CAELUM_GPP_POL_MID,
+ .gppPolarityValHigh = 0,
+
+ /* External Switch Configuration */
+ .pSwitchInfo = NULL,
+ .switchInfoNum = 0,
+
+ /* NAND init params */
+ .nandFlashReadParams = DB_DX_BOBK_BOARD_NAND_READ_PARAMS,
+ .nandFlashWriteParams = DB_DX_BOBK_BOARD_NAND_WRITE_PARAMS,
+ .nandFlashControl = DB_DX_BOBK_BOARD_NAND_CONTROL,
+ /* NOR init params */
+ .norFlashReadParams = DB_DX_BOBK_BOARD_NOR_READ_PARAMS,
+ .norFlashWriteParams = DB_DX_BOBK_BOARD_NOR_WRITE_PARAMS,
+ .isSmiExternalPp = MV_TRUE,
+ .smiExternalPpIndex = 1,
+ .modelName = "BobK Caelum Development Board",
.isSdMmcConnected = MV_TRUE
};
@@ -1288,7 +1506,8 @@
};
MV_BOARD_INFO *marvellBOBKBoardInfoTbl[] = {
- &db_dx_bobkInfo
+ &db_dx_bobkCetusInfo,
+ &db_dx_bobkCaelumInfo
};
MV_BOARD_INFO *marvellAC3BoardInfoTbl[] = {
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
index 9188e40..10ad2e2 100644
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvSpec.h
@@ -106,15 +106,15 @@
/* BobK Customer Boards */
#define BOBK_CUSTOMER_BOARD_ID_BASE 0x40
-#define BOBK_CUSTOMER_BOARD_ID0 (BOBK_CUSTOMER_BOARD_ID_BASE + 0)
-#define BOBK_CUSTOMER_BOARD_ID1 (BOBK_CUSTOMER_BOARD_ID_BASE + 1)
+#define BOBK_CETUS_CUSTOMER_BOARD_ID0 (BOBK_CUSTOMER_BOARD_ID_BASE + 0)
+#define BOBK_CAELUM_CUSTOMER_BOARD_ID1 (BOBK_CUSTOMER_BOARD_ID_BASE + 1)
#define BOBK_CUSTOMER_MAX_BOARD_ID (BOBK_CUSTOMER_BOARD_ID_BASE + 2)
#define BOBK_CUSTOMER_BOARD_NUM (BOBK_CUSTOMER_MAX_BOARD_ID - BOBK_CUSTOMER_BOARD_ID_BASE)
/* BobK Marvell Boards */
#define BOBK_MARVELL_BOARD_ID_BASE 0x50
-#define DB_BOBK_ID (BOBK_MARVELL_BOARD_ID_BASE + 0)
-#define RD_BOBK_ID (BOBK_MARVELL_BOARD_ID_BASE + 1)
+#define BOBK_CETUS_DB_ID (BOBK_MARVELL_BOARD_ID_BASE + 0)
+#define BOBK_CAELUM_DB_ID (BOBK_MARVELL_BOARD_ID_BASE + 1)
#define BOBK_MARVELL_MAX_BOARD_ID (BOBK_MARVELL_BOARD_ID_BASE + 2)
#define BOBK_MARVELL_BOARD_NUM (BOBK_MARVELL_MAX_BOARD_ID - BOBK_MARVELL_BOARD_ID_BASE)
@@ -136,11 +136,10 @@
#define MV_MARVELL_BOARD_NUM BC2_MARVELL_BOARD_NUM
#define MV_DEFAULT_BOARD_ID DB_DX_BC2_ID
#else
-/* BobK Marvell boards - TBD!*/
#define MARVELL_BOARD_ID_BASE BOBK_MARVELL_BOARD_ID_BASE
#define MV_MAX_MARVELL_BOARD_ID BOBK_MARVELL_MAX_BOARD_ID
#define MV_MARVELL_BOARD_NUM BOBK_MARVELL_BOARD_NUM
- #define MV_DEFAULT_BOARD_ID DB_BOBK_ID
+ #define MV_DEFAULT_BOARD_ID BOBK_CETUS_DB_ID
#endif
/********************************************
@@ -312,37 +311,59 @@
* Bobk Boards
*********************************************/
/*******************************************************************************
-* BobK Customer board - Based on DB_DX_BOBK
+* BobK Cetus Customer board - Based on BOBK-CETUS-DB-98DX4235-12XG
*******************************************************************************/
-#define BOBK_CUSTOMER_0_MPP0_7 0x22242222
-#define BOBK_CUSTOMER_0_MPP8_15 0x11122222
-#define BOBK_CUSTOMER_0_MPP16_23 0x44444044
-#define BOBK_CUSTOMER_0_MPP24_31 0x14444444
-#define BOBK_CUSTOMER_0_MPP32_39 0x00000001
+#define BOBK_CETUS_CUSTOMER_0_MPP0_7 0x22242222
+#define BOBK_CETUS_CUSTOMER_0_MPP8_15 0x11122222
+#define BOBK_CETUS_CUSTOMER_0_MPP16_23 0x44444044
+#define BOBK_CETUS_CUSTOMER_0_MPP24_31 0x14444444
+#define BOBK_CETUS_CUSTOMER_0_MPP32_39 0x00000001
-#define BOBK_CUSTOMER_0_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
| BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
-#define BOBK_CUSTOMER_0_GPP_OUT_ENA_MID (~(0))
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_ENA_MID (~(0))
-#define BOBK_CUSTOMER_0_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
| BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
-#define BOBK_CUSTOMER_0_GPP_OUT_VAL_MID 0x0
+#define BOBK_CETUS_CUSTOMER_0_GPP_OUT_VAL_MID 0x0
-#define BOBK_CUSTOMER_0_GPP_POL_LOW 0x0
-#define BOBK_CUSTOMER_0_GPP_POL_MID 0x0
+#define BOBK_CETUS_CUSTOMER_0_GPP_POL_LOW 0x0
+#define BOBK_CETUS_CUSTOMER_0_GPP_POL_MID 0x0
-/******************/
-/* DB_DX_BOBK */
-/******************/
-#define DB_DX_BOBK_MPP0_7 0x22242222
-#define DB_DX_BOBK_MPP8_15 0x11122222
-#define DB_DX_BOBK_MPP16_23 0x44444044
-#define DB_DX_BOBK_MPP24_31 0x14444444
-#define DB_DX_BOBK_MPP32_39 0x00000001
+/*******************************************************************************
+* BobK Caelum Customer board - Based on BOBK-CAELUM-DB-98DX4203-12XG
+*******************************************************************************/
-#define DB_DX_BOBK_NOR_MPP0_7 0x44444444
-#define DB_DX_BOBK_NOR_MPP8_15 0x11122244
+#define BOBK_CAELUM_CUSTOMER_1_MPP0_7 0x22242222
+#define BOBK_CAELUM_CUSTOMER_1_MPP8_15 0x11122222
+#define BOBK_CAELUM_CUSTOMER_1_MPP16_23 0x44444044
+#define BOBK_CAELUM_CUSTOMER_1_MPP24_31 0x14444444
+#define BOBK_CAELUM_CUSTOMER_1_MPP32_39 0x00000001
+
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_ENA_MID (~(0))
+
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
+#define BOBK_CAELUM_CUSTOMER_1_GPP_OUT_VAL_MID 0x0
+
+#define BOBK_CAELUM_CUSTOMER_1_GPP_POL_LOW 0x0
+#define BOBK_CAELUM_CUSTOMER_1_GPP_POL_MID 0x0
+
+
+/************************************/
+/* BOBK-CETUS-DB-98DX4235-12XG */
+/************************************/
+#define DB_DX_BOBK_CETUS_MPP0_7 0x22242222
+#define DB_DX_BOBK_CETUS_MPP8_15 0x11122222
+#define DB_DX_BOBK_CETUS_MPP16_23 0x44444044
+#define DB_DX_BOBK_CETUS_MPP24_31 0x14444444
+#define DB_DX_BOBK_CETUS_MPP32_39 0x00000001
+
+#define DB_DX_BOBK_CETUS_NOR_MPP0_7 0x44444444
+#define DB_DX_BOBK_CETUS_NOR_MPP8_15 0x11122244
/* GPPs
MPP# NAME IN/OUT
@@ -383,16 +404,78 @@
32 SLV_SMI_MDIO (in/out)
*/
-#define DB_DX_BOBK_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+#define DB_DX_BOBK_CETUS_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
| BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
-#define DB_DX_BOBK_GPP_OUT_ENA_MID (~(0))
+#define DB_DX_BOBK_CETUS_GPP_OUT_ENA_MID (~(0))
-#define DB_DX_BOBK_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+#define DB_DX_BOBK_CETUS_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
| BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
-#define DB_DX_BOBK_GPP_OUT_VAL_MID 0x0
+#define DB_DX_BOBK_CETUS_GPP_OUT_VAL_MID 0x0
-#define DB_DX_BOBK_GPP_POL_LOW 0x0
-#define DB_DX_BOBK_GPP_POL_MID 0x0
+#define DB_DX_BOBK_CETUS_GPP_POL_LOW 0x0
+#define DB_DX_BOBK_CETUS_GPP_POL_MID 0x0
+
+/*************************************/
+/* BOBK-CAELUM-DB-98DX4203-12XG */
+/*************************************/
+#define DB_DX_BOBK_CAELUM_MPP0_7 0x22242222
+#define DB_DX_BOBK_CAELUM_MPP8_15 0x11122222
+#define DB_DX_BOBK_CAELUM_MPP16_23 0x44444044
+#define DB_DX_BOBK_CAELUM_MPP24_31 0x14444444
+#define DB_DX_BOBK_CAELUM_MPP32_39 0x00000001
+
+#define DB_DX_BOBK_CAELUM_NOR_MPP0_7 0x44444444
+#define DB_DX_BOBK_CAELUM_NOR_MPP8_15 0x11122244
+
+/* GPPs
+MPP# NAME IN/OUT
+----------------------------------------------
+0 SPI_MOSI (out)
+1 SPI_MISO (in)
+2 SPI_SCK (out)
+3 SPI_CS0n (out)
+4 DEV_CSn[0] (out) NF CS (Boot)
+5 SD_CMD (in/out)
+6 SD_CLK (out)
+7 SD_D[0] (in/out)
+8 SD_D[1] (in/out)
+9 SD_D[2] (in/out)
+10 SD_D[3] (in/out)
+11 UART1_RXD (in)
+12 UART1_TXD (out)
+13 INTERRUPT_OUTn (out)
+14 I2C_SCL (in/out)
+15 I2C_SDA (in/out)
+
+16 DEV_Oen_NF_Ren (out)
+17 DEV_CLK_OUT (out) Test point
+18 GPIO[18] (in/out) INT_in / SD_WP / VC2_GPP
+19 NF_RBn (in)
+20 DEV_WEn[0] (out)
+21 DEV_AD[0] (in/out)
+22 DEV_AD[1] (in/out)
+23 DEV_AD[2] (in/out)
+24 DEV_AD[3] (in/out)
+25 DEV_AD[4] (in/out)
+26 DEV_AD[5] (in/out)
+27 DEV_AD[6] (in/out)
+28 DEV_AD[7] (in/out)
+29 NF_CLE_DEV_A[0] (out)
+30 NF_ALE_DEV_A[1] (out)
+31 SLV_SMI_MDC (in)
+32 SLV_SMI_MDIO (in/out)
+
+*/
+#define DB_DX_BOBK_CAELUM_GPP_OUT_ENA_LOW (~(BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30))
+#define DB_DX_BOBK_CAELUM_GPP_OUT_ENA_MID (~(0))
+
+#define DB_DX_BOBK_CAELUM_GPP_OUT_VAL_LOW (BIT0 | BIT2 | BIT3 | BIT4 | BIT6 | BIT12\
+ | BIT13 | BIT16 | BIT17 | BIT20 | BIT29 | BIT30)
+#define DB_DX_BOBK_CAELUM_GPP_OUT_VAL_MID 0x0
+
+#define DB_DX_BOBK_CAELUM_GPP_POL_LOW 0x0
+#define DB_DX_BOBK_CAELUM_GPP_POL_MID 0x0
/********************************************
* AlleyCat3 Boards
diff --git a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
index 5bca590..b1f69de 100644
--- a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
+++ b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
@@ -99,7 +99,8 @@
MV_U32 cpuClk[] = MV_CPU_CLK_TBL_AXP;
MV_CPUDDR_MODE bc2ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BC2;
MV_CPUDDR_MODE ac3ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_AC3;
- MV_CPUDDR_MODE bobkClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK;
+ MV_CPUDDR_MODE bobkCetusClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CETUS;
+ MV_CPUDDR_MODE bobkCaelumClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
MV_U32 sar2;
@@ -116,9 +117,21 @@
freqMhz = bc2ClockRatioTbl[idx].cpuFreq * 1000000;
else if (family == MV_ALLEYCAT3_DEV_ID)
freqMhz = ac3ClockRatioTbl[idx].cpuFreq * 1000000;
- else if (family == MV_BOBK_DEV_ID)
- freqMhz = bobkClockRatioTbl[idx].cpuFreq * 1000000;
- else
+ else if (family == MV_BOBK_DEV_ID) {
+ switch (mvBoardIdGet()) {
+ case BOBK_CETUS_DB_ID:
+ case BOBK_CETUS_CUSTOMER_BOARD_ID0:
+ freqMhz = bobkCetusClockRatioTbl[idx].cpuFreq * 1000000;
+ break;
+ case BOBK_CAELUM_DB_ID:
+ case BOBK_CAELUM_CUSTOMER_BOARD_ID1:
+ freqMhz = bobkCaelumClockRatioTbl[idx].cpuFreq * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown BoardID %d, CPU freq get failed\n", mvBoardIdGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
return freqMhz;
@@ -146,7 +159,8 @@
MV_U32 freqMhz;
MV_CPUDDR_MODE bc2ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BC2;
MV_CPUDDR_MODE ac3ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_AC3;
- MV_CPUDDR_MODE bobkClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK;
+ MV_CPUDDR_MODE bobkCetusClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CETUS;
+ MV_CPUDDR_MODE bobkCaelumClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
MV_U32 sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
@@ -155,9 +169,21 @@
freqMhz = bc2ClockRatioTbl[idx].ddrFreq * 1000000;
else if (family == MV_ALLEYCAT3_DEV_ID)
freqMhz = ac3ClockRatioTbl[idx].ddrFreq * 1000000;
- else if (family == MV_BOBK_DEV_ID)
- freqMhz = bobkClockRatioTbl[idx].ddrFreq * 1000000;
- else
+ else if (family == MV_BOBK_DEV_ID) {
+ switch (mvBoardIdGet()) {
+ case BOBK_CETUS_DB_ID:
+ case BOBK_CETUS_CUSTOMER_BOARD_ID0:
+ freqMhz = bobkCetusClockRatioTbl[idx].ddrFreq * 1000000;
+ break;
+ case BOBK_CAELUM_DB_ID:
+ case BOBK_CAELUM_CUSTOMER_BOARD_ID1:
+ freqMhz = bobkCaelumClockRatioTbl[idx].ddrFreq * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown BoardID %d, DDR freq get failed\n", mvBoardIdGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
return freqMhz;
@@ -185,7 +211,8 @@
MV_U32 freqMhz;
MV_CPUDDR_MODE bc2ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BC2;
MV_CPUDDR_MODE ac3ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_AC3;
- MV_CPUDDR_MODE bobkClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK;
+ MV_CPUDDR_MODE bobkCetusClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CETUS;
+ MV_CPUDDR_MODE bobkCaelumClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BOBK_CAELUM;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
MV_U32 sar2;
@@ -195,19 +222,26 @@
sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
idx = MSAR_CPU_DDR_CLK(0, sar2);
- switch (family) {
- case MV_BOBCAT2_DEV_ID:
+ if (family == MV_BOBCAT2_DEV_ID)
freqMhz = bc2ClockRatioTbl[idx].pllClk * 1000000;
- break;
- case MV_ALLEYCAT3_DEV_ID:
+ else if (family == MV_ALLEYCAT3_DEV_ID)
freqMhz = ac3ClockRatioTbl[idx].pllClk * 1000000;
- break;
- case MV_BOBK_DEV_ID:
- freqMhz = bobkClockRatioTbl[idx].pllClk * 1000000;
- break;
- default:
+ else if (family == MV_BOBK_DEV_ID) {
+ switch (mvBoardIdGet()) {
+ case BOBK_CETUS_DB_ID:
+ case BOBK_CETUS_CUSTOMER_BOARD_ID0:
+ freqMhz = bobkCetusClockRatioTbl[idx].pllClk * 1000000;
+ break;
+ case BOBK_CAELUM_DB_ID:
+ case BOBK_CAELUM_CUSTOMER_BOARD_ID1:
+ freqMhz = bobkCaelumClockRatioTbl[idx].pllClk * 1000000;
+ break;
+ default:
+ mvOsPrintf("ERROR: Unknown BoardID %d, PLL freq get failed\n", mvBoardIdGet());
+ return 0xFFFFFFFF;
+ }
+ } else
return 0xFFFFFFFF;
- }
return freqMhz;
}
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
index e001deb..2d25242 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
@@ -132,10 +132,11 @@
/* PNC_UNIT_ID */ { 0, 0, 1, 0,},
};
-MV_U32 mvDev2CpuMapTable[18][2] = {
+MV_U32 mvDev2CpuMapTable[19][2] = {
/* Dev ID cores# */
{MV_BOBCAT2_DEV_ID, 2},
- {MV_BOBK_DEV_ID, 2},
+ {MV_BOBK_CETUS_98DX4235_DEV_ID, 2},
+ {MV_BOBK_CAELUM_98DX4203_DEV_ID, 2},
{MV_ALLEYCAT3_98DX3336_DEV_ID, 2},
{MV_ALLEYCAT3_98DX3335_DEV_ID, 2},
{MV_ALLEYCAT3_98DX3334_DEV_ID, 2},
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index e411ffc..d087b89 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -368,7 +368,13 @@
#define DEV_ID_REG 0x1823C
#define DEVICE_ID_OFFS 0
#define DEVICE_ID_MASK 0xFFFF
-#define DEVICE_FLAVOR_MASK 0xFF
+
+/* for BobK devID, Cetus: 0xBE00 Caelum:0xBC00, the higher 6bits are the same.
+so update mask to 0x3FF, for BC2 flavor(0xF4XX), and AC3 flavor(0xFC00),
+the higher 6bits are also the same, so can work normally */
+#define DEVICE_FLAVOR_MASK 0x3FF
+
+#define BOBK_FLAVOR_MASK 0xFF /* only for Cetus & Caelum flavor */
#define DEV_REV_ID_REG 0xF8244
#define REVISON_ID_OFFS 28
#define REVISON_ID_MASK 0xF0000000
@@ -539,12 +545,18 @@
450 \
}
-#define MV_CORE_CLK_TBL_BOBK { \
+#define MV_CORE_CLK_TBL_BOBK_CETUS { \
365, 220, \
250, 200, \
167 \
}
+#define MV_CORE_CLK_TBL_BOBK_CAELUM { \
+ 365, 220, \
+ 250, 200, \
+ 167, 133 \
+ }
+
#define MV_CORE_CLK_TBL_AC3 { \
290, 250, \
222, 167, \
@@ -563,14 +575,24 @@
{1333, 666, 1600, MV_TRUE} \
}
-#define MV_CPU_DDR_CLK_TBL_BOBK { \
+#define MV_CPU_DDR_CLK_TBL_BOBK_CETUS { \
{ 400, 400, 400, MV_FALSE}, \
{1000, 667, 2000, MV_FALSE}, \
{ 667, 667, 2000, MV_FALSE}, \
{ 800, 800, 800, MV_FALSE}, \
{1200, 800, 2400, MV_FALSE}, \
{ 800, 400, 800, MV_FALSE}, \
- { 800, 800, 800, MV_FALSE} \
+ { 800, 800, 800, MV_TRUE} \
+}
+
+#define MV_CPU_DDR_CLK_TBL_BOBK_CAELUM { \
+ { 400, 400, 400, MV_FALSE}, \
+ {1000, 667, 2000, MV_TRUE}, \
+ { 667, 667, 2000, MV_FALSE}, \
+ { 800, 800, 800, MV_FALSE}, \
+ {1200, 800, 2400, MV_TRUE}, \
+ { 800, 400, 800, MV_FALSE}, \
+ { 800, 800, 800, MV_TRUE} \
}
#define MV_CPU_DDR_CLK_TBL_AC3 { \
