| # |
| # (C) Copyright 2012 |
| # Stefan Bigler, Keymile AG, stefan.bigler@keymile.com |
| # Norbert Mayer, Keymile AG, norbert.mayer@keymile.com |
| # Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk |
| # |
| # See file CREDITS for list of people who contributed to this |
| # project. |
| # |
| # This program is free software; you can redistribute it and/or |
| # modify it under the terms of the GNU General Public License as |
| # published by the Free Software Foundation; either version 2 of |
| # the License, or (at your option) any later version. |
| # |
| # This program is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| # GNU General Public License for more details. |
| # |
| # You should have received a copy of the GNU General Public License |
| # along with this program; if not, write to the Free Software |
| # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| # MA 02110-1301 USA |
| # |
| # Refer docs/README.kwimage for more details about how-to configure |
| # and create kirkwood boot image |
| # |
| # This configuration applies to COGE5 design (ARM-part) |
| # Two 8-Bit devices are connected on the 16-Bit bus on the same |
| # chip-select. The supported devices are |
| # MT47H256M8EB-3IT:C |
| # MT47H256M8EB-25EIT:C |
| |
| # Boot Media configurations |
| BOOT_FROM spi # Boot from SPI flash |
| |
| DATA 0xFFD10000 0x01112222 # MPP Control 0 Register |
| # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) |
| # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) |
| # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) |
| # bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) |
| # bit 19-16: 1, MPPSel4 NF_IO[6] |
| # bit 23-20: 1, MPPSel5 NF_IO[7] |
| # bit 27-24: 1, MPPSel6 SYSRST_O |
| # bit 31-28: 0, MPPSel7 GPO[7] |
| |
| DATA 0xFFD10004 0x03303300 # MPP Control 1 Register |
| # bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged |
| # bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged |
| # bit 12-8: 3, MPPSel10 UA0_TXD |
| # bit 15-12: 3, MPPSel11 UA0_RXD |
| # bit 19-16: 0, MPPSel12 not connected |
| # bit 23-20: 3, MPPSel13 GPIO[14] |
| # bit 27-24: 3, MPPSel14 GPIO[15] |
| # bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) |
| |
| DATA 0xFFD10008 0x00001100 # MPP Control 2 Register |
| # bit 3-0: 0, MPPSel16 GPIO[16] |
| # bit 7-4: 0, MPPSel17 not connected |
| # bit 11-8: 1, MPPSel18 NF_IO[0] |
| # bit 15-12: 1, MPPSel19 NF_IO[1] |
| # bit 19-16: 0, MPPSel20 GPIO[20] |
| # bit 23-20: 0, MPPSel21 GPIO[21] |
| # bit 27-24: 0, MPPSel22 GPIO[22] |
| # bit 31-28: 0, MPPSel23 GPIO[23] |
| |
| # MPP Control 3-6 Register untouched (MPP24-49) |
| |
| DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register |
| # bit 2-0: 3, Reserved |
| # bit 5-3: 3, Reserved |
| # bit 6: 0, Reserved |
| # bit 7: 0, RGMII-pads voltage = 3.3V |
| # bit 10-8: 3, Reserved |
| # bit 13-11: 3, Reserved |
| # bit 14: 0, Reserved |
| # bit 15: 0, MPP RGMII-pads voltage = 3.3V |
| # bit 31-16 0x1B1B, Reserved |
| |
| DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register |
| # bit 0-1: 2, Tag RAM RTC RAM0 |
| # bit 3-2: 1, Tag RAM WTC RAM0 |
| # bit 7-4: 6, Reserved |
| # bit 9-8: 2, Valid RAM RTC RAM |
| # bit 11-10: 1, Valid RAM WTC RAM |
| # bit 13-12: 2, Dirty RAM RTC RAM |
| # bit 15-14: 1, Dirty RAM WTC RAM |
| # bit 17-16: 2, Data RAM RTC RAM0 |
| # bit 19-18: 1, Data RAM WTC RAM0 |
| # bit 21-20: 2, Data RAM RTC RAM1 |
| # bit 23-22: 1, Data RAM WTC RAM1 |
| # bit 25-24: 2, Data RAM RTC RAM2 |
| # bit 27-26: 1, Data RAM WTC RAM2 |
| # bit 29-28: 2, Data RAM RTC RAM3 |
| # bit 31-30: 1, Data RAM WTC RAM4 |
| |
| DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register |
| # bit 15-0: ?, Reserved |
| # bit 17-16: 2, ECC RAM RTC RAM0 |
| # bit 19-18: 1, ECC RAM WTC RAM0 |
| # bit 31-20: ?,Reserved |
| |
| # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! |
| # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage |
| |
| # SDRAM initalization |
| DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register |
| # bit 13-0: 0x4E0, DDR2 clks refresh rate |
| # bit 14: 0, reserved |
| # bit 15: 0, reserved |
| # bit 16: 0, CPU to Dram Write buffer policy |
| # bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic |
| # bit 19-18: 0, reserved |
| # bit 23-20: 0, reserved |
| # bit 24: 1, enable exit self refresh mode on DDR access |
| # bit 25: 1, required |
| # bit 29-26: 0, reserved |
| # bit 31-30: 1, reserved |
| |
| DATA 0xFFD01404 0x36543000 # DDR Controller Control Low |
| # bit 3-0: 0, reserved |
| # bit 4: 0, 2T mode =addr/cmd in same cycle |
| # bit 5: 0, clk is driven during self refresh, we don't care for APX |
| # bit 6: 0, use recommended falling edge of clk for addr/cmd |
| # bit 7-11: 0, reserved |
| # bit 12-13: 1, reserved, required 1 |
| # bit 14: 0, input buffer always powered up |
| # bit 17-15: 0, reserved |
| # bit 18: 1, cpu lock transaction enabled |
| # bit 19: 0, reserved |
| # bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 |
| # bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM |
| # bit 30-28: 3, required |
| # bit 31: 0, no additional STARTBURST delay |
| |
| DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) |
| # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles |
| # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles |
| # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles |
| # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles |
| # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles |
| # bit 20: 0, extended TRAS msb |
| # bit 23-21: 0, reserved |
| # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles |
| # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles |
| |
| DATA 0xFFD0140C 0x0000003E # DDR Timing (High) |
| # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles |
| # bit 8-7: 0, TR2R |
| # bit 10-9: 0, TR2W |
| # bit 12-11: 0, TW2W |
| # bit 31-13: 0, reserved |
| |
| DATA 0xFFD01410 0x00000000 # DDR Address Control |
| # bit 1-0: 0, Cs0width=x8 (2 devices) |
| # bit 3-2: 0, Cs0size=2Gb |
| # bit 5-4: 0, Cs1width=nonexistent |
| # bit 7-6: 0, Cs1size =nonexistent |
| # bit 9-8: 0, Cs2width=nonexistent |
| # bit 11-10: 0, Cs2size =nonexistent |
| # bit 13-12: 0, Cs3width=nonexistent |
| # bit 15-14: 0, Cs3size =nonexistent |
| # bit 16: 0, Cs0AddrSel |
| # bit 17: 0, Cs1AddrSel |
| # bit 18: 0, Cs2AddrSel |
| # bit 19: 0, Cs3AddrSel |
| # bit 31-20: 0, required |
| |
| DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
| # bit 0: 0, OpenPage enabled |
| # bit 31-1: 0, required |
| |
| DATA 0xFFD01418 0x00000000 # DDR Operation |
| # bit 3-0: 0, DDR cmd |
| # bit 31-4: 0, required |
| |
| DATA 0xFFD0141C 0x00000652 # DDR Mode |
| # bit 2-0: 2, Burst Length = 4 |
| # bit 3: 0, Burst Type |
| # bit 6-4: 5, CAS Latency = 5 |
| # bit 7: 0, Test mode |
| # bit 8: 0, DLL Reset |
| # bit 11-9: 3, Write recovery for auto-precharge must be 3 |
| # bit 12: 0, Active power down exit time, fast exit |
| # bit 14-13: 0, reserved |
| # bit 31-15: 0, reserved |
| |
| DATA 0xFFD01420 0x00000006 # DDR Extended Mode |
| # bit 0: 0, DDR DLL enabled |
| # bit 1: 1, DDR drive strenght reduced |
| # bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] |
| # bit 5-3: 0, required |
| # bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] |
| # bit 9-7: 0, required |
| # bit 10: 0, differential DQS enabled |
| # bit 11: 0, required |
| # bit 12: 0, DDR output buffer enabled |
| # bit 31-13: 0 required |
| |
| DATA 0xFFD01424 0x0000F17F # DDR Controller Control High |
| # bit 2-0: 7, required |
| # bit 3: 1, MBUS Burst Chop disabled |
| # bit 6-4: 7, required |
| # bit 7: 0, reserved |
| # bit 8: 1, add sample stage required for > 266Mhz |
| # bit 9: 0, no half clock cycle addition to dataout |
| # bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals |
| # bit 11: 0, 1/4 clock cycle skew disabled for write mesh |
| # bit 15-12:0xf, required |
| # bit 31-16: 0, required |
| |
| DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low |
| # bit 3-0: 0, required |
| # bit 7-4: 2, M_ODT assertion 2 cycles after read start command |
| # bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command |
| # (ODT turn off delay 2,5 clk cycles) |
| # bit 15-12: 4, internal ODT time based on bit 7-4 |
| # with the considered SDRAM internal delay |
| # bit 19-16: 8, internal ODT de-assertion based on bit 11-8 |
| # with the considered SDRAM internal delay |
| # bit 31-20: 0, required |
| |
| DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High |
| # bit 3-0: 2, M_ODT assertion same as bit 11-8 |
| # bit 7-4: 5, M_ODT de-assertion same as bit 15-12 |
| # bit 11-8: 4, internal ODT assertion 2 cycles after write start command |
| # with the considered SDRAM internal delay |
| # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command |
| # with the considered SDRAM internal delay |
| |
| DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
| # bit 23-0: 0, reserved |
| # bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] |
| |
| DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size |
| # bit 0: 1, Window enabled |
| # bit 1: 0, Write Protect disabled |
| # bit 3-2: 0, CS0 hit selected |
| # bit 23-4:ones, required |
| # bit 31-24:0x1F, Size (i.e. 512MB) |
| |
| DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled |
| DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
| DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
| |
| DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) |
| # bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 |
| # bit 7-4: 0, ODT0Rd, MODT[1] not asserted |
| # bit 11-8: 0, required |
| # big 15-11: 0, required |
| # bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 |
| # bit 23-20: 0, ODT0Wr, MODT[1] not asserted |
| # bit 27-24: 0, required |
| # bit 31-28: 0, required |
| |
| DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) |
| # bit 1-0: 0, ODT0 controlled by ODT Control (low) register above |
| # bit 3-2: 1, ODT1 never active |
| # bit 31-4: 0, required |
| |
| DATA 0xFFD0149C 0x0000E801 # CPU ODT Control |
| # bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 |
| # bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 |
| # bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr |
| # bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm |
| # bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm |
| # bit 14: 1, STARTBURST ODT enabled |
| # bit 15: 1, Use ODT Block |
| |
| DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
| # bit 0: 1, enable DDR init upon this register write |
| # bit 31-1: 0, reserved |
| |
| # End of Header extension |
| DATA 0x0 0x0 |
