fix: i2c: a385-amc: disable external I2C: prevent bus contention
A385-AMC has external I2C access via AMC connector, which is needed to:
- detect remote MSYS PCIe Gen settings (via MSYS i2c EEPROM)
- configure MSYS Sample at reset values via remote i2c devices
When A385 is mastering the I2C bus in parallel with MSYS platform,
I2C bus contention sometimes occur, which leads to invalid board
configuration for A385 (invalid Board ID from EEPROM, etc..)
To avoid this issue, this patch currently disable external I2C
access on A385-AMC side (via GPIO)
Change-Id: I76644ccab224de4fd42007f161269625630f3680
Signed-off-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/22267
Tested-by: Star_Automation <star@marvell.com>
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
index 36c8e4d..8b65364 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
@@ -303,7 +303,7 @@
#define DB_AMC_88F68XX_GPP_OUT_ENA_MID (~(BIT12 | BIT17 | BIT18 | BIT20 | BIT21)) /* 44:I2C_EXT_EN, 49,50,52,53:Leds*/
#define DB_AMC_88F68XX_GPP_OUT_ENA_HIGH 0xFFFFFFFF
#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT29) /* GPIO29: QS_SMI_ENA = OUT VAL High */
-#define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0 /* (was BIT12): GPIO44 I2C_EXT_EN = OUT VAL Low */
+#define DB_AMC_88F68XX_GPP_OUT_VAL_MID (BIT12) /* (was BIT12): GPIO44 I2C_EXT_EN = FALSE (False = OUT VAL High) */
#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
#define DB_AMC_88F68XX_GPP_POL_LOW 0x0
#define DB_AMC_88F68XX_GPP_POL_MID 0x0
diff --git a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c
index ab3599e..a0b908c 100755
--- a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c
+++ b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c
@@ -258,13 +258,13 @@
MV_REG_BIT_RESET(TWSI_CONFIG_DEBUG_REG, TWSI_DEBUG_SLAVE_PORT0_EN);
MV_REG_BIT_RESET(TWSI_CONFIG_DEBUG_REG, TWSI_DEBUG_SLAVE_PORT1_EN);
- /* GPP configuration is required for enabling access to i2c channel 1
- Output from GPP-44 should set to be HIGH for enabling external
+ /* GPP configuration is required for disabling access to i2c channel 1
+ Output from GPP-44 should set to be HIGH for disabling external
i2c channel 1 buffer circuit
The entire GPPs configuration is the same as in u-boot */
/* Set GPP Out value */
MV_REG_WRITE(GPP_DATA_OUT_REG(0), BIT29); /* GPIO29: QS_SMI_ENA = OUT VAL High */
- MV_REG_WRITE(GPP_DATA_OUT_REG(1), 0); /* GPIO44: I2C_EXT_EN = OUT VAL Low */
+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BIT12); /* GPIO44 (BIT12) : I2C_EXT_EN = FALSE (False = OUT VAL High) */
MV_REG_WRITE(GPP_DATA_OUT_REG(2), 0);
/* set GPP polarity */
