| commit | d0b23e8a199c1ffc314fafbc07e9d13de303eb34 | [log] [tgz] |
|---|---|---|
| author | Margarita Granov <margra@marvell.com> | Mon Aug 10 16:51:58 2015 +0300 |
| committer | Greg Poist <poist@google.com> | Thu Mar 24 11:59:54 2016 -0700 |
| tree | cf4787a8f4e90129364f7fabf2e064f361160e99 | |
| parent | ea1a440ea18bce9f42576773e7e6b790eea9654c [diff] |
ddr3libv2: bobk: Add write leveling supplementary to DDR3 training Change ddr3 tune mask to implement write/read supplementary Change-Id: Ic956f695c5e196717c913b28538073a50eff2131 Signed-off-by: Margarita Granov <margra@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/22707 Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/24154 Tested-by: Star_Automation <star@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c index e27fa4c..d049b55 100755 --- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c +++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -855,13 +855,13 @@ SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT | LOAD_PATTERN_2_MASK_BIT | - /*WRITE_LEVELING_SUPP_MASK_BIT |*/ + WRITE_LEVELING_SUPP_MASK_BIT | READ_LEVELING_MASK_BIT | PBS_RX_MASK_BIT | PBS_TX_MASK_BIT | SET_TARGET_FREQ_MASK_BIT | WRITE_LEVELING_TF_MASK_BIT | - /*WRITE_LEVELING_SUPP_TF_MASK_BIT |*/ + WRITE_LEVELING_SUPP_TF_MASK_BIT | READ_LEVELING_TF_MASK_BIT | CENTRALIZATION_RX_MASK_BIT | CENTRALIZATION_TX_MASK_BIT