commit cf93ddbdb4dfded99c51a2dae975a44f35a04e0e
author Margarita Granov <margra@marvell.com> Wed May 06 10:09:45 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree f9cb827830cce5c8b06e03a1d6e84af4e93252ce
parent 402048e3d4a28e4bdef24d05c9028d151f73cde1

ddr3libv2: Add the possibility to change DDR training flags in DEBUG mode

	Add DDR training flags to access attribute list

Change-Id: Ia53068ee95324200c4d364131fc93fcd33acb84c
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19024
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Reviewed-by: Igor Patrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24117
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
index 98360f5..4f28b3c 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
@@ -692,7 +692,7 @@
 ******************************************************************************/
 GT_STATUS ddr3TipRegisterXsbInfo
 (
-    GT_U32					devNum, 
+    GT_U32					devNum,
     MV_HWS_XSB_INFO         *xsbInfoTable
 )
 {
@@ -761,10 +761,13 @@
 extern GT_U8  isDfsInInit;
 extern GT_32 wlDebugDelay;
 extern GT_U32 siliconDelay[HWS_MAX_DEVICE_NUM];
-#ifdef ODT_TEST_SUPPORT
-extern GT_U32 Pfinger;
-extern GT_U32 Nfinger;
-#endif
+extern 	GT_U32 vrefInitialValue;
+extern 	GT_U32 gZpriData;
+extern 	GT_U32 gZnriData;
+extern 	GT_U32 gZpriCtrl;
+extern 	GT_U32 gZnriCtrl;
+extern 	GT_U32 gZpodtData;
+extern 	GT_U32 gZnodtData;
 extern GT_U32 freqVal[DDR_FREQ_LIMIT];
 extern GT_U32 startPattern, endPattern;
 extern GT_U32  PhyReg0Val;
@@ -989,15 +992,14 @@
    case 0x32:
        *ptr = (GT_U32*) &isDfsInInit;
        break;
-#ifdef ODT_TEST_SUPPORT
    case 0x33:
-       *ptr = (GT_U32*) &Pfinger;
+       *ptr = (GT_U32*) &gZnodtData;
        break;
 
    case 0x34:
-       *ptr = (GT_U32*) &Nfinger;
+       *ptr = (GT_U32*) &gZpodtData;
        break;
-#endif
+
    case 0x35:
        initFreq = (MV_HWS_DDR_FREQ)value;
        break;
@@ -1038,6 +1040,13 @@
        *ptr = (GT_U32*) &(phy1ValTable[DDR_FREQ_LOW_FREQ]);
        break;
 */
+   case 0x51:
+       *ptr = (GT_U32*) &gZnriData;
+       break;
+
+   case 0x52:
+       *ptr = (GT_U32*) &gZpriData;
+       break;
 
    case 0x53:
        *ptr = (GT_U32*) &fingerTest;
@@ -1067,10 +1076,21 @@
        *ptr = (GT_U32*) &nFingerStep;
        break;
 
+   case 0x5A:
+       *ptr = (GT_U32*) &gZnriCtrl;
+       break;
+
+   case 0x5B:
+       *ptr = (GT_U32*) &gZpriCtrl;
+       break;
    case 0x5C:
        *ptr = (GT_U32*) &isRegDump;
        break;
 
+   case 0x5D:
+       *ptr = (GT_U32*) &vrefInitialValue;
+       break;
+
    case 0x5E:
        *ptr = (GT_U32*) &mode2T;
        break;