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| *******************************************************************************/ |
| #include "config_marvell.h" /* Required to identify SOC and Board */ |
| #include "mv_os.h" |
| #include "mvSysEnvLib.h" |
| #if defined(MV88F78X60) |
| #include "ddr3_axp.h" |
| #elif defined(MV88F6710) |
| #include "ddr3_a370.h" |
| extern MV_U32 mvCpuL2ClkGet(MV_VOID); |
| #elif defined(MV88F68XX) |
| #include "ddr3_a38x.h" |
| #elif defined(MV88F69XX) |
| #include "ddr3_a39x.h" |
| #elif defined(MV88F66XX) |
| #include "ddr3_alp.h" |
| extern MV_U32 mvCpuL2ClkGet(MV_VOID); |
| #elif defined(MV88F672X) |
| #include "ddr3_a375.h" |
| extern MV_U32 mvCpuL2ClkGet(MV_VOID); |
| #elif defined(MV_MSYS_BC2) |
| #include "ddr3_msys_bc2.h" |
| #elif defined(MV_MSYS_AC3) |
| #include "ddr3_msys_ac3.h" |
| #else |
| #error "No SOC define for uart in binary header." |
| #endif |
| #define UBOOT_CNTR 0 /* counter to use for uboot timer 0,1 */ |
| |
| void __udelay(unsigned long usec) |
| { |
| unsigned long delayticks; |
| unsigned int cntmrCtrl; |
| |
| /* In case udelay is called before timier was initialized */ |
| delayticks = (usec * (MV_BOARD_REFCLK / 1000000)); |
| /* init the counter */ |
| MV_REG_WRITE(CNTMR_RELOAD_REG(UBOOT_CNTR),delayticks); |
| MV_REG_WRITE(CNTMR_VAL_REG(UBOOT_CNTR),delayticks); |
| |
| /* set control for timer \ cunter and enable */ |
| /* read control register */ |
| cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(UBOOT_CNTR)); |
| cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); |
| cntmrCtrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); |
| |
| /* check if 25Mhz as ref clock is supported by SoC */ |
| if (mvSysEnvTimerIsRefClk25Mhz()) |
| cntmrCtrl |= CTCR_ARM_TIMER_25MhzFRQ_EN(UBOOT_CNTR); |
| |
| MV_REG_WRITE(CNTMR_CTRL_REG(UBOOT_CNTR),cntmrCtrl); |
| |
| while(MV_REG_READ(CNTMR_VAL_REG(UBOOT_CNTR))); |
| |
| /* disable times*/ |
| cntmrCtrl &= ~CTCR_ARM_TIMER_EN(UBOOT_CNTR); |
| MV_REG_WRITE(CNTMR_CTRL_REG(UBOOT_CNTR),cntmrCtrl); |
| } |
| void __timerSet(unsigned long usec) |
| { |
| unsigned int cntmrCtrl; |
| unsigned long startTicks; |
| |
| /* In case udelay is called before timier was initialized */ |
| startTicks = (usec * (MV_BOARD_REFCLK / 1000000)); |
| /* init the counter */ |
| MV_REG_WRITE(CNTMR_RELOAD_REG(UBOOT_CNTR),startTicks); |
| MV_REG_WRITE(CNTMR_VAL_REG(UBOOT_CNTR),startTicks); |
| |
| /* set control for timer \ cunter and enable */ |
| /* read control register */ |
| cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(UBOOT_CNTR)); |
| cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); |
| cntmrCtrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); |
| cntmrCtrl |= CTCR_ARM_TIMER_25MhzFRQ_EN(UBOOT_CNTR); |
| MV_REG_WRITE(CNTMR_CTRL_REG(UBOOT_CNTR),cntmrCtrl); |
| |
| } |
| MV_U32 __timerGet(void) |
| { |
| return MV_REG_READ(CNTMR_VAL_REG(UBOOT_CNTR)); |
| } |
| |
| void __timerDisable(void) |
| { |
| unsigned int cntmrCtrl; |
| cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG(UBOOT_CNTR)); |
| cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); |
| cntmrCtrl |= CTCR_ARM_TIMER_25MhzFRQ_EN(UBOOT_CNTR); |
| /* disable times*/ |
| cntmrCtrl &= ~CTCR_ARM_TIMER_EN(UBOOT_CNTR); |
| MV_REG_WRITE(CNTMR_CTRL_REG(UBOOT_CNTR),cntmrCtrl); |
| } |
