msys: axp-amc: merge register information of AXP and MSYS
- TODO - solve problem with different definitions of MV_XOR_REGS_OFFSET
and MV_GPP_REGS_OFFSET
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Conflicts:
arch/arm/mach-msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
Change-Id: Ifcdac8527d4a99952533768bf514f27bc4948b40
Reviewed-on: http://vgitil04.il.marvell.com:8080/20548
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
index a1dab3f..b2eed16 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvSpec.h
@@ -82,7 +82,7 @@
#define SOC_NAME_PREFIX "Bobcat2"
#endif
/*
- * Bobcat2 Units Address decoding
+ * Bobcat2/AXP Units Address decoding
*/
#define MV_DRAM_REGS_OFFSET (0x0)
#define MV_AURORA_L2_REGS_OFFSET (0x8000)
@@ -92,9 +92,11 @@
#define MV_TWSI_SLAVE_REGS_OFFSET(chanNum) (0x11000 + (chanNum * 0x100))
#define MV_UART_REGS_OFFSET(chanNum) (0x12000 + (chanNum * 0x100))
+#define MV_RUNIT_PMU_REGS_OFFSET (0x1C000)
#define MV_MPP_REGS_OFFSET (0x18000)
#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x80))
+#define MV_GPP_REGS_OFFSET_AXP(unit) (0x18100 + ((unit) * 0x40))
#define MV_MISC_REGS_OFFSET (0x18200)
#define MV_CLK_CMPLX_REGS_OFFSET (0x18700)
@@ -108,17 +110,21 @@
#define MV_CPUIF_REGS_OFFSET(cpu) (0x21800 + (cpu) * 0x100)
#define MV_PMU_NFABRIC_UNIT_SERV_OFFSET (0x22000)
#define MV_CPU_PMU_UNIT_SERV_OFFSET(cpu) (0x22100 + (cpu) * 0x100)
+#define MV_CPU_HW_SEM_OFFSET (0x20500)
#define MV_ETH_BASE_ADDR (0x70000)
-#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR + (port) * 0x4000)
+#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * 0x40000 + ((port) % 2) * 0x4000)
#define MV_PEX_IF_REGS_OFFSET(pexIf)\
(pexIf < 8 ? (0x40000 + ((pexIf) / 4) * 0x40000 + ((pexIf) % 4) * 0x4000)\
: (0X42000 + ((pexIf) % 8) * 0x40000))
#define MV_USB_REGS_OFFSET(dev) (0x50000 + (dev * 0x1000))
#define MV_USB2_USB3_REGS_OFFSET(unitType, dev) (MV_USB_REGS_OFFSET(dev))
#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
+#define MV_XOR_REGS_OFFSET_AXP(unit) (unit ? 0xF0900 : 0x60900)
#if defined(MV_INCLUDE_IDMA)
#define MV_IDMA_REGS_OFFSET (0x60800)
#endif
+#define MV_CESA_TDMA_REGS_OFFSET(chanNum) (0x90000 + (chanNum * 0x2000))
+#define MV_CESA_REGS_OFFSET(chanNum) (0x9D000 + (chanNum * 0x2000))
#define MV_SATA_REGS_OFFSET (0xA0000)
#define MV_COMM_UNIT_REGS_OFFSET (0xB0000)
#define MV_NFC_REGS_OFFSET (0xD0000)
@@ -142,17 +148,19 @@
#define TWSI0_CPU_MAIN_INT_BIT(ch) ((ch) + 3)
#define TWSI_SPEED 100000
-#define MV_GPP_MAX_PINS 33
+#define MV_GPP_MAX_PINS 68
#define MV_GPP_MAX_GROUP 2 /* group == configuration register? */
+#define MV_GPP_MAX_GROUP_AXP 3
#define MV_CNTMR_MAX_COUNTER 8 /* 4 global + 1 global WD + 2 current private CPU + 1 private CPU WD*/
#define MV_UART_MAX_CHAN 2
-#define MV_XOR_MAX_UNIT 1 /* XOR unit == XOR engine */
-#define MV_XOR_MAX_CHAN 2 /* total channels for all units together*/
+#define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */
+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/
#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */
#define MV_MPP_MAX_GROUP 5
+#define MV_MPP_MAX_GROUP_AXP 9
#define MV_DRAM_MAX_CS 4
#define MV_SPI_MAX_CS 8
@@ -170,6 +178,8 @@
/* This define describes the maximum number of supported PEX Interfaces */
#define MV_PEX_MAX_IF 1
#define MV_PEX_MAX_UNIT 1
+#define MV_PEX_MAX_IF_AXP 10
+#define MV_PEX_MAX_UNIT_AXP 4
#ifdef MV_INCLUDE_PEX
#define MV_INCLUDE_PEX0
#define MV_DISABLE_PEX_DEVICE_BAR
@@ -186,6 +196,10 @@
/* This define describes the maximum number of supported PCI Interfaces */
#define MV_DEVICE_MAX_CS 4
+/* CESA version #3: One channel, 2KB SRAM, TDMA, CHAIN Mode support */
+#define MV_CESA_VERSION 3
+#define MV_CESA_SRAM_SIZE (2 * 1024)
+
#ifdef CONFIG_ALLEYCAT3
#define MV_USB_MAX_PORTS 1
#else /* BC2 no USB ports */
@@ -197,11 +211,12 @@
/* TODO - verify all these numbers */
#define MV_ETH_VERSION 4 /* for Legacy mode */
#define MV_NETA_VERSION 1 /* for NETA mode */
-#define MV_ETH_MAX_PORTS 2
+#define MV_ETH_MAX_PORTS 4
#define MV_ETH_MAX_RXQ 8
#define MV_ETH_MAX_TXQ 8
#define MV_ETH_TX_CSUM_MAX_SIZE 9800
#define MV_ETH_TX_CSUM_MIN_SIZE 2048
+#define MV_PNC_TCAM_LINES 1024 /* TCAM num of entries */
#define BOARD_ETH_SWITCH_PORT_NUM 2
/* New GMAC module is used */
