msys: axp-amc: align NFC code
- update mvBoardTclkGet and mvCpuPllClkGet with values for AXP
- add auxiliary routine for setting NAND ECC clock for AXP
- add necessary registers' defines
Change-Id: I1d29983c035dcada4a274ba783f04406399d78b0
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/20557
Tested-by: Star_Automation <star@marvell.com>
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
index 4b9dd07..ee941b2 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
@@ -546,7 +546,15 @@
*******************************************************************************/
MV_U32 mvBoardTclkGet(MV_VOID)
{
- return 200000000; /* constant Tclock @ 200MHz (not Sampled@Reset) */
+ if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID)
+ /* constant Tclock @ 200MHz (not Sampled@Reset) */
+ return MV_BOARD_TCLK_200MHZ;
+
+ if ((MV_REG_READ(MPP_SAMPLE_AT_RESET(0)) & MSAR_TCLK_MASK) != 0)
+ return MV_BOARD_TCLK_200MHZ;
+ else
+ return MV_BOARD_TCLK_250MHZ;
+
}
/*******************************************************************************
diff --git a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
index 796940f..785dfe5 100644
--- a/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
+++ b/board/mv_ebu/msys/msys_family/cpu/mvCpu.c
@@ -180,7 +180,12 @@
MV_CPUDDR_MODE bc2ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_BC2;
MV_CPUDDR_MODE ac3ClockRatioTbl[8] = MV_CPU_DDR_CLK_TBL_AC3;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
- MV_U32 sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
+ MV_U32 sar2;
+
+ if (family == MV_78460_DEV_ID)
+ return AXP_PLL_IN_CLK;
+
+ sar2 = MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1));
idx = MSAR_CPU_DDR_CLK(0, sar2);
switch (family) {
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
index 659d689..2a45c4b 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
@@ -1776,6 +1776,53 @@
}
/*******************************************************************************
+* mvCtrlNandClkSetAxp
+*
+* DESCRIPTION:
+* Set the division ratio of ECC Clock for AXP
+*
+*******************************************************************************/
+static int mvCtrlNandClkSetAxp(int nfc_clk_freq, MV_U32 pll_clk)
+{
+ int divider;
+
+ /* Set the division ratio of ECC Clock 0x00018748[13:8] (by default it's
+ * double of core clock)
+ */
+ MV_U32 nVal = MV_REG_READ(AXP_CORE_DIV_CLK_CTRL(1));
+
+ /* Calculate nand divider for requested nfc_clk_freq. If integer divider
+ * cannot be achieved, it will be rounded-up, which will result in
+ * setting the closest lower frequency.
+ * ECC engine clock = (PLL frequency / divider)
+ * NFC clock = ECC clock / 2
+ */
+ divider = DIV_ROUND_UP(pll_clk, (2 * nfc_clk_freq));
+ DB(mvOsPrintf("%s: divider %d\n", __func__, divider));
+
+ nVal &= ~(AXP_NAND_ECC_DIVCLK_RATIO_MASK);
+ nVal |= (divider << AXP_NAND_ECC_DIVCLK_RATIO_OFFS);
+ MV_REG_WRITE(AXP_CORE_DIV_CLK_CTRL(1), nVal);
+
+ /* Set reload force of ECC clock 0x00018740[7:0] to 0x2 (meaning you
+ * will force only the ECC clock)
+ */
+ nVal = MV_REG_READ(AXP_CORE_DIV_CLK_CTRL(0));
+ nVal &= ~(AXP_CORE_DIVCLK_RELOAD_FORCE_MASK);
+ nVal |= AXP_CORE_DIVCLK_RELOAD_FORCE_VAL;
+ MV_REG_WRITE(AXP_CORE_DIV_CLK_CTRL(0), nVal);
+
+ /* Set reload ratio bit 0x00018740[8] to 1'b1 */
+ MV_REG_BIT_SET(AXP_CORE_DIV_CLK_CTRL(0), AXP_CORE_DIVCLK_RELOAD_RATIO_MASK);
+ mvOsDelay(1); /* msec */
+ /* Set reload ratio bit 0x00018740[8] to 0'b1 */
+ MV_REG_BIT_RESET(AXP_CORE_DIV_CLK_CTRL(0), AXP_CORE_DIVCLK_RELOAD_RATIO_MASK);
+
+ /* Return calculated nand clock frequency */
+ return (pll_clk)/(2 * divider);
+}
+
+/*******************************************************************************
* mvCtrlNandClkSet
*
* DESCRIPTION:
@@ -1793,9 +1840,14 @@
int mvCtrlNandClkSet(int nfc_clk_freq)
{
int divider;
- MV_U32 nVal = MV_DFX_REG_READ(CORE_DIV_CLK_CTRL(2));
+ MV_U32 nVal;
MV_U32 pll_clk = mvCpuPllClkGet();
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ return mvCtrlNandClkSetAxp(nfc_clk_freq, pll_clk);
+
+ nVal = MV_DFX_REG_READ(CORE_DIV_CLK_CTRL(2));
+
/*
* Calculate nand divider for requested nfc_clk_freq. If integer divider
* cannot be achieved, it will be rounded-up, which will result in
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index cb05eb4..c4f6f6a6 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -279,10 +279,23 @@
#define CORE_DIV_CLK_CTRL(num) (DFX_CORE_DIVCLK_CONTROL0_REG + ((num) * 0x4))
-
#define DFX_TEMPERATURE_SENSOR_LSB_CTRL_REG 0xF8070
#define DFX_TEMPERATURE_SENSOR_MSB_CTRL_REG 0xF8074
#define DFX_TEMPERATURE_SENSOR_STATUS_REG 0xF8078
+
+/* Core Divider Clock Control - AXP only */
+#define AXP_CORE_DIV_CLK_CTRL(num) (0x18740 + ((num) * 0x8))
+
+#define AXP_CORE_DIVCLK_RELOAD_FORCE_OFFS 0
+#define AXP_CORE_DIVCLK_RELOAD_FORCE_MASK (0xFF << AXP_CORE_DIVCLK_RELOAD_FORCE_OFFS)
+#define AXP_CORE_DIVCLK_RELOAD_FORCE_VAL (0x2 << AXP_CORE_DIVCLK_RELOAD_FORCE_OFFS)
+
+#define AXP_NAND_ECC_DIVCLK_RATIO_OFFS 8
+#define AXP_NAND_ECC_DIVCLK_RATIO_MASK (0x3F << AXP_NAND_ECC_DIVCLK_RATIO_OFFS)
+
+#define AXP_CORE_DIVCLK_RELOAD_RATIO_OFFS 8
+#define AXP_CORE_DIVCLK_RELOAD_RATIO_MASK (1 << AXP_CORE_DIVCLK_RELOAD_RATIO_OFFS)
+
/* definition for caculate Temperature */
#define TEMPERATURE_OFFSET (596)
#define TEMPERATURE_FACTOR (2154)
@@ -351,6 +364,9 @@
#define MSAR_TCLK_OFFS 28
#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
+/* PLL(CPU) input clock - AXP only */
+#define AXP_PLL_IN_CLK _2GHz
+
#ifndef MV_ASMLANGUAGE
#define MV_CPU_CLK_TBL_AXP { 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000,\
