| LOCAL &runmode |
| LOCAL &ddrbus |
| LOCAL &boardtype |
| |
| DIALOG |
| ( |
| HEADER "Marvell Avanta-LP debug" |
| POS 1. 0. 28. 1. |
| TEXT "Please select the run mode:" |
| |
| ;choosebox group for Mode |
| POS 0. 1. 29. 1. |
| LINE "Run Mode" |
| POS 1. 2. 25. 1. |
| Mode.1: CHOOSEBOX "Debugger initialization" "GOTO disable_ddr" |
| Mode.2: CHOOSEBOX "Debugger and SOC initialization" "GOTO enable_ddr" |
| |
| ;choosebox group for DDR init method |
| POS 0. 4. 29. 1. |
| LINE "DDR Init Method" |
| POS 1. 5. 25. 1. |
| DdrBus.1: CHOOSEBOX "Static DDR training" "GOTO enable_board" |
| DdrBus.2: CHOOSEBOX "Dynamic training (bypass BootROM)" "GOTO disable_board" |
| DdrBus.3: CHOOSEBOX "Dynamic training (SRAM via BootROM)" "GOTO disable_board" |
| |
| LINE "Board type for static training" |
| POS 1. 9. 10. |
| BoardType.1: CHOOSEBOX "DB-6650/6660" "" |
| BoardType.2: CHOOSEBOX "RD-6650" "" |
| BoardType.3: CHOOSEBOX "RD-6660" "" |
| |
| ;buttons OK (Default) and Cancel |
| POS 1. 13. 10. 1. |
| DEFBUTTON "OK" "CONTinue" |
| POS 14. 13. 10. 1. |
| BUTTON "Cancel" "GOTO mode_cancel" |
| ;define action when window is closed |
| CLOSE "GOTO mode_cancel" |
| ) |
| |
| disable_ddr: |
| DIALOG.SET Mode.1 |
| DIALOG.DISABLE DdrBus.1 |
| DIALOG.DISABLE DdrBus.2 |
| DIALOG.DISABLE DdrBus.3 |
| |
| disable_board: |
| DIALOG.DISABLE BoardType.1 |
| DIALOG.DISABLE BoardType.2 |
| DIALOG.DISABLE BoardType.3 |
| |
| waitforok: |
| STOP |
| GOTO dialog_ok |
| |
| mode_cancel: |
| ;script continues here when Cancel is clicked" |
| DIALOG.END |
| DIALOG.OK "Script cancelled" |
| ENDDO |
| |
| enable_ddr: |
| DIALOG.ENABLE DdrBus.1 |
| ;DIALOG.ENABLE DdrBus.2 |
| DIALOG.ENABLE DdrBus.3 |
| DIALOG.SET DdrBus.3 |
| GOTO waitforok |
| |
| enable_board: |
| DIALOG.ENABLE BoardType.1 |
| DIALOG.ENABLE BoardType.2 |
| DIALOG.ENABLE BoardType.3 |
| DIALOG.SET BoardType.1 |
| GOTO waitforok |
| |
| dialog_ok: |
| ;get selections |
| IF DIALOG.BOOLEAN(Mode.1) |
| &runmode="basic" |
| IF DIALOG.BOOLEAN(Mode.2) |
| &runmode="ddr" |
| IF DIALOG.BOOLEAN(DdrBus.1) |
| &ddrbus="static" |
| IF DIALOG.BOOLEAN(DdrBus.2) |
| &ddrbus="naked" |
| IF DIALOG.BOOLEAN(DdrBus.3) |
| &ddrbus="bootrom" |
| IF DIALOG.BOOLEAN(BoardType.1) |
| &boardtype="db6660" |
| IF DIALOG.BOOLEAN(BoardType.2) |
| &boardtype="rd6650" |
| IF DIALOG.BOOLEAN(BoardType.3) |
| &boardtype="rd6660" |
| |
| ;close dialog window |
| DIALOG.END |
| |
| ;*************************************************************************************************************** |
| ; First it is very important to select the CPU and then set the options, |
| ; otherwise important options are cleared again |
| SYStem.RESet |
| SYStem.CPU CortexA9MPCore ; or CortexA9 |
| SYStem.MultiCore MEMORYACCESSPORT 0 |
| SYStem.MultiCore DEBUGACCESSPORT 1 |
| ;SYStem.MemAccess Denied |
| |
| SYStem.MultiCore COREBASE 0xc2310000 |
| SYStem.MultiCore ETMBASE 0xc231c000 |
| SYStem.MultiCore ETBBASE 0xc2324000 |
| ;SYStem.Option L2CacheBase 0xD0008000 |
| SYStem.Option CFLUSH OFF |
| |
| SYStem.JtagClock 10Mhz |
| SYStem.Mode attach |
| SYStem.Up |
| |
| ; set system settings according LE MMU |
| ; <MCR|MRC> p15, <op1>, Rd, CRn, CRm, <op2> |
| ; BIT0-3:CRn, BIT4-7:CRm, BIT8-10:<op2>, BIT12-14:<op1>, Bit16=0 (32-bit access) |
| Per.Set C15:1 %LONG 0x00052078 |
| |
| BREAK.SELECT PROGRAM ONCHIP |
| ;*************************************************************************************************************** |
| |
| IF ("&runmode"=="ddr") |
| ( |
| ;*************************************************************************************************************** |
| IF ("&ddrbus"=="bootrom") |
| ( |
| ;*************************************************************************************************************** |
| Break 0x40000000 /Write ; Stop on L2 SRAM access |
| GO ; Run the Bootrom |
| WAIT !RUN() |
| PRINT "Please select the bin_hdr.elf file location" |
| D.LOAD ../../bin_hdr/* |
| ; The binary header is started by the following ASM code (bin_entry.s): |
| ; _start: |
| ; push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
| ; blx <mvBinHdrDispatcher> |
| ; mov r0, #0 |
| ; pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
| ; Each of these commands is 4 bytes long, while PC is set to _start upon ELF load. |
| ; Therefore the end execution break point should be set to _start + 0xC (pop) |
| Break.Set Register(PC)+0xC ; Stop at the end of BIN header execution |
| GO ; Run the BIN header |
| WAIT !RUN() |
| Break.Delete |
| Per.Set C15:1 %LONG 0x00052078 ; Disable MMU |
| PRINT "Done, DRAM is ready" ; The u-boot can be loaded and executed |
| ;*************************************************************************************************************** |
| ) |
| ELSE IF ("&ddrbus"=="naked") |
| ( |
| ;*************************************************************************************************************** |
| LOCAL ®val |
| LOCAL &savectrl |
| LOCAL &savebar |
| LOCAL &address |
| LOCAL &counter |
| |
| ;====================l2_activate=============================================== |
| ; Activate L2 cache |
| ; 1. Invalidate all ways |
| ; 2. Instruction lock all ways |
| |
| ; REG1_AUX_CONTROL |
| ; bit[16] - 16 Ways(1)/ Bit 17-19 - 64KB way (0b011) |
| ; bit[26] - enable non-secure lockdown |
| Data.Set D:0xD0008104 %LONG (Data.Long(D:0xD0008104)|(0x4070000)) |
| |
| ;SCU Disable and invalidate |
| Data.Set D:0xD000C000 %LONG (Data.Long(D:0xD000C000)&~(0x1)) |
| Data.Set D:0xD000C00C %LONG 0xFFFFFFFF |
| |
| ; Disable L2 cache through L2 REG1_CONTROL |
| Data.Set D:0xD0008100 %LONG (Data.Long(D:0xD0008100)&~(0x1)) |
| |
| ; Invalidate all ways |
| Data.Set D:0xD000877C %LONG 0xFFFF 0xFFFF ; REG7_INV_WAY |
| |
| ; Check for loops |
| WHILE ((Data.Long(D:0xD000877C)&(0x0000FFFF))!=0) |
| |
| ; Enable L2 cache - REG1_CONTROL |
| Data.Set D:0xD0008100 %LONG (Data.Long(D:0xD0008100)|(0x1)) |
| |
| ; Lock all ways Instruction cache |
| Data.Set D:0xD0008904 %LONG 0x0000FFFF ; REG9_I_LOCKDOWN0 |
| ;====================l2_activate_done========================================== |
| |
| ; Configure EFUSE Window |
| Data.Set D:0xD00200EC %LONG 0x410F0000 ; Window 19 base |
| Data.Set D:0xD00200E8 %LONG 0x00000AE1 ; Window 19 control |
| |
| ; Initial Clean up & configurations |
| |
| ; <MCR|MRC> p15, <op1>, Rd, CRn, CRm, <op2> |
| ; BIT0-3:CRn, BIT4-7:CRm, BIT8-10:<op2>, BIT12-14:<op1>, Bit16=0 (32-bit access) |
| Per.Set C15:0x57 %LONG 0x0 ; Invalidate entire I-cache, flush BTC & BTAC |
| Per.Set C15:0x78 %LONG 0x0 ; TLB invalidate |
| WAIT 1.s |
| Per.Set C15:0x3 %LONG 0x3 ; Set DAC Register - Domain 0 is manager domain |
| Per.Set C15:0x2 %LONG 0xD002C000 ; Set TTBR Register to Table in SRAM start |
| |
| ; Enable I-Cache |
| Per.Set C15:1 %LONG (Data.Long(C15:0x1)|(0x1000)) ; set bit 12 (I) I-Cache enable |
| |
| ;====================mmu_init================================================ |
| ; Initialize MMU - 8 Static Windows |
| Data.Set D:0xD0020890 %LONG ((0x00001027)|(0xFFF00000)) ; BootROM Window - 1MB |
| Data.Set D:0xD0020894 %LONG ((0x00001001)|(0xD0080000)) ; Internal Registers Window - 256MB |
| Data.Set D:0xD0020898 %LONG ((0x00001001)|(0xE0090000)) ; RUNIT Window - 512MB |
| Data.Set D:0xD002089C %LONG ((0x0000103F)|(0xC8000000)) ; CESA Window - 1MB |
| Data.Set D:0xD00208A0 %LONG ((0x00001001)|(0x41000000)) ; EFUSE Window - 1MB |
| Data.Set D:0xD00208A4 %LONG ((0x0000902F)|(0x40000000)) ; SRAM Window - 1MB |
| Data.Set D:0xD00208A8 %LONG ((0x00001001)|(0x800A0000)) ; PEX Window - 1GB |
| Data.Set D:0xD00208AC %LONG ((0x00001001)|(0x000A0000)) ; DUNIT Window - 1GB |
| ;====================mmu_init_done================================================ |
| WAIT 1.s |
| |
| ;====================dcache_invalidate================================================ |
| ; D-cache invalidate |
| ; <MCR|MRC> p15, <op1>, Rd, CRn, CRm, <op2> |
| ; BIT0-3:CRn, BIT4-7:CRm, BIT8-10:<op2>, BIT12-14:<op1>, Bit16=0 (32-bit access) |
| Per.Set C15:0x2000 %LONG 0x0 ; cache size selection register, select dcache |
| WAIT 1.s |
| |
| ®val=((Data.Long(C15:0x1000)>>(0xD))&(0xFFF)) ; cache size ID register |
| IF ®val==0x7F |
| ( |
| &counter=0x1000 ; 4KB per way |
| ) |
| IF ®val==0xFF |
| ( |
| &counter=0x2000 ; 8KB per way |
| ) |
| ELSE |
| ( |
| &counter=0x4000 ; 16KB per way |
| ) |
| ; D-cache invalidate by way loop |
| &address=0 |
| WHILE (&address<&counter) |
| ( |
| ; <MCR|MRC> p15, <op1>, Rd, CRn, CRm, <op2> |
| ; BIT0-3:CRn, BIT4-7:CRm, BIT8-10:<op2>, BIT12-14:<op1>, Bit16=0 (32-bit access) |
| Per.Set C15:0x267 %LONG &address ; invalidate dcache by set / way |
| Per.Set C15:0x267 %LONG (0x40000000+&address) ; invalidate dcache by set / way |
| Per.Set C15:0x267 %LONG (0x80000000+&address) ; invalidate dcache by set / way |
| Per.Set C15:0x267 %LONG (0xC0000000+&address) ; invalidate dcache by set / way |
| &address=&address+0x20 |
| ) |
| ;====================dcache_invalidate_done============================================= |
| |
| ; Enable MMU & D-Cache |
| Per.Set C15:0x1 %LONG (Data.Long(C15:0x1)|(0x5)) ; Enable MMU (bit0) and Dcache (bit2) |
| |
| ;====================create_sram====================================================== |
| ; Create SRAM from L2 cache |
| ; 1. Redirect SRAM address to CESA sram |
| ; 2. Read 192K into the L2 |
| ; 3. Lock the L2 |
| ; 4. Restore CESA sram bar to default setting |
| |
| ; Keep CESA Window original values and change the CESA BAR to SRAM values |
| &savectrl=Data.Long(D:0xD0020040) ; Original value of CESA BAR Control |
| &savebar=Data.Long(D:0xD0020044) ; Original value of CESA BAR Base Address |
| Data.Set D:0xD0020040 %LONG 0x000F1991 ; New value for CESA BAR Control |
| Data.Set D:0xD0020044 %LONG 0x40000000 ; New value for CESA BAR Base Address |
| |
| ; Create an SRAM |
| &address=0x40000000 ; bit[4:0] - way, bit[31:10] - base address |
| WHILE (&address<0x40004000) |
| ( |
| ®val=Data.Long(D:&address) ; Read from SRAM CESA to the L2 |
| &address=&address+0x20 ; Increment address. 4KB*32 / (32 bytes read fetch at the time)=32K writes |
| ) |
| |
| ; ==================PLE TEST======================== |
| ; <MCR|MRC> p15, <op1>, Rd, CRn, CRm, <op2> |
| ; BIT0-3:CRn, BIT4-7:CRm, BIT8-10:<op2>, BIT12-14:<op1>, Bit16=0 (32-bit access) |
| ;Per.Set C15:0x11B %LONG 0x3FFFFF00 ; MRC p15, 0, <Rt>, c11, c1, 1; Write PLEPCR |
| ; <MCRR|MRRC> p15, <op1>, <Rd1>, <Rd2>, <CRm> |
| ; BIT0-3: -, BIT4-7:CRm, BIT8-10: -, BIT12-14:<op1>, Bit16=1 (64-bit access) |
| ; MCRR p15, 0, <Rt>,<Rt2> c11 - PLE programm new channel |
| ;Per.Set C15:0x90B0 %QUAD 0x4000000040000000 ; Length - 0x1000 words, 1 block |
| ;WAIT 1.s |
| ; <MCR|MRC> p15, <op1>, Rd, CRn, CRm, <op2> |
| ; BIT0-3:CRn, BIT4-7:CRm, BIT8-10:<op2>, BIT12-14:<op1>, Bit16=0 (32-bit access) |
| ;Per.Set C15:0x23B %LONG 0x0 ; Kill channel MCR p15, 0, <Rt>, c11, c3, 2 |
| ; ==================PLE TEST END==================== |
| |
| ; Lock all ways |
| &address=0xD0008900 ; L2 lockdown registers base - REG9_D_LOCKDOWN0 |
| WHILE (&address<=0xD000893C) ; REG9_I_LOCKDOWN7 - last lockdown register |
| ( |
| Data.Set &address %LONG 0x0000FFFF ; Lock the current way |
| &address=&address+0x4 ; Go to next way |
| ) |
| |
| ; Restore CESA Window |
| Data.Set 0xD0020040 %LONG &savectrl ; Saved value of CESA BAR Control |
| Data.Set 0xD0020044 %LONG &savebar ; Saved value of CESA BAR Base Address |
| ;====================create_sram_done================================================== |
| |
| ; Stack pointer |
| Register.Set R13 0x4003FFFC |
| |
| PRINT "Please select the bin_hdr.elf file location" |
| D.LOAD ../../bin_hdr/* |
| GO |
| WAIT 5.s |
| Break.direct |
| Per.Set C15:1 %LONG 0x00052078 ; Disable MMU |
| PRINT "Done, DRAM is ready" ; The u-boot can be loaded and executed |
| ;*************************************************************************************************************** |
| ) |
| ELSE ; Static DDR init |
| ( |
| ;*************************************************************************************************************** |
| ; 533 MHZ DDR |
| PRINT "" |
| PRINT "Starting DRAM Static initialization :" |
| |
| ; First descrease size of CS[2] to prevent overlap with 0xD0000000 |
| Data.Set 0xD00200b0 %LONG 0x000f3b11 |
| |
| ;*********************************************************************************************************** |
| IF ("&boardtype"=="db6660") |
| ( |
| ;*********************************************************************************************************** |
| ; 533 MHZ DDR |
| ; First descrease size of CS[2] to prevent overlap with 0xD0000000 |
| Data.Set 0xD00200b0 %LONG 0x000f3b11 |
| |
| ; Start DRAM init |
| ;SDRAM_CONFIG_ADDR |
| Data.Set 0xD0001400 %LONG 0x7B00c820 |
| |
| ;SDRAM_DUNIT_CTRL_LOW_ADDR |
| Data.Set 0xD0001404 %LONG 0x36301820 |
| |
| ;SDRAM_TIMING_LOW_ADDR |
| Data.Set 0xD0001408 %LONG 0x33137772 |
| |
| ;SDRAM_TIMING_HI_ADDR |
| Data.Set 0xD000140c %LONG 0x384019D5 |
| |
| ;SDRAM_ADDR_CTRL_ADDR |
| Data.Set 0xD0001410 %LONG 0x10000000 |
| Data.Set 0xD0001414 %LONG 0x00000700 |
| |
| ;DDR_CONTROLLER_CTRL_HIGH |
| Data.Set 0xD0001424 %LONG 0x60F3FF |
| |
| ;DDR_CONTROLLER_CTRL_HIGH |
| Data.Set 0xD0001428 %LONG 0x000D6720 |
| |
| ;DDR ODT Timing (High) Register |
| Data.Set 0xD000147c %LONG 0x0000B571 |
| |
| ;SDRAM_SRAM_ODT_CNTL_LOW |
| Data.Set 0xD0001494 %LONG 0x00030000 |
| |
| ;SDRAM_ODT_CONTROL |
| Data.Set 0xD000149c %LONG 0x303 |
| |
| ;AXI Control Register |
| Data.Set 0xD00014a8 %LONG 0x0 |
| |
| ;Win 0 Control Register (This value will be writen by the bin header file to register 0x20184) |
| Data.Set 0xD0001504 %LONG 0x7FFFFFE1 |
| ;Win 1 Control Register (This value will be writen by the bin header file to register 0x2018C) |
| Data.Set 0xD000150c %LONG 0x7FFFFFE5 |
| ;Win 2 Control Register (This value will be writen by the bin header file to register 0x20194) |
| Data.Set 0xD0001514 %LONG 0x0 |
| ;Win 3 Control Register (This value will be writen by the bin header file to register 0x2019C) |
| Data.Set 0xD000151c %LONG 0x0 |
| |
| ;Read Data Sample Delays Register |
| Data.Set 0xD0001538 %LONG 0x707 |
| |
| ;Read Data Ready Delays Register |
| Data.Set 0xD000153c %LONG 0x707 |
| |
| ;DDR3 MR0 Register |
| Data.Set 0xD00015d0 %LONG 0x630 |
| |
| ;DDR3 MR1 Register |
| Data.Set 0xD00015d4 %LONG 0x46 |
| |
| ;DDR3 MR2 Register |
| Data.Set 0xD00015d8 %LONG 0x8 |
| |
| ;DDR3 MR3 Register |
| Data.Set 0xD00015dC %LONG 0x0 |
| |
| ;DDR3 Rank Control Register |
| Data.Set 0xD00015e0 %LONG 0x1 |
| |
| ;ZQC Configuration Register |
| Data.Set 0xD00015e4 %LONG 0x203C18 |
| |
| ;DRAM PHY Configuration Register |
| Data.Set 0xD00015ec %LONG 0xF8000025 |
| |
| ;DRAM address and Control Driving Strenght |
| Data.Set 0xD00014c0 %LONG 0x192434E9 |
| |
| ;DRAM Data and DQS Driving Strenght |
| Data.Set 0xD00014c4 %LONG 0x192434E9 |
| |
| ;*********************************************************************************************************** |
| ) |
| ELSE IF ("&boardtype"=="rd6650") |
| ( |
| ;*********************************************************************************************************** |
| ; Start DRAM init |
| ;SDRAM_CONFIG_ADDR |
| Data.Set 0xD0001400 %LONG 0x7B004C30 |
| ;SDRAM_DUNIT_CTRL_LOW_ADDR |
| Data.Set 0xD0001404 %LONG 0x36300820 |
| ;SDRAM_TIMING_LOW_ADDR |
| Data.Set 0xD0001408 %LONG 0x3303555D |
| ;SDRAM_TIMING_HI_ADDR |
| Data.Set 0xD000140c %LONG 0x384019BF |
| ;SDRAM_ADDR_CTRL_ADDR |
| Data.Set 0xD0001410 %LONG 0x10000001 |
| Data.Set 0xD0001414 %LONG 0x00000700 |
| ;DDR_CONTROLLER_CTRL_HIGH |
| Data.Set 0xD0001424 %LONG 0x60F3FF |
| ;DDR_CONTROLLER_CTRL_HIGH |
| Data.Set 0xD0001428 %LONG 0x000C5720 |
| ;DDR ODT Timing (High) Register |
| Data.Set 0xD000147c %LONG 0x0000A471 |
| ;SDRAM_SRAM_ODT_CNTL_LOW |
| Data.Set 0xD0001494 %LONG 0x00010000 |
| ;SDRAM_ODT_CONTROL |
| Data.Set 0xD000149c %LONG 0x301 |
| ;AXI Control Register |
| Data.Set 0xD00014a8 %LONG 0x0 |
| |
| ;Win 0 Control Register (This value will be writen by the bin header file to register 0x20184) |
| Data.Set 0xD0001504 %LONG 0x1FFFFFE1 |
| ;Win 1 Control Register (This value will be writen by the bin header file to register 0x2018C) |
| Data.Set 0xD000150c %LONG 0x0 |
| ;Win 2 Control Register (This value will be writen by the bin header file to register 0x20194) |
| Data.Set 0xD0001514 %LONG 0x0 |
| ;Win 3 Control Register (This value will be writen by the bin header file to register 0x2019C) |
| Data.Set 0xD000151c %LONG 0x0 |
| |
| ;Read Data Sample Delays Register |
| Data.Set 0xD0001538 %LONG 0x6 |
| ;Read Data Ready Delays Register |
| Data.Set 0xD000153c %LONG 0xc |
| |
| ;DDR3 MR0 Register |
| Data.Set 0xD00015d0 %LONG 0x620 |
| ;DDR3 MR1 Register |
| Data.Set 0xD00015d4 %LONG 0x44 |
| ;DDR3 MR2 Register |
| Data.Set 0xD00015d8 %LONG 0x8 |
| ;DDR3 MR3 Register |
| Data.Set 0xD00015dC %LONG 0x0 |
| ;DDR3 Rank Control Register |
| Data.Set 0xD00015e0 %LONG 0x1 |
| ;ZQC Configuration Register |
| Data.Set 0xD00015e4 %LONG 0x203C18 |
| |
| ;DRAM PHY Configuration Register |
| Data.Set 0xD00015ec %LONG 0xF8000F25 |
| |
| ;DRAM address and Control Driving Strenght |
| Data.Set 0xD00014c0 %LONG 0x192424C9 |
| ;DRAM Data and DQS Driving Strenght |
| Data.Set 0xD00014c4 %LONG 0x192424C9 |
| |
| ;*********************************************************************************************************** |
| ) |
| ELSE ; rd-6660 |
| ( |
| ;*********************************************************************************************************** |
| ; Start DRAM init |
| ;SDRAM_CONFIG_ADDR |
| Data.Set 0xD0001400 %LONG 0x7B00D040 |
| ;SDRAM_DUNIT_CTRL_LOW_ADDR |
| Data.Set 0xD0001404 %LONG 0x36300820 |
| ;SDRAM_TIMING_LOW_ADDR |
| Data.Set 0xD0001408 %LONG 0x33137772 |
| ;SDRAM_TIMING_HI_ADDR |
| Data.Set 0xD000140c %LONG 0x3841199F |
| ;SDRAM_ADDR_CTRL_ADDR |
| Data.Set 0xD0001410 %LONG 0x16100011 |
| Data.Set 0xD0001414 %LONG 0x00000700 |
| ;DDR_CONTROLLER_CTRL_HIGH |
| Data.Set 0xD0001424 %LONG 0x60F3FF |
| ;DDR_CONTROLLER_CTRL_HIGH |
| Data.Set 0xD0001428 %LONG 0x000D6720 |
| ;DDR ODT Timing (High) Register |
| Data.Set 0xD000147c %LONG 0x0000B571 |
| ;SDRAM_SRAM_ODT_CNTL_LOW |
| Data.Set 0xD0001494 %LONG 0x00010000 |
| ;SDRAM_ODT_CONTROL |
| Data.Set 0xD000149c %LONG 0x301 |
| ;AXI Control Register |
| Data.Set 0xD00014a8 %LONG 0x0 |
| |
| ;Win 0 Control Register (This value will be writen by the bin header file to register 0x20184) |
| Data.Set 0xD0001504 %LONG 0x1FFFFFE1 |
| ;Win 1 Control Register (This value will be writen by the bin header file to register 0x2018C) |
| Data.Set 0xD000150c %LONG 0x7FFFFFE5 |
| ;Win 2 Control Register (This value will be writen by the bin header file to register 0x20194) |
| Data.Set 0xD0001514 %LONG 0x0 |
| ;Win 3 Control Register (This value will be writen by the bin header file to register 0x2019C) |
| Data.Set 0xD000151c %LONG 0x0 |
| |
| ;Read Data Sample Delays Register |
| Data.Set 0xD0001538 %LONG 0x6 |
| ;Read Data Ready Delays Register |
| Data.Set 0xD000153c %LONG 0xc |
| |
| ;DDR3 MR0 Register |
| Data.Set 0xD00015d0 %LONG 0x630 |
| ;DDR3 MR1 Register |
| Data.Set 0xD00015d4 %LONG 0x44 |
| ;DDR3 MR2 Register |
| Data.Set 0xD00015d8 %LONG 0x8 |
| ;DDR3 MR3 Register |
| Data.Set 0xD00015dC %LONG 0x0 |
| ;DDR3 Rank Control Register |
| Data.Set 0xD00015e0 %LONG 0x1 |
| ;ZQC Configuration Register |
| Data.Set 0xD00015e4 %LONG 0x203C18 |
| |
| ;DRAM PHY Configuration Register |
| Data.Set 0xD00015ec %LONG 0xF8000F25 |
| |
| ;DRAM address and Control Driving Strenght |
| Data.Set 0xD00014c0 %LONG 0x192424C9 |
| ;DRAM Data and DQS Driving Strenght |
| Data.Set 0xD00014c4 %LONG 0x192424C9 |
| |
| ;*********************************************************************************************************** |
| ) |
| |
| ;Enable DDR |
| Data.Set 0xD0001480 %LONG 0x1 |
| |
| ; Set Dram size 256MB for FPGA (only if using XBAR) |
| Data.Set 0xD0008c04 %LONG 0x3fff0000 |
| |
| ;set ddr_phy width |
| Data.Set 0xD00014a8 %LONG 0x00000000 |
| Data.Set 0xD0020184 %LONG 0x1fFFFFE1 |
| |
| ;FASTPASS- close XBAR window 19 (set BIT0=0 - Disabled DDR window enabled in default) |
| Data.Set 0xD00200e8 %LONG 0x0fff0e00 |
| |
| ; training |
| Data.Set 0xD00015B0 %LONG 0x80100008 |
| WAIT 1.s |
| |
| ; training |
| Data.Set 0xD00015B0 %LONG 0x80100010 |
| WAIT 1.s |
| |
| ; training |
| Data.Set 0xD00015B0 %LONG 0x80100040 |
| WAIT 1.s |
| |
| ; End DRAM init |
| PRINT "Done, DRAM is ready" ; The u-boot can be loaded and executed |
| |
| ) ; End of if &ddrbus!=3 |
| |
| ) ; End of &runmode==ddr |
| |
| |
| enddo |
