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| |
| #ifndef _INC_A375_TRAINING_STATIC_H |
| #define _INC_A375_TRAINING_STATIC_H |
| |
| /* STATIC_TRAINING - Set only if static parameters for training are set and required */ |
| /*#define STATIC_TRAINING */ |
| |
| typedef struct __mvDramTrainingInit { |
| MV_U32 reg_addr; |
| MV_U32 reg_value; |
| } MV_DRAM_TRAINING_INIT; |
| |
| MV_DRAM_TRAINING_INIT ddr3_db_88F6650[MV_MAX_DDR3_STATIC_SIZE] = |
| { |
| #if 0 |
| /*PUP RdSampleDly (+CL) Phase RL ADLL value */ |
| /* Read Leveling */ |
| /* PUP0 */ |
| {0x000016A0, 0xC0020000},/*CS0*/ |
| {0x000016A0, 0xC0060000},/*CS1*/ |
| /* PUP1 */ |
| {0x000016A0, 0xC0420000},/*CS0*/ |
| {0x000016A0, 0xC0460000},/*CS1*/ |
| |
| /* Write Leveling */ |
| /* PUP0 */ |
| {0x000016A0, 0xC0008812},/*CS0*/ |
| {0x000016A0, 0xC0048812},/*CS1*/ |
| /* PUP1 */ |
| {0x000016A0, 0xC0408812},/*CS0*/ |
| {0x000016A0, 0xC0448812},/*CS1*/ |
| |
| /* DQS ref delay*/ |
| {0x000016A0, 0xC003000f},/*CS0*/ |
| {0x000016A0, 0xC007000f},/*CS1*/ |
| |
| {0x00001538, 0x00000909}, /*Read Data Sample Delays Register */ |
| {0x0000153C, 0x00000d0d}, /*Read Data Ready Delay Register */ |
| #endif |
| /*init DRAM */ |
| {0x00001480, 0x00000001}, |
| |
| /*HW mechanizem*/ |
| /* WL training*/ |
| {0x000015B0, 0x80300008}, |
| /* Preload training pattern to DRAM*/ |
| {0x000015B0, 0x80300010}, |
| /* Read Leveling using training pattern at high frequency*/ |
| {0x000015B0, 0x80300040}, |
| |
| {0x0, 0x0} |
| }; |
| MV_DRAM_TRAINING_INIT ddr3_db_88F6660[MV_MAX_DDR3_STATIC_SIZE] = |
| { |
| #if 0 |
| /*PUP RdSampleDly (+CL) Phase RL ADLL value */ |
| /* Read Leveling */ |
| /*PUP 0 */ |
| {0x000016A0, 0xC0020119}, |
| {0x000016A0, 0xC0060119}, |
| /*PUP 1 */ |
| {0x000016A0, 0xC042011b}, |
| {0x000016A0, 0xC046011b}, |
| |
| /* Write Leveling */ |
| /*PUP 0 */ |
| {0x000016A0, 0xC000700f}, |
| {0x000016A0, 0xC004700f}, |
| /*PUP 1 */ |
| {0x000016A0, 0xC040680d}, |
| {0x000016A0, 0xC044680d}, |
| |
| /* DQS ref delay*/ |
| {0x000016A0, 0xC003000f},/*CS0*/ |
| {0x000016A0, 0xC007000f},/*CS1*/ |
| |
| {0x00001538, 0x00000909}, /*Read Data Sample Delays Register */ |
| {0x0000153C, 0x00000d0d}, /*Read Data Ready Delay Register */ |
| #endif |
| |
| /*init DRAM */ |
| {0x00001480, 0x00000001}, |
| |
| /*HW mechanizem*/ |
| /* WL training*/ |
| {0x000015B0, 0x80300008}, |
| /* Preload training pattern to DRAM*/ |
| {0x000015B0, 0x80300010}, |
| /* Read Leveling using training pattern at high frequency*/ |
| {0x000015B0, 0x80300040}, |
| |
| {0x0, 0x0} |
| }; |
| |
| |
| |
| #endif /* _INC_A375_TRAINING_STATIC_H */ |