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| *******************************************************************************/ |
| |
| #ifndef __INCmvCtrlEthCompLibh |
| #define __INCmvCtrlEthCompLibh |
| |
| #include "ctrlEnv/mvCtrlEnvSpec.h" |
| #include "mvSysEthConfig.h" |
| |
| /******************************************************************************* |
| * Ports Group Control and Status */ |
| #define MV_ETHCOMP_GOP_CTRL_STAT_REG MV_ETH_COMPLEX_BASE |
| |
| #define ETHCGCS_PORT_DP_CLK_SRC_OFFSET(port) ((port == 0) ? 13 : 14) |
| #define ETHCGCS_PORT_DP_CLK_SRC_MASK(port) (0x1 << ETHCGCS_PORT_DP_CLK_SRC_OFFSET(port)) |
| |
| #define ETHCGCS_GOP_ENABLE_DEV_OFFSET 19 |
| #define ETHCGCS_GOP_ENABLE_DEV_MASK (0x1 << ETHCGCS_GOP_ENABLE_DEV_OFFSET) |
| |
| /******************************************************************************* |
| * Ports Group Control and Status */ |
| #define MV_ETHCOMP_GBE_PHY_CLOCK_CTRL_REG (MV_ETH_COMPLEX_BASE + 0x1C) |
| |
| #define ETHCC_GBE_PHY_P4_SW_TO_MPP_EDGE_OFFSET 23 |
| #define ETHCC_GBE_PHY_P4_SW_TO_MPP_EDGE_MASK (0x1 << ETHCC_GBE_PHY_P4_SW_TO_MPP_EDGE_OFFSET) |
| |
| #define ETHCC_GBE_PHY_GBE_P0_TO_MPP_EDGE_OFFSET 28 |
| #define ETHCC_GBE_PHY_GBE_P0_TO_MPP_EDGE_MASK (0x1 << ETHCC_GBE_PHY_GBE_P0_TO_MPP_EDGE_OFFSET) |
| |
| /******************************************************************************* |
| * Ethernet Complex Control 0 */ |
| #define MV_ETHCOMP_CTRL_REG (MV_ETH_COMPLEX_BASE + 0x10) |
| |
| #define ETHCC_SW_PORT_SRC_OFFSET(port) (port == 0 ? 4 : (port == 3 ? 5 : \ |
| (port == 4 ? 6 : (port == 6 ? 7 : 4)))) |
| #define ETHCC_SW_PORT_SRC_MASK(port) (0x1 << ETHCC_SW_PORT_SRC_OFFSET(port)) |
| |
| enum mvSwPortSrc { |
| ETHC_SW_PORT_SRC_NC, |
| ETHC_SW_PORT_SRC_GBE_MAC, |
| ETHC_SW_PORT_SRC_MPP, |
| ETHC_SW_PORT_SRC_GBE_PHY, |
| }; |
| |
| #define ETHCC_GBE_MAC_SRC_OFFSET(port) (port == 0 ? 10 : (port == 1 ? 12 : 10)) |
| #define ETHCC_GBE_MAC_SRC_MASK(port) (0x3 << ETHCC_GBE_MAC_SRC_OFFSET(port)) |
| |
| #define ETHCC_GBE_PHY_PORT_SMI_SRC_OFFSET(port) (port == 0 ? 20 : (port == 1 ? 15 : \ |
| (port == 2 ? 16 : (port == 3 ? 21 : 4)))) |
| #define ETHCC_GBE_PHY_PORT_SMI_SRC_MASK(port) (0x1 << ETHCC_GBE_PHY_PORT_SMI_SRC_OFFSET(port)) |
| |
| #define ETHCC_GBE_PHY_PORT_SRC_OFFSET(phy) ((phy >= 0 && phy <= 3) ? 14 + phy : 14) |
| #define ETHCC_GBE_PHY_PORT_SRC_MASK(phy) (0x1 << ETHCC_GBE_PHY_PORT_SRC_OFFSET(phy)) |
| |
| #define ETHCC_GE_MAC0_SW_PORT_6_SPEED_OFFSET 18 |
| #define ETHCC_GE_MAC0_SW_PORT_6_SPEED_MASK (0x1 << ETHCC_GE_MAC0_SW_PORT_6_SPEED_OFFSET) |
| |
| #define ETHCC_LOOPBACK_PORT_SPEED_OFFSET 19 |
| #define ETHCC_LOOPBACK_PORT_SPEED_MASK (0x1 << ETHCC_LOOPBACK_PORT_SPEED_OFFSET) |
| |
| #define ETHCC_SW_OUT_CLOCK_IN_SRC_OFFSET 26 |
| #define ETHCC_SW_OUT_CLOCK_IN_SRC_MASK (0x1 << ETHCC_SW_OUT_CLOCK_IN_SRC_OFFSET) |
| |
| /******************************************************************************* |
| * Switch Configuration and Reset Control |
| */ |
| #define MV_ETHCOMP_SW_CONFIG_RESET_CTRL (MV_ETH_COMPLEX_BASE + 0x30) |
| |
| #define ETHSCRC_SWITCH_RESET_OFFSET 0 |
| #define ETHSCRC_SWITCH_RESET_MASK (0x1 << ETHSCRC_SWITCH_RESET_OFFSET) |
| |
| #define ETHSCRC_PORT_2G_SELECT_OFFSET 14 |
| #define ETHSCRC_PORT_2G_SELECT_MASK (0x1 << ETHSCRC_PORT_2G_SELECT_OFFSET) |
| |
| /******************************************************************************* |
| * GbE PHY <<%n>> Control 0. |
| * 0x000189A0 + n*4: where n (0-3) represents GPHY_Num. |
| */ |
| #define MV_ETHCOMP_GBE_PHY_CTRL0_REG(phy) (MV_ETH_COMPLEX_BASE + 0xA0 + (phy * 0x4)) |
| |
| #define ETHCGPC0_PCS_PHY_ADDR_OFFSET 13 |
| #define ETHCGPC0_PCS_PHY_ADDR_MASK (0x1F << ETHCGPC0_PCS_PHY_ADDR_OFFSET) |
| |
| /******************************************************************************* |
| * GbE PHY <<%n>> Control 1. |
| * 0x000189B0 + n*4: where n (0-3) represents GPHY_Num. |
| */ |
| #define MV_ETHCOMP_GBE_PHY_CTRL1_REG(phy) (MV_ETH_COMPLEX_BASE + 0xB0 + (phy * 0x4)) |
| |
| #define ETHCGPC1_PHY_POWER_DOWN_OFFSET 10 |
| #define ETHCGPC1_PHY_POWER_DOWN_MASK (0x3 << ETHCGPC1_PHY_POWER_DOWN_OFFSET) |
| |
| #define ETHCGPC1_PS_ENA_XCS_OFFSET 12 |
| #define ETHCGPC1_PS_ENA_XCS_MASK (0x3 << ETHCGPC1_PS_ENA_XCS_OFFSET) |
| |
| #define ETHCGPC1_PD_CFG_EDED_A_OFFSET 14 |
| #define ETHCGPC1_PD_CFG_EDED_A_MASK (0x7 << ETHCGPC1_PD_CFG_EDED_A_OFFSET) |
| |
| /******************************************************************************* |
| * Quad GbE PHY Common Control and Status |
| */ |
| #define MV_ETHCOMP_QUAD_GBE_PHY_CTRL_STAT_REG (MV_ETH_COMPLEX_BASE + 0xD0) |
| |
| #define ETHQPCS_RESET_OFFSET 0 |
| #define ETHQPCS_RESET_MASK (0x1 << ETHQPCS_DPLL_RESET_OFFSET) |
| |
| #define ETHQPCS_DPLL_RESET_OFFSET 4 |
| #define ETHQPCS_DPLL_RESET_MASK (0x1 << ETHQPCS_DPLL_RESET_OFFSET) |
| |
| /******************************************************************************* |
| * GPON PHY Contol 1 |
| */ |
| #define MV_GPON_PHY_CTRL1_REG (MV_IP_CONFIG_REGS_OFFSET + 0xF8) |
| |
| #define GPON_PHY_CTRL1_OFFSET 0 |
| #define GPON_PHY_CTRL1_MASK (0x1 << GPON_PHY_CTRL1_OFFSET) |
| |
| /******************************************************************************* |
| * Port Auto-Negotiation Configuration |
| */ |
| #define MV_ETH_IN_BAND_AN_EN_OFFSET 2 |
| #define MV_ETH_IN_BAND_AN_EN_MASK (1 << MV_ETH_IN_BAND_AN_EN_OFFSET) |
| |
| #define MV_ETH_SPEED_AUTO_NEG_OFFSET 7 |
| #define MV_ETH_SPEED_AUTO_NEG_MASK (1 << MV_ETH_SPEED_AUTO_NEG_OFFSET) |
| |
| #define MV_ETH_FLOW_CTRL_AUTO_NEG_OFFSET 11 |
| #define MV_ETH_FLOW_CTRL_AUTO_NEG_MASK (1 << MV_ETH_FLOW_CTRL_AUTO_NEG_OFFSET) |
| |
| #define MV_ETH_DUPLEX_AUTO_NEG_OFFSET 13 |
| #define MV_ETH_DUPLEX_AUTO_NEG_MASK (1 << MV_ETH_DUPLEX_AUTO_NEG_OFFSET) |
| |
| #ifdef CONFIG_MV_ETH_PP2 |
| MV_STATUS mvEthComplexInit(MV_U32 ethCompConfig); |
| void mvEthComplexGphyPortSmiSrcSet(MV_U32 phy, MV_U32 src); |
| #else |
| MV_STATUS mvEthComplexInit(MV_U32 ethCompConfig) { /* empty */ } |
| #endif |
| |
| #endif /* __INCmvCtrlEthCompLibh */ |
