commit a75a5c01285b16422094739d9f4934e868058761
author hayim <hayim@marvell.com> Tue Oct 20 10:50:57 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree 10514412c8a4d0adf6b8ea9d36a83cbde846325b
parent 0476bf3eb06a58b764a0c58fd6e74ec4e23e4ad5

ddr3libv2: fix: increas ODPG polling (again) x10 for DDR4

    the reason for the delay in the machine is because there
    is a jitter and it causes the machine to scan specific
    areas (which have jitter) man times

Change-Id: I6de1d1bd02d58192ada84e976df78265559809a8
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24076
Reviewed-on: http://vgitil04.il.marvell.com:8080/24177
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
index 8d8045a..b51d5c0 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
@@ -307,13 +307,13 @@
 GT_U32                      trainCsNum;
 GT_U32                      trainIfAcess, trainIfId, trainPupAccess;
 #ifdef CONFIG_DDR4
-GT_U32                      maxPollingForDone = 10000000;  /* this counter was increased for DDR4
-                                                              due to A390 DB-GP DDR4 failure */
+GT_U32                      maxPollingForDone = 100000000;  /* this counter was increased for DDR4
+                                                               due to A390 DB-GP DDR4 failure */
 #else /* DDR3 */
 #ifdef CONFIG_BOBK
 GT_U32                      maxPollingForDone = 1000;
 #else
-GT_U32                      maxPollingForDone = 1000000; 
+GT_U32                      maxPollingForDone = 1000000;
 #endif /* CONFIG_BOBK */
 #endif /* CONFIG_DDR4 */
 extern MV_HWS_RESULT trainingResult[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];