commit a3bfddc663cfe472211662852ba262ea27a8c2b8
author Margarita Granov <margra@marvell.com> Wed Sep 02 10:41:13 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree 26e3fcae4af3648c30385e57e41afa467c4d2f7c
parent 8f29cd157652aca9ae083c7505b9df96b00b2a96

fix: ddr3libv2: bobk: Fix CPSS compilation warnings for TM functionality.

Change-Id: I7931c499d19207bd18c0dc0060a79178a76a985b
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/23368
Reviewed-by: Haim Boot <hayim@marvell.com>
Tested-by: Haim Boot <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24159
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
index 81287df..2e035f3 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -93,7 +93,7 @@
 static GT_STATUS ddr3TipTmSetDivider
 (
 	GT_U8							devNum,
-	GT_U8                			interfaceId,
+	GT_U32                			interfaceId,
     MV_HWS_DDR_FREQ                 frequency
 );
 
@@ -807,6 +807,9 @@
     GT_BOOL  enable
 )
 {
+    /* avoid warnings */
+    devNum =devNum;
+    enable = enable;
     return GT_OK;
 }
 
@@ -1257,7 +1260,7 @@
 static GT_STATUS ddr3TipTmSetDivider
 (
 	GT_U8							devNum,
-	GT_U8							interfaceId,
+	GT_U32							interfaceId,
     MV_HWS_DDR_FREQ                 frequency
 )
 {
@@ -1266,6 +1269,8 @@
 
 	DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("TM PLL Config\n"));
 
+    /* avoid warnings */
+    interfaceId = interfaceId;
     /* Calc SAR */
    /*CHECK_STATUS(ddr3TipTmGetInitFreq(devNum, &sarFreq));*/
     /* calc SAR */