commit 9f3d8138d02a52e545b25a51d36b5f483abc7c44
author hayim <hayim@marvell.com> Mon Oct 19 16:28:36 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree 654fbf883cc06db22f9be257b7c64f1693e31834
parent 173e5c012da87de1a191f8ae90bb2e256c02c622

ddr3libv2: a38x: fix 16 bit with ecc DB GP DDR failure

    - DB GP failed on 16 configuration with ECC.
    - implemented JIRA #1498
    - change DQ result reg mapping so when working with PUP 3 ECC,
      when masking PUP 4, PUP 3 bits will be masked (since the results
      are read from PUP 4)

Change-Id: If91a69a00789dd75cead5fef7bf16d7c9173e519
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24068
Reviewed-on: http://vgitil04.il.marvell.com:8080/24175
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
index 55b429c..8d8045a 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
@@ -69,8 +69,8 @@
     RESULT_CONTROL_PUP_2_BIT_4_REG, RESULT_CONTROL_PUP_2_BIT_5_REG, RESULT_CONTROL_PUP_2_BIT_6_REG, RESULT_CONTROL_PUP_2_BIT_7_REG,
     RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG, RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
     RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG, RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
-    RESULT_CONTROL_PUP_4_BIT_0_REG, RESULT_CONTROL_PUP_4_BIT_1_REG, RESULT_CONTROL_PUP_4_BIT_2_REG, RESULT_CONTROL_PUP_4_BIT_3_REG,
-    RESULT_CONTROL_PUP_4_BIT_4_REG, RESULT_CONTROL_PUP_4_BIT_5_REG, RESULT_CONTROL_PUP_4_BIT_6_REG, RESULT_CONTROL_PUP_4_BIT_7_REG,
+    RESULT_CONTROL_PUP_3_BIT_0_REG, RESULT_CONTROL_PUP_3_BIT_1_REG, RESULT_CONTROL_PUP_3_BIT_2_REG, RESULT_CONTROL_PUP_3_BIT_3_REG,
+    RESULT_CONTROL_PUP_3_BIT_4_REG, RESULT_CONTROL_PUP_3_BIT_5_REG, RESULT_CONTROL_PUP_3_BIT_6_REG, RESULT_CONTROL_PUP_3_BIT_7_REG,
 };
 
 GT_U16   maskResultsPupRegMapPup3ECC[] =

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
index cdf4c6c..dcee61b 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
@@ -847,6 +847,12 @@
 			}
 			else
 			{
+                #if defined(CONFIG_ARMADA_38X) /* JIRA #1498 for 16 bit with ECC */
+                if(topologyMap->activeBusMask == 0xB)
+                {
+                    break;
+                }
+                #endif
 				CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_TRIGGER_REG, dataRead, (1 << 2)));
 				if (dataRead[interfaceId] != 0)
 				{
@@ -867,6 +873,13 @@
 			{
 				CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, ODPG_TRAINING_STATUS_REG, dataRead, (1 << 2)));
 				regData = dataRead[interfaceId];
+                #if defined(CONFIG_ARMADA_38X) /* JIRA #1498 for 16 bit with ECC */
+                if(topologyMap->activeBusMask == 0xB)
+                {
+                    /* set data to 0 in order to skip the check */
+                    regData = 0;
+                }
+                #endif
 				if (regData != 0)
 				{
 					DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("WL 2:  WL failed IF %d regData=0x%x\n",interfaceId,regData));