commit 9ea0193403a83378b4db5e8a4c92181bae266cf5
author Margarita Granov <margra@marvell.com> Sun Oct 18 14:48:32 2015 +0200
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree adc382003af0198cd7fbaf7cd749b411912fbdf2
parent 111e9793221efc79084535fac13586a2ff237804

fix: ddr3libv2: bobk: fix CPSS compilation warnings in CPU set divider.

Change-Id: If20981375886b3044427deca729fcaf7f0aa7357
Signed-off-by: Margarita Granov <margra@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24053
Reviewed-by: Haim Boot <hayim@marvell.com>
Tested-by: Haim Boot <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24172
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
index f1aca0d..d4388dc 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -101,7 +101,7 @@
 static GT_STATUS ddr3TipCpuSetDivider
 (
 	GT_U8							devNum,
-	GT_U8                			interfaceId,
+	GT_U32                			interfaceId,
     MV_HWS_DDR_FREQ                 frequency
 );
 
@@ -1363,7 +1363,7 @@
 static GT_STATUS ddr3TipCpuSetDivider
 (
 	GT_U8							devNum,
-	GT_U8							interfaceId,
+	GT_U32							interfaceId,
     MV_HWS_DDR_FREQ                 frequency
 )
 {