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| *******************************************************************************/ |
| |
| #ifndef _INC_A370_CONFIG_H |
| #define _INC_A370_CONFIG_H |
| |
| /*DDR3_LOG_LEVEL Information |
| Level 0: Provides an error code in a case of failure, RL, WL errors and other algorithm failure |
| Level 1: Provides the D-Unit setup (SPD/Static configuration) |
| Level 2: Provides the windows margin as a results of DQS centeralization |
| Level 3: Provides the windows margin of each DQ as a results of DQS centeralization */ |
| |
| #define DDR3_LOG_LEVEL 0 |
| #define DDR3_PBS 0 |
| /* this flag allows the execution of SW WL/RL oppon HW failure */ |
| #define DDR3_RUN_SW_WHEN_HW_FAIL 1 |
| |
| /* General Configurations */ |
| /* The following parameters are required for proper setup */ |
| /* DRAM_ECC - Must be set to FALSE */ |
| /* DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board */ |
| /* DDR3_TRAINING_DEBUG - debug prints of internal code */ |
| /* A370_A0 - must be defined if using Marvell DB board and A370 A0 device otherwise dont care */ |
| #define DUNIT_STATIC |
| #define DRAM_ECC FALSE |
| #undef DQS_CLK_ALIGNED |
| #define DDR3_TRAINING_DEBUG FALSE |
| #undef A370_A0 |
| #define REG_DIMM_SKIP_WL TRUE |
| |
| /* Marvell boards specific configurations */ |
| #if defined(DB_88F6710_PCAC) |
| #define STATIC_TRAINING |
| #endif |
| |
| #if defined(DB_88F6710) && !defined(A370_A0) |
| #define AUTO_DETECTION_SUPPORT |
| #define SPD_SUPPORT |
| #define DRAM_2T 0x0 |
| #define DIMM_CS_BITMAP 0xF |
| #define DUNIT_SPD |
| #undef DUNIT_STATIC |
| #endif |
| |
| #endif /* _INC_A370_CONFIG_H */ |
