ddr3libv2: bobk: Presilicon debug fixes
Fixed attributes and ifdefs to be as in AC3
Fixed getFreq functions to be as in AC3
Fixed training stages( Controller init called in main flow)
Opened Server access init
Change-Id: I5a0511edc65d6b9724e2574e8c160865bfa3f16a
Signed-off-by: Igor Patrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/21996
Tested-by: Star_Automation <star@marvell.com>
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Reviewed-by: Haim Boot <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24137
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
index 9955dd3..d258cfc 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Driver/ddr3/mvDdr3TrainingIpFlow.h
@@ -131,7 +131,7 @@
#define DISABLE_DDR_TUNING_DATA (0x02294285)
#define ENABLE_DDR_TUNING_DATA (0x12294285)
-#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
+#if !defined(CONFIG_BOBCAT2)
#define ODPG_TRAINING_STATUS_REG (0x18488)
#else
#define ODPG_TRAINING_STATUS_REG (0x1030)
@@ -205,7 +205,7 @@
#define CS_ENABLE_REG (0x16D8)
#define WR_LEVELING_DQS_PATTERN_REG (0x16DC)
-#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
+#if !defined(CONFIG_BOBCAT2)
#define ODPG_BIST_DONE (0x186D4)
#else
#define ODPG_BIST_DONE (0x16FC)
@@ -214,7 +214,7 @@
#define ODPG_BIST_DONE_BIT_VALUE_REV2 (1)
#define ODPG_BIST_DONE_BIT_VALUE_REV3 (0)
-#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
+#if !defined(CONFIG_BOBCAT2)
#define RESULT_CONTROL_BYTE_PUP_0_REG (0x1830)
#define RESULT_CONTROL_BYTE_PUP_1_REG (0x1834)
#define RESULT_CONTROL_BYTE_PUP_2_REG (0x1838)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 64ef502..d8555c3 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -597,11 +597,13 @@
/*Pad calibration control - enable*/
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, CALIB_MACHINE_CTRL_REG, 0x1, 0x1));
-#if !defined(CONFIG_ARMADA_38X) && !defined(CONFIG_ALLEYCAT3) && !defined (CONFIG_ARMADA_39X)
- /* DDR3_Rank_Control \96 Part of the Generic code */
- /*: CS1 Mirroring enable + w/a for JIRA DUNIT-14581 */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, RANK_CTRL_REG, 0x27, MASK_ALL_BITS));
-#endif
+
+ if (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) < MV_TIP_REV_3){
+ /* DDR3_Rank_Control \96 Part of the Generic code */
+ /*: CS1 Mirroring enable + w/a for JIRA DUNIT-14581 */
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, RANK_CTRL_REG, 0x27, MASK_ALL_BITS));
+ }
+
csMask = 0;
dataValue = 0x7;
/* Address ctrl \96 Part of the Generic code
@@ -670,12 +672,14 @@
ddr3TipWriteOdt(devNum, accessType, interfaceId, clValue, cwlVal);
ddr3TipSetTiming(devNum, accessType, interfaceId, freq);
-#if !defined(CONFIG_ARMADA_38X) && !defined(CONFIG_ALLEYCAT3) && !defined (CONFIG_ARMADA_39X)
- /*WrBuff, RdBuff*/
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, DUNIT_CONTROL_HIGH_REG, 0x1000119,0x100017F));
-#else
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, DUNIT_CONTROL_HIGH_REG, 0x177,0x1000177));
-#endif
+ if (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) < MV_TIP_REV_3){
+ /*WrBuff, RdBuff*/
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, DUNIT_CONTROL_HIGH_REG, 0x1000119,0x100017F));
+ }
+ else{
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, DUNIT_CONTROL_HIGH_REG, 0x177,0x1000177));
+ }
+
if (initCntrPrm->isCtrl64Bit)
{
/* disable 0.25 cc delay */
@@ -712,7 +716,7 @@
/*Set Active control for ODT write transactions*/
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, 0x1494, uiODTConfig, MASK_ALL_BITS));
-#if defined (CONFIG_ALLEYCAT3)
+#if defined (CONFIG_ALLEYCAT3) || defined(CONFIG_BOBK)
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, 0x14a8, 0x900,0x900));
/*WA: Controls whether to float The Control pups outputs during Self Refresh*/
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, 0x16d0, 0,0x8000));
@@ -802,7 +806,7 @@
/*****************************************************************************
RANK Control Flow
******************************************************************************/
-#if !defined(CONFIG_ARMADA_38X) && !defined (CONFIG_ARMADA_39X) && !defined(CONFIG_ALLEYCAT3)
+#if defined(CONFIG_BOBCAT2)
static GT_STATUS ddr3TipRankControl(GT_U32 devNum, GT_U32 interfaceId)
{
GT_U32 dataValue = 0, busCnt= 0;
@@ -834,10 +838,7 @@
}
}
}
-#if !defined(CONFIG_ALLEYCAT3)
- /* jirra CS2 exist */
- dataValue |= (1 << CS2_EXIST_BIT);
-#endif
+
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, RANK_CTRL_REG, dataValue, 0xFF));
return GT_OK;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingBist.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingBist.c
index 08e99d5..ecff52a 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingBist.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingBist.c
@@ -123,19 +123,20 @@
{
CHECK_STATUS(mvHwsDdr3TipIFRead(devNum,ACCESS_TYPE_UNICAST, ifNum, ODPG_BIST_DONE, readData, MASK_ALL_BITS));
dataValue = readData[interfaceNum];
-#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
- if ((dataValue & 0x1) == 0x0)/*in SOC type devices this bit is self clear so, if it was cleared all good*/
- break;
-#else
- if ((dataValue & 0x1) == 0x1)
- {
- if (isBistResetBit != 0)
- {
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,ACCESS_TYPE_UNICAST, ifNum, ODPG_BIST_DONE, (dataValue & 0xFFFFFFFE), MASK_ALL_BITS));
- }
- break;
- }
-#endif
+ if (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3){
+ if ((dataValue & 0x1) == 0x0)/*in SOC type devices this bit is self clear so, if it was cleared all good*/
+ break;
+ }
+ else{
+ if ((dataValue & 0x1) == 0x1)
+ {
+ if (isBistResetBit != 0)
+ {
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,ACCESS_TYPE_UNICAST, ifNum, ODPG_BIST_DONE, (dataValue & 0xFFFFFFFE), MASK_ALL_BITS));
+ }
+ break;
+ }
+ }
}
if (pollCnt >= MaxPoll)
{
@@ -262,19 +263,21 @@
if (operType == BIST_STOP)
{
-#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_BIST_DONE, (1 << 8), (1 << 8)));
-#else
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_DATA_CONTROL_REG, (1 << 30) , (GT_U32)(0x3 << 30)));
-#endif
+ if (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3){
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_BIST_DONE, (1 << 8), (1 << 8)));
+ }
+ else{
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_DATA_CONTROL_REG, (1 << 30) , (GT_U32)(0x3 << 30)));
+ }
}
else
{
-#if defined(CONFIG_ARMADA_38X) || defined (CONFIG_ALLEYCAT3) || defined (CONFIG_ARMADA_39X)
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_BIST_DONE, 1, 1));
-#else
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_DATA_CONTROL_REG, (GT_U32)(1 << 31), (GT_U32)(1 << 31)));
-#endif
+ if (ddr3TipDevAttrGet(devNum, MV_ATTR_TIP_REV) >= MV_TIP_REV_3){
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_BIST_DONE, 1, 1));
+ }
+ else{
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, ODPG_DATA_CONTROL_REG, (GT_U32)(1 << 31), (GT_U32)(1 << 31)));
+ }
}
return GT_OK;
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
index 0db5b8a..3d8378f 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3BobK.c
@@ -240,7 +240,7 @@
/* Bit mapping (for PBS) */
GT_U32 bobKDQbitMap2Phypin[] =
{
-/*#warning "DQ mapping not updated!" !!!*/
+#warning "DQ mapping not updated!" !!!
/* Interface 0 */
8, 1, 0, 7, 9, 2, 3, 6 , /* dq[0:7] */
8, 1, 6, 3, 9, 7, 2, 0 , /* dq[8:15] */
@@ -761,18 +761,6 @@
GT_BOOL enable
)
{
- GT_U32 uiReg;
- uiReg = MV_REG_READ(CS_ENABLE_REG);
-
- if (enable)
- {
- uiReg |= (1 << 6);
- }
- else
- {
- uiReg &= ~(1 << 6);
- }
- MV_REG_WRITE(CS_ENABLE_REG, uiReg);
return GT_OK;
}
@@ -792,6 +780,7 @@
MV_HWS_TIP_CONFIG_FUNC_DB configFunc;
MV_HWS_TOPOLOGY_MAP* topologyMap = ddr3TipGetTopologyMap(devNum);
GT_TUNE_TRAINING_PARAMS tuneParams;
+ GT_U8 numOfBusPerInterface = 5;
if(topologyMap == NULL)
{
@@ -826,29 +815,30 @@
/*Set device attributes*/
ddr3TipDevAttrInit(devNum);
- ddr3TipDevAttrSet(devNum, MV_ATTR_TIP_REV, MV_TIP_REV_2);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_TIP_REV, MV_TIP_REV_3);
ddr3TipDevAttrSet(devNum, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_NEGATIVE);
- ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, NUMBER_OF_PUP);
- /*ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);*/
+ ddr3TipDevAttrSet(devNum, MV_ATTR_OCTET_PER_INTERFACE, numOfBusPerInterface);
+ ddr3TipDevAttrSet(devNum, MV_ATTR_INTERLEAVE_WA, GT_FALSE);
- maskTuneFunc = ( INIT_CONTROLLER_MASK_BIT |
- SET_MEDIUM_FREQ_MASK_BIT |
- WRITE_LEVELING_MASK_BIT |
- LOAD_PATTERN_2_MASK_BIT |
- READ_LEVELING_MASK_BIT |
- PBS_RX_MASK_BIT |
- PBS_TX_MASK_BIT |
- SET_TARGET_FREQ_MASK_BIT |
- WRITE_LEVELING_TF_MASK_BIT |
- READ_LEVELING_TF_MASK_BIT |
- WRITE_LEVELING_SUPP_TF_MASK_BIT |
- CENTRALIZATION_RX_MASK_BIT |
- CENTRALIZATION_TX_MASK_BIT);
+ maskTuneFunc = (SET_LOW_FREQ_MASK_BIT |
+ LOAD_PATTERN_MASK_BIT |
+ SET_MEDIUM_FREQ_MASK_BIT |
+ WRITE_LEVELING_MASK_BIT |
+ WRITE_LEVELING_SUPP_MASK_BIT |
+ READ_LEVELING_MASK_BIT |
+ PBS_RX_MASK_BIT |
+ PBS_TX_MASK_BIT |
+ SET_TARGET_FREQ_MASK_BIT |
+ WRITE_LEVELING_TF_MASK_BIT |
+ WRITE_LEVELING_SUPP_TF_MASK_BIT |
+ READ_LEVELING_TF_MASK_BIT |
+ CENTRALIZATION_RX_MASK_BIT |
+ CENTRALIZATION_TX_MASK_BIT
+ );
/*Skip mid freq stages for 400Mhz DDR speed*/
if( (topologyMap->interfaceParams[firstActiveIf].memoryFreq == DDR_FREQ_400) ){
- maskTuneFunc = (INIT_CONTROLLER_MASK_BIT |
- WRITE_LEVELING_MASK_BIT |
+ maskTuneFunc = ( WRITE_LEVELING_MASK_BIT |
LOAD_PATTERN_2_MASK_BIT |
READ_LEVELING_MASK_BIT |
CENTRALIZATION_RX_MASK_BIT |
@@ -874,18 +864,16 @@
tuneParams.gZnodtData = 45;
tuneParams.gZpodtCtrl = 45;
tuneParams.gZnodtCtrl = 45;
+ tuneParams.gRttWR = 0x0;
CHECK_STATUS(ddr3TipTuneTrainingParams(devNum, &tuneParams));
/* frequency and general parameters */
ddr3TipBobKGetMediumFreq(devNum, firstActiveIf, &mediumFreq);
initFreq = topologyMap->interfaceParams[firstActiveIf].memoryFreq;
- dfsLowFreq = 100;
+ freqVal[DDR_FREQ_LOW_FREQ] = dfsLowFreq = 130;
dfsLowPhy1 = PhyReg1Val;
- isPllBeforeInit = 0;
- useBroadcast = GT_FALSE; /* multicast */
- isCbeRequired = GT_TRUE;
- calibrationUpdateControl = 2;
+ calibrationUpdateControl = 1;
return GT_OK;
}
@@ -1429,38 +1417,37 @@
MV_HWS_DDR_FREQ *freq
)
{
- GT_U32 data;
+ GT_U32 data;
/* calc SAR */
- CHECK_STATUS(ddr3TipBobKRead(devNum, 0x000F8204 , &data, MASK_ALL_BITS ));
- data = (data >> 18) & 0x7;
-#ifdef ASIC_SIMULATION
- data = 3;
-#endif
+ CHECK_STATUS(ddr3TipBobKServerRegRead(devNum, REG_DEVICE_SAR1_ADDR, &data, MASK_ALL_BITS ));
+ mvPrintf("SAR1 is 0x%X\n", data);
+ data = (data >> PLL1_CNFIG_OFFSET) & PLL1_CNFIG_MASK;
switch(data)
{
case 0:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("MSYS DDR_FREQ_400\n"));
+ case 5:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("DDR_FREQ_400\n"));
*freq = DDR_FREQ_400;
break;
-
+ case 1:
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("DDR_FREQ_533\n"));
+ *freq = DDR_FREQ_533;
+ break;
case 2:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("MSYS DDR_FREQ_667\n"));
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("DDR_FREQ_667\n"));
*freq = DDR_FREQ_667;
break;
-
case 3:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("MSYS DDR_FREQ_800\n"));
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("DDR_FREQ_800\n"));
*freq = DDR_FREQ_800;
break;
-
default:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Error: ddr3TipCpuGetInitFreq: Unknown SAR value 0x%x\n", data));
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("Freq SAR Unknown\n"));
*freq = DDR_FREQ_LIMIT;
return GT_BAD_PARAM;
}
-
return GT_OK;
}
@@ -1478,35 +1465,28 @@
MV_HWS_DDR_FREQ *freq
)
{
- GT_U32 sarFreq;
+ GT_U32 data;
- CHECK_STATUS(ddr3TipBobKRead((GT_U8)devNum, interfaceId, &sarFreq, MASK_ALL_BITS));
+ /* calc SAR */
+ CHECK_STATUS(ddr3TipBobKRead(devNum, REG_DEVICE_SAR1_ADDR, &data, MASK_ALL_BITS ));
+ data = (data >> PLL1_CNFIG_OFFSET) & PLL1_CNFIG_MASK;
- switch(sarFreq)
+ switch(data)
{
- case DDR_FREQ_400:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("No medium freq supported for 400Mhz\n"));
+ case 0:
+ case 5:
*freq = DDR_FREQ_400;
break;
-
- case DDR_FREQ_667:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("Medium DDR_FREQ_333\n"));
+ case 2:
*freq = DDR_FREQ_333;
break;
-
- case DDR_FREQ_800:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("Medium DDR_FREQ_400\n"));
+ case 3:
*freq = DDR_FREQ_400;
break;
-
- case DDR_FREQ_933:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_TRACE, ("Medium DDR_FREQ_311\n"));
- *freq = DDR_FREQ_311;
- break;
-
default:
- DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, ("Error: ddr3TipBobKGetMediumFreq: Freq %d is not supported\n", sarFreq));
- return GT_FAIL;
+ DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_INFO, ("Freq SAR Unknown\n"));
+ *freq = DDR_FREQ_LIMIT;
+ return GT_BAD_PARAM;
}
return GT_OK;
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_hws_hw_training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_hws_hw_training.c
index 9ef879a..be3b0e8 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_hws_hw_training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_hws_hw_training.c
@@ -122,12 +122,12 @@
}
initParam.doMrsPhy = GT_TRUE;
-#if defined (CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+#if !defined (CONFIG_BOBCAT2)
initParam.isCtrl64Bit = GT_FALSE;
#else
initParam.isCtrl64Bit = GT_TRUE;
#endif
-#if defined (CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+#if !defined (CONFIG_BOBCAT2)
initParam.initPhy = GT_TRUE;
#else
initParam.initPhy = GT_FALSE;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_msys_bobk_training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_msys_bobk_training.c
index 81a7a80..9d3cc9e 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_msys_bobk_training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Soc/ddr3_msys_bobk_training.c
@@ -30,10 +30,8 @@
/************************** globals ***************************************/
-#if 0
extern MV_SERVER_REG_ACCESS_SET hwsServerRegSetFuncPtr;
extern MV_SERVER_REG_ACCESS_GET hwsServerRegGetFuncPtr;
-#endif
GT_U32 serverBaseAddr = 0;
/* the following global variables are set in ddr3TipDynamicReadLeveling */
@@ -105,7 +103,6 @@
/***************************************************************************/
-#if 0
/******************************************************************************
* Name: serverRegSet.
* Desc: definition of server write prototype
@@ -156,17 +153,13 @@
return GT_OK;
}
-#endif
-
MV_STATUS ddr3SiliconPreInit(void)
{
MV_STATUS status;
MV_U8 devNum = 0;
-#if 0
/* initialize window to server */
configureServerWindows();
-#endif
if (ddr3GetSdramAssignment(devNum) == TM_EN) {
mvPrintf("Error: DDR3 interface is used by Traffic Manager\n", 0);
@@ -187,31 +180,11 @@
return status;
}
- CHECK_STATUS(ddr3TipBobKSelectCPUDdrController(0, GT_FALSE)); // set mux to msys
-
- /* configure Dunit */
- status = ddr3DunitAccessInit(0, 1);
- if (MV_OK != status) {
- mvPrintf("DDR3 Dunit Access Init - FAILED 0x%x\n", status);
- return status;
- }
return MV_OK;
}
-MV_STATUS ddr3SiliconPostInit(void)
+MV_STATUS ddr3SiliconPostInit(void)
{
- MV_STATUS status;
-
-
- status = ddr3SiliconInit();
- if (MV_OK != status) {
- mvPrintf("DDR3 silicon init - FAILED 0x%x\n", status);
- return status;
- }
-
-
- CHECK_STATUS(ddr3TipBobKSelectCPUDdrController(0, GT_TRUE)); // set mux to tip
-
return MV_OK;
}
@@ -352,11 +325,9 @@
serverBaseAddr = MV_REG_READ(REG_XBAR_WIN_5_BASE_ADDR);
-#if 0
/* init server access */
hwsServerRegSetFuncPtr = serverRegSet;
hwsServerRegGetFuncPtr = serverRegGet;
-#endif
configDone = MV_TRUE;
}
