| commit | 76df89cd730acd229bc904767c0d153c5b2c748a | [log] [tgz] |
|---|---|---|
| author | hayim <hayim@marvell.com> | Sun Nov 15 15:22:31 2015 +0200 |
| committer | Greg Poist <poist@google.com> | Thu Mar 24 11:59:54 2016 -0700 |
| tree | 98e835c1681534562a6187399a2a79db60bc678c | |
| parent | aca9c6c16734d1ee438760d0579afa2132ada73e [diff] |
ddr3libv2: tWR timing parameter configuration
- updated tWR DB entry for 8cc
- updated tWR configuration mask
Change-Id: I24435b90aafa28ff25953a2513f7e4fa076cee98
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24858
Reviewed-by: Ofer Benjamin <oferb@marvell.com>