ddr3libv2: tWR timing parameter configuration
- updated tWR DB entry for 8cc
- updated tWR configuration mask
Change-Id: I24435b90aafa28ff25953a2513f7e4fa076cee98
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24858
Reviewed-by: Ofer Benjamin <oferb@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 5b80bb6..50ab797 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -656,8 +656,8 @@
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("clValue 0x%x cwlVal 0x%x \n", clValue, cwlVal));
dataValue = ((clMaskTable[clValue] & 0x1) << 2) | ((clMaskTable[clValue] & 0xE) << 3);
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, MR0_REG, dataValue,(0x7 << 4) | (1 << 2)));
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, MR0_REG, twrMaskTable[tWR + 1],0xE00));
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, MR0_REG, dataValue, (0x7 << 4) | (1 << 2)));
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, accessType, interfaceId, MR0_REG, (twrMaskTable[tWR + 1] << 9), (0x7 << 9)));
/* MR1: Set RTT and DIC Design GL values configured by user */
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, MR1_REG, gDic | gRttNom, 0x266));
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c
index 72b27fe..6c10a4e 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingDb.c
@@ -129,7 +129,7 @@
1, /*5*/
2, /*6*/
3, /*7*/
- 10,
+ 4, /*8*/
10,
5, /*10*/
10,
