msys: axp-amc: update Board- and Ctrl- Env initializing
- enable obtaining BoardSysClk for AXP
- enable printing SoC revision for AXP
Change-Id: Ia336a3a55df10e9b51e9f6e758d13b2cbb15b755
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Omri Itach <omrii@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/20550
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
index 354b7f9..4b9dd07 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
@@ -203,6 +203,12 @@
mvGppTypeSet(0, 0xFFFFFFFF, board->gppOutEnValLow);
mvGppTypeSet(1, 0xFFFFFFFF, board->gppOutEnValMid);
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID) {
+ MV_REG_WRITE(GPP_DATA_OUT_REG(2), board->gppOutValHigh);
+ mvGppPolaritySet(2, 0xFFFFFFFF, board->gppPolarityValHigh);
+ mvGppTypeSet(2, 0xFFFFFFFF, board->gppOutEnValHigh);
+ }
+
#ifndef CONFIG_CUSTOMER_BOARD_SUPPORT
mvBoardOobPortCfgSet();
#endif
@@ -544,6 +550,44 @@
}
/*******************************************************************************
+* mvBoardSysClkGetAxp - Get the board SysClk of AXP (CPU bus clock , i.e. DDR clock)
+*
+* DESCRIPTION:
+* This routine extract the CPU bus clock.
+*
+* INPUT:
+* countNum - Counter number.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32bit clock cycles in Hertz.
+*
+*******************************************************************************/
+MV_U32 mvBoardSysClkGetAxp(MV_VOID)
+{
+ MV_U32 idx;
+ MV_U32 cpuFreqMhz, ddrFreqMhz;
+ MV_CPU_ARM_CLK_RATIO clockRatioTbl[] = MV_DDR_L2_CLK_RATIO_TBL_AXP;
+
+ idx = MSAR_DDR_L2_CLK_RATIO_IDX(MV_REG_READ(MPP_SAMPLE_AT_RESET(0)),
+ MV_REG_READ(MPP_SAMPLE_AT_RESET(1)));
+
+ if (clockRatioTbl[idx].vco2cpu != 0) { /* valid ratio ? */
+ cpuFreqMhz = mvCpuPclkGet() / 1000000; /* obtain CPU freq */
+ cpuFreqMhz *= clockRatioTbl[idx].vco2cpu; /* compute VCO freq */
+ ddrFreqMhz = cpuFreqMhz / clockRatioTbl[idx].vco2ddr;
+ /* round up to integer MHz */
+ if (((cpuFreqMhz % clockRatioTbl[idx].vco2ddr) * 10 / clockRatioTbl[idx].vco2ddr) >= 5)
+ ddrFreqMhz++;
+
+ return ddrFreqMhz * 1000000;
+ } else
+ return 0xFFFFFFFF;
+}
+
+/*******************************************************************************
* mvBoardSysClkGet - Get the board SysClk (CPU bus clock , i.e. DDR clock)
*
* DESCRIPTION:
@@ -566,6 +610,8 @@
MV_U32 freq_tbl_ac3[] = MV_CORE_CLK_TBL_AC3;
MV_U16 family = mvCtrlDevFamilyIdGet(0);
+ if (family == MV_78460_DEV_ID)
+ return mvBoardSysClkGetAxp();
idx = MSAR_CORE_CLK(MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(0)), MV_DFX_REG_READ(DFX_DEVICE_SAR_REG(1)));
if (idx >= 7)
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
index fa2e37d..5c991f9 100755
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvLib.c
@@ -268,6 +268,8 @@
MV_U32 mppGroup;
MV_U32 mppVal;
MV_U32 i, gppMask;
+ int maxGroup = mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID ?
+ MV_MPP_MAX_GROUP_AXP : MV_MPP_MAX_GROUP;
/* Disable MBus Error Propagation */
@@ -280,23 +282,23 @@
mvBoardMppModulesScan();
/* Read MPP config values from board level and write MPP options to HW */
- for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) {
+ for (mppGroup = 0; mppGroup < maxGroup; mppGroup++) {
mppVal = mvBoardMppGet(mppGroup); /* get pre-defined values */
MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal);
}
/* disable all GPIO interrupts */
- for (i = 0; i < MV_GPP_MAX_GROUP; i++) {
+ for (i = 0; i < maxGroup; i++) {
MV_REG_WRITE(GPP_INT_MASK_REG(i), 0x0);
MV_REG_WRITE(GPP_INT_LVL_REG(i), 0x0);
}
/* clear all int */
- for (i = 0; i < MV_GPP_MAX_GROUP; i++)
+ for (i = 0; i < maxGroup; i++)
MV_REG_WRITE(GPP_INT_CAUSE_REG(i), 0x0);
/* Set gpp interrupts as needed */
- for (i = 0; i < MV_GPP_MAX_GROUP; i++) {
+ for (i = 0; i < maxGroup; i++) {
gppMask = mvBoardGpioIntMaskGet(i);
mvGppTypeSet(i, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(i, gppMask , (MV_GPP_IN_INVERT & gppMask));
@@ -309,12 +311,14 @@
if (MV_OK != mvCtrlSerdesPhyConfig())
mvOsPrintf("mvCtrlEnvInit: Can't init some or all SERDES lanes\n");
- mvCtrlDevBusInit();
+ if (mvCtrlDevFamilyIdGet(0) != MV_78460_DEV_ID) {
+ mvCtrlDevBusInit();
#ifdef ERRATA_GL_5956802
/* SW WA for ERRATA 5956802 - disable the external i2c debugger access */
MV_REG_BIT_RESET(TWSI_CONFIG_DEBUG_REG, TWSI_DEBUG_SLAVE_PORT0_EN);
#endif
+ }
mvOsDelay(100);
@@ -651,7 +655,11 @@
*******************************************************************************/
MV_STATUS mvCtrlNameGet(char *pNameBuff)
{
- mvOsSPrintf(pNameBuff, "%s", SOC_NAME_PREFIX);
+ if (mvCtrlDevFamilyIdGet(0) == MV_78460_DEV_ID)
+ mvOsSPrintf(pNameBuff, "%s", "");
+ else
+ mvOsSPrintf(pNameBuff, "%s", SOC_NAME_PREFIX);
+
return MV_OK;
}
@@ -721,7 +729,17 @@
mvOsSPrintf(pNameBuff, " Rev %s", revArrayAC3[revId]);
return;
}
-
+ } else if (ctrlFamily == MV_78460_DEV_ID) {
+ switch (mvCtrlModelRevGet()) {
+ case MV_78460_A0_ID:
+ mvOsSPrintf(pNameBuff, "%s", MV_78460_A0_NAME);
+ return;
+ case MV_78460_B0_ID:
+ mvOsSPrintf(pNameBuff, "%s", MV_78460_B0_NAME);
+ return;
+ default:
+ break;
+ }
} else
mvOsPrintf("%s: Error: Wrong controller model %#x\n", __func__, ctrlFamily);
