tools/marvell/bin_hdr/platform/utils/debug/xor_memtest.h

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#define SRAM_WIN_ID		0x4
#define SRAM_WIN_BASE		0x40000000

#define XOR_ENGINE_TIMEOUT	0x5000000

#define ST_KP_LEN		59
#define ONE			0xffffffff
#define ZERO			0
#define BUS_STATUS(nValue)	((nValue) ? ONE : ZERO)
#define BIT(X)			(0x1 << X)

#define NUM_OF_DESC		8
#define DESC_SIZE		_8M

#define SOURCE_ADDRESS_BASE    0x83000000
#define BLOCK_SIZE             _1M
#define TOTAL_BLOCK_SIZE       (BLOCK_SIZE*2)
#define KILLER_64BIT_BASE      SOURCE_ADDRESS_BASE
#define KILLER_128BIT_BASE     (KILLER_64BIT_BASE + BLOCK_SIZE)
#define CPU_BURST_SIZE         _1K

#define DESTANTION_ADDRESS_BASE 0x84000000
#define DESTANTION_SIZE         _128M

#define NUM_OF_XOR_ENGINE              4
#define XOR_BLOCK_SIZE                 (_16M - 1)
#define XOR_SOURCE_ADDRESS(nXorNum)    (0x10000000 + _128M*nXorNum)
#define XOR_DEST_ADDRESS(nXorNum)      (XOR_SOURCE_ADDRESS(nXorNum) + (DESC_SIZE*NUM_OF_DESC))

#define MV_PLD(Address)\
{\
	__asm__ __volatile__("pld [%0]" : : "r" (Address));\
}

#define MV_PLD_RANGE(from, to)\
{\
	MV_U32 addr;\
	for (addr = from; addr < to; addr += 32) {\
		MV_PLD(addr);\
	} \
}

#define CHECK_CRC_STATUS(status)\
{\
	if (status != MV_OK) {\
		mvPrintf("Failed to calculate CRC32\n");\
		return 1;\
	} \
}

void cache_inv(MV_U32 dest);
void flush_l1_v7(MV_U32 dest);

#define MV_FLUSH_CACHE_L1(from, to)\
{\
	MV_U32 addr;\
	for (addr = from; addr < to; addr += 32) {\
		cache_inv(addr);\
		flush_l1_v7(addr);\
	} \
}

#define KILLER_PATTERN_BUS_STATE\
	{\
		0, 0, 0, 1, 1, 1, 0, 1, 0, 1,\
		0, 0, 1, 0, 1, 0, 1, 0, 1, 0,\
		1, 0, 1, 0, 0, 1, 0, 1, 0, 0,\
		0, 1, 1, 1, 0, 0, 1, 1, 0, 1,\
		0, 1, 1, 0, 0, 1, 0, 1, 1, 0,\
		1, 1, 0, 1, 1, 0, 0\
	}

#define KILLER_PATTERN_BIT_STATE\
	{\
		1, 0, 1, 1, 0, 0, 1, 0, 1, 0,\
		1, 1, 0, 1, 0, 0, 1, 0, 1, 0,\
		1, 0, 1, 1, 0, 1, 0, 1, 0, 0,\
		0, 0, 0, 1, 0, 0, 1, 1, 0, 1,\
		0, 1, 1, 0, 0, 1, 0, 1, 0, 0,\
		0, 0, 0, 1, 1, 1, 1\
	}