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| *******************************************************************************/ |
| #ifndef _INC_DDR_H |
| #define _INC_DDR_H |
| |
| #include "mv_os.h" |
| |
| #include "config_marvell.h" /* Required to identify SOC and Board */ |
| |
| #ifdef MV88F78X60 |
| #include "ddr3_axp.h" |
| #elif defined(MV88F67XX) |
| #include "ddr3_a370.h" |
| #elif defined(MV88F66XX) |
| #include "ddr3_alp.h" |
| #elif defined(MV88F672X) |
| #include "ddr3_a375.h" |
| #elif defined(MV_MSYS_BC2) |
| #include "ddr3_msys_bc2.h" |
| #elif defined(MV_MSYS_AC3) |
| #include "ddr3_msys_ac3.h" |
| #elif defined(MV88F68XX) |
| #include "ddr3_a38x.h" |
| #endif |
| |
| /*DRR training Error codes*/ |
| /*Stage 0 errors*/ |
| #define MV_DDR3_TRAINING_ERR_BAD_SAR 0xDD300001 |
| /*Stage 1 errors*/ |
| #define MV_DDR3_TRAINING_ERR_TWSI_FAIL 0xDD301001 |
| #define MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH 0xDD301001 |
| #define MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE 0xDD301003 |
| #define MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH 0xDD301004 |
| #define MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP 0xDD301005 |
| #define MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT 0xDD301006 |
| #define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT 0xDD301007 |
| #define MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP 0xDD301008 |
| /*Stage 2 errors*/ |
| #define MV_DDR3_TRAINING_ERR_HW_FAIL_BASE 0xDD302000 |
| |
| typedef enum _mvConfigType { |
| CONFIG_ECC, |
| CONFIG_MULTI_CS, |
| CONFIG_BUS_WIDTH |
| } MV_CONFIG_TYPE; |
| |
| typedef enum { |
| MV_LOG_LEVEL_0, |
| MV_LOG_LEVEL_1, |
| MV_LOG_LEVEL_2, |
| MV_LOG_LEVEL_3 |
| } MV_LOG_LEVEL; |
| |
| |
| MV_STATUS ddr3HwTraining(MV_U32 uiTargetFreq, MV_U32 uiDdrWidth, |
| MV_BOOL bXorBypass, MV_U32 uiScrubOffs, MV_U32 uiScrubSize, MV_BOOL bDQSCLKAligned, |
| MV_BOOL bDebugMode, MV_BOOL bRegDimmSkipWL); |
| |
| MV_VOID ddr3PrintVersion(void); |
| |
| MV_VOID fixPLLValue(MV_U8 targetFabric); |
| MV_U8 ddr3GetEpromFabric(void); |
| |
| MV_VOID uDelay(MV_U32 uiDelay); |
| |
| MV_U32 ddr3GetFabOpt(void); |
| MV_U32 ddr3GetCpuFreq(void); |
| MV_U32 ddr3GetVCOFreq(void); |
| MV_BOOL ddr3CheckConfig(MV_U32 twsiAddr, MV_CONFIG_TYPE configType); |
| MV_U32 ddr3GetStaticMCValue(MV_U32 regAddr, MV_U32 offset1, MV_U32 mask1, MV_U32 offset2, MV_U32 mask2); |
| |
| MV_U32 ddr3CLtoValidCL(MV_U32 uiCL); |
| MV_U32 ddr3ValidCLtoCL(MV_U32 uiValidCL); |
| MV_U32 ddr3GetCSNumFromReg(void); |
| MV_U32 ddr3GetCSEnaFromReg(void); |
| MV_U8 mvCtrlRevGet(MV_VOID); |
| MV_VOID levelLogPrintS(char *str,MV_LOG_LEVEL eLogLevel); |
| MV_VOID levelLogPrintD(MV_U32 dec_num,MV_U32 length,MV_LOG_LEVEL eLogLevel); |
| MV_VOID levelLogPrintDD(MV_U32 dec_num,MV_U32 length,MV_LOG_LEVEL eLogLevel); |
| MV_VOID printDunitSetup(void); |
| MV_VOID ddr3SetDqsResultsPrintStatus(MV_U32 status); |
| MV_U32 ddr3GetLogLevel(void); |
| MV_VOID ddr3NewTipDlbConfig(void); |
| MV_VOID ddr3GetAlpBusWidth(void); |
| MV_VOID ddr3GetA375BusWidth(void); |
| #endif /* _INC_DDR_H */ |
