commit 402048e3d4a28e4bdef24d05c9028d151f73cde1
author Igor Patrik <igorp@marvell.com> Mon May 11 14:45:38 2015 +0300
committer Greg Poist <poist@google.com> Thu Mar 24 11:59:54 2016 -0700
tree 3de3686c8ec3065a61783b1daf727822dc772cb0
parent 86978feb5ab0311acdf7f74c2d35b245cf0ebf03

ddr: a38x, a39x: Added warning message for not official freq SatR values

Change-Id: I754ed3df08bfd28da7fb40be3718a3d387b2dbc4
Signed-off-by: Igor Patrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/19139
Reviewed-by: Haim Boot <hayim@marvell.com>
Tested-by: Star_New_DDR <star-new-ddr@marvell.com>
Tested-by: Star_Automation <star@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24116
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>

tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c

diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index 2d72232..7026db5 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -710,30 +710,35 @@
     uiReg = (MV_REG_READ(REG_DEVICE_SAR1_ADDR)>> RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
     switch(uiReg) {
 #ifdef CONFIG_DDR3
-    case 0x0:
     case 0x1:
+		mvPrintf("Warning: Unsupported freq mode for 333Mhz configured(%d)\n", uiReg);
+    case 0x0:
         *freq = DDR_FREQ_333;
         break;
-    case 0x2:
     case 0x3:
+		mvPrintf("Warning: Unsupported freq mode for 400Mhz configured(%d)\n", uiReg);
+    case 0x2:
         *freq = DDR_FREQ_400;
         break;
-    case 0x4:
     case 0xd:
+		mvPrintf("Warning: Unsupported freq mode for 533Mhz configured(%d)\n", uiReg);
+    case 0x4:
         *freq = DDR_FREQ_533;
         break;
     case 0x6:
         *freq = DDR_FREQ_600;
         break;
 #endif
-    case 0x8:
 	case 0x11:
 	case 0x14:
+		mvPrintf("Warning: Unsupported freq mode for 667Mhz configured(%d)\n", uiReg);
+    case 0x8:
         *freq = DDR_FREQ_667;
         break;
-	case 0xC:
 	case 0x15:
 	case 0x1b:
+		mvPrintf("Warning: Unsupported freq mode for 800Mhz configured(%d)\n", uiReg);
+	case 0xC:
         *freq = DDR_FREQ_800;
         break;
 	case 0x10:
@@ -764,16 +769,16 @@
     /* Read sample at reset setting */
     uiReg = (MV_REG_READ(REG_DEVICE_SAR1_ADDR)>> RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) & RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
     switch(uiReg) {
-    case 0x0:
     case 0x1:
+    case 0x0:
         *freq = DDR_FREQ_333; /*Medium is same as TF to run PBS in this freq*/
         break;
-    case 0x2:
     case 0x3:
+    case 0x2:
         *freq = DDR_FREQ_400; /*Medium is same as TF to run PBS in this freq*/
         break;
-    case 0x4:
     case 0xd:
+    case 0x4:
         *freq = DDR_FREQ_533;
         break;
     case 0x8:
@@ -782,9 +787,9 @@
 	case 0x10:
         *freq = DDR_FREQ_333;
         break;
-	case 0xC:
 	case 0x15:
 	case 0x1b:
+	case 0xC:
         *freq = DDR_FREQ_400;
         break;
     case 0x6: