ddr3libv2: fix devel branch warnings in cpss compilation.
Change-Id: I8ee956a42e2be679a8e8251250d2c0960fcfe240
Signed-off-by: hayim <hayim@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/18272
Reviewed-by: Igor Patrik <igorp@marvell.com>
Tested-by: Igor Patrik <igorp@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/24108
Reviewed-by: Omri Itach <omrii@marvell.com>
Tested-by: Omri Itach <omrii@marvell.com>
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
index da7ee8b..659507a 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Debug.c
@@ -171,7 +171,7 @@
{
GT_U32 interfaceId, regAddr, dataValue, busId;
GT_U32 readData[MAX_INTERFACE_NUM];
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
mvPrintf("-- dunit registers --\n");
for(regAddr = 0x1400; regAddr < 0x19F0; regAddr+=4)
{
@@ -425,9 +425,12 @@
GT_STATUS ddr3TipPrintLog(GT_U32 devNum, GT_U32 memAddr)
{
GT_U32 interfaceId = 0;
- memAddr = memAddr;
-#ifdef DDR_VIEWER_TOOL
+ memAddr = memAddr; /* avoid warnings */
+
+#ifndef DDR_VIEWER_TOOL
+ devNum = devNum; /* avoid warnings */
+#else
if (( isValidateWindowPerIf != 0) || ( isValidateWindowPerPup != 0))
{
@@ -611,7 +614,7 @@
{
VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- mvPrintf("Data: %d,%d,",interfaceId, (configFuncInfo[devNum].tipGetTemperature != NULL)?(configFuncInfo[devNum].tipGetTemperature(devNum)):(0));
+ mvPrintf("Data: %d,%d,",interfaceId, (configFuncInfo[devNum].tipGetTemperature != NULL)?(configFuncInfo[devNum].tipGetTemperature((GT_U8)devNum)):(0));
CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0x14C8, readData, MASK_ALL_BITS));
mvPrintf("%d,%d,",((readData[interfaceId]&0x3F0)>>4),((readData[interfaceId]&0xFC00)>>10));
@@ -709,7 +712,7 @@
GT_U32 dataValue;
GT_U32 interfaceId = 0, busId = 0;
GT_U32 devNum = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* multi CS support - regAddr is calucalated in calling function with CS offset */
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
@@ -733,7 +736,7 @@
{
GT_U32 interfaceId = 0, busId = 0;
GT_U32 devNum = 0, data;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* multi CS support - regAddr is calucalated in calling function with CS offset */
@@ -824,7 +827,7 @@
GT_STATUS ddr3TipPrintAdll()
{
GT_U32 busCnt = 0, interfaceId, dataP1, dataP2, uiData3, devNum = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
index 6bf07f1..b314db9 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3Training.c
@@ -396,7 +396,7 @@
)
{
GT_U32 interfaceId, phyId;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, PAD_ZRI_CALIB_PHY_REG, ((0x7f & gZpriData) << 7 | (0x7f & gZnriData))));
CHECK_STATUS(mvHwsDdr3TipBUSWrite( devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL, PAD_ZRI_CALIB_PHY_REG, ((0x7f & gZpriCtrl) << 7 | (0x7f & gZnriCtrl))));
@@ -484,7 +484,7 @@
GT_U32 csCount;
GT_U32 csBitmask;
GT_U32 currCsNum = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(busCnt = 0; busCnt < octetsPerInterfaceNum; busCnt++)
{
@@ -530,7 +530,7 @@
GT_U32 refreshIntervalCnt = 0, busCnt = 0, adllTap = 0;
MV_HWS_ACCESS_TYPE accessType = ACCESS_TYPE_UNICAST;
GT_U32 dataRead[MAX_INTERFACE_NUM];
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("InitController, doMrsPhy=%d, isCtrl64Bit=%d\n", initCntrPrm->doMrsPhy, initCntrPrm->isCtrl64Bit));
@@ -778,7 +778,7 @@
MV_HWS_SPEED_BIN speedBinIndex;
MV_HWS_DDR_FREQ freq = DDR_FREQ_LIMIT;
GT_U32 interfaceId = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
ddr3TipSetTopologyMap(devNum, topologyMapPtr);
topologyMap = ddr3TipGetTopologyMap(devNum);
@@ -817,7 +817,7 @@
static GT_STATUS ddr3TipRankControl(GT_U32 devNum, GT_U32 interfaceId)
{
GT_U32 dataValue = 0, busCnt= 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(busCnt = 0; busCnt < octetsPerInterfaceNum; busCnt++)
{
@@ -884,7 +884,7 @@
)
{
GT_U32 busCnt, dataValue, ckSwapPupCtrl;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(busCnt = 0; busCnt < octetsPerInterfaceNum; busCnt++)
{
@@ -1192,7 +1192,7 @@
{
GT_U32 busIndex = 0;
GT_U32 dataRead[MAX_INTERFACE_NUM];
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
if (phyAccess == ACCESS_TYPE_MULTICAST)
{
@@ -1364,7 +1364,7 @@
{
MV_HWS_TIP_FREQ_CONFIG_INFO freqConfigInfo;
GT_U32 busCnt = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* Reset Diver_b assert -> de-assert*/
CHECK_STATUS (mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, SDRAM_CONFIGURATION_REG, 0, 0x10000000));
@@ -1423,7 +1423,7 @@
GT_U32 busIndex = 0, adllTap = 0;
MV_HWS_SPEED_BIN speedBinIndex = 0;
GT_U32 csMask[MAX_INTERFACE_NUM];
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("dev %d access %d IF %d freq %d\n",devNum , accessType , interfaceId , frequency));
@@ -2082,7 +2082,7 @@
)
{
GT_U32 interfaceId,busNum, csBitmask, dataVal, csNum;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
@@ -2228,7 +2228,7 @@
)
{
GT_U32 interfaceId, phyId,cs;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
@@ -2952,37 +2952,37 @@
GT_U32 devNum
)
{
- GT_BOOL isFail = GT_FALSE;
- GT_U32 interfaceId = 0, memMask= 0 , busIndex = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_BOOL isFail = GT_FALSE;
+ GT_U32 interfaceId = 0, memMask= 0 , busIndex = 0;
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
- /*Enable init sequence */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, SDRAM_INIT_CONTROL_REG, 0x1,0x1));
+ /*Enable init sequence */
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, 0, SDRAM_INIT_CONTROL_REG, 0x1,0x1));
- for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
- {
- VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
+ for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
+ {
+ VALIDATE_IF_ACTIVE(topologyMap->interfaceActiveMask, interfaceId)
- if (ddr3TipIfPolling(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0, 0x1, SDRAM_INIT_CONTROL_REG, MAX_POLLING_ITERATIONS) != GT_OK)
- {
- DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("polling failed IF %d \n",interfaceId));
- isFail = GT_TRUE;
- continue;
- }
- memMask = 0;
- for(busIndex=0; busIndex < octetsPerInterfaceNum ; busIndex++)
- {
- VALIDATE_BUS_ACTIVE(topologyMap->activeBusMask, busIndex)
- memMask |= topologyMap->interfaceParams[interfaceId].asBusParams[busIndex].mirrorEnableBitmask;
- }
- if (memMask != 0)
- {
- /*Disable MultiCS */
- CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,ACCESS_TYPE_MULTICAST, interfaceId, CS_ENABLE_REG, 1<<3, 1<<3));
- }
+ if (ddr3TipIfPolling(devNum, ACCESS_TYPE_UNICAST, interfaceId, 0, 0x1, SDRAM_INIT_CONTROL_REG, MAX_POLLING_ITERATIONS) != GT_OK)
+ {
+ DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("polling failed IF %d \n",interfaceId));
+ isFail = GT_TRUE;
+ continue;
+ }
+ memMask = 0;
+ for(busIndex=0; busIndex < octetsPerInterfaceNum ; busIndex++)
+ {
+ VALIDATE_BUS_ACTIVE(topologyMap->activeBusMask, busIndex)
+ memMask |= topologyMap->interfaceParams[interfaceId].asBusParams[busIndex].mirrorEnableBitmask;
+ }
+ if (memMask != 0)
+ {
+ /*Disable MultiCS */
+ CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,ACCESS_TYPE_MULTICAST, interfaceId, CS_ENABLE_REG, 1<<3, 1<<3));
+ }
- }
- return (isFail == GT_FALSE)? GT_OK:GT_FAIL;
+ }
+ return (isFail == GT_FALSE)? GT_OK:GT_FAIL;
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingCentralization.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingCentralization.c
index d7373be..a3ce64c 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingCentralization.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingCentralization.c
@@ -128,7 +128,7 @@
GT_U32 pupWinLength = 0;
MV_HWS_SearchDirection searchDirId;
GT_U8 consTap = (mode == CENTRAL_TX)?(64):(0);
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
@@ -387,7 +387,7 @@
GT_U32 csEnableRegVal[MAX_INTERFACE_NUM];
GT_U32 temp = 0;
int PadNum = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
if( ddr3TipSpecialRxRunOnceFlag != 0 )
return GT_OK;
@@ -502,7 +502,7 @@
)
{
GT_U32 interfaceId = 0, busId = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
devNum = devNum;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingHwAlgos.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingHwAlgos.c
index 98bf463..626aa6e 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingHwAlgos.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingHwAlgos.c
@@ -91,8 +91,8 @@
GT_U32 dataValue;
GT_U32 pupIndex;
GT_32 maxPhase = MIN_VALUE, currentPhase;
- MV_HWS_ACCESS_TYPE accessType = ACCESS_TYPE_UNICAST;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ MV_HWS_ACCESS_TYPE accessType = ACCESS_TYPE_UNICAST;
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum,accessType, interfaceId, DUNIT_ODT_CONTROL_REG, 0 << 8, 0x3 << 8));
CHECK_STATUS(mvHwsDdr3TipIFRead(devNum, accessType, interfaceId, READ_DATA_SAMPLE_DELAY, dataRead, MASK_ALL_BITS));
@@ -172,17 +172,18 @@
/* The Vref register have non linear order. need to check what will be in futur projects. */
GT_U32 vrefMap[8] = {1,2,3,4,5,6,7,0};
/* state and parameter definitions */
- GT_U32 initialStep = VREF_INITIAL_STEP;
- GT_U32 secondStep = VREF_SECOND_STEP;/* need to be assign with minus ????? */
+ GT_U8 initialStep = VREF_INITIAL_STEP;
+ GT_U8 secondStep = VREF_SECOND_STEP;/* need to be assign with minus ????? */
GT_U32 algoRunFlag = 0, currrentVref = 0;
GT_U32 whileCount = 0;
- GT_U32 pup = 0, interfaceId = 0, numPup = 0, Rep = 0;
+ GT_U32 pup = 0, interfaceId = 0, numPup = 0;
+ GT_U8 rep = 0;
GT_U32 dataValue = 0;
GT_U32 regAddr = 0xA8;
GT_U32 copyStartPattern, copyEndPattern;
MV_HWS_RESULT* flowResult = ddr3TipGetResultPtr(trainingStage);
GT_U8 res[4];
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
CHECK_STATUS(ddr3TipSpecialRx(devNum));
@@ -223,7 +224,7 @@
{
whileCount++;
- for(Rep = 1 ; Rep < 4 ; Rep++)
+ for(rep = 1 ; rep < 4 ; rep++)
{
ddr3TipCentralizationSkipMinWindowCheck = GT_TRUE;
ddr3TipCentralizationRx(devNum);
@@ -242,7 +243,7 @@
{
continue;
}
- currentValidWindow[pup][interfaceId] = (currentValidWindow[pup][interfaceId]*(Rep-1) + 1000*res[pup])/Rep;
+ currentValidWindow[pup][interfaceId] = (currentValidWindow[pup][interfaceId]*(rep-1) + 1000*res[pup])/rep;
}
}
}
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
index 4b8ff94..119197b 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingIpEngine.c
@@ -299,7 +299,7 @@
PatternInfo *patternTable = ddr3TipGetPatternTable();
GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
GT_U16 *maskResultsDqRegMap = ddr3TipGetMaskResultsDqReg();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
if (pupNum >= octetsPerInterfaceNum)
{
@@ -708,7 +708,7 @@
GT_U32 readData[MAX_INTERFACE_NUM];
GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
GT_U16 *maskResultsDqRegMap = ddr3TipGetMaskResultsDqReg();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* Agreed assumption: all CS mask contain same number of bits, i.e. in multi CS, the number of CS per memory is the same for all pups */
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_UNICAST, interfaceId, CS_ENABLE_REG, (csNumType == 0) ? 1<<3 : 0, (1 << 3)));
@@ -991,7 +991,7 @@
MV_HWS_SearchDirection searchDirId , startSearch, endSearch;
MV_HWS_EdgeCompare edgeCompUsed;
GT_U8 consTap = (direction == OPER_WRITE)?(64):(0);
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
if (trainStatus == NULL)
{
@@ -1094,7 +1094,7 @@
GT_U8 consTap = (direction == OPER_WRITE)?(64):(0);
GT_U8 bitBitMask[MAX_BUS_NUM] = {0}, bitBitMaskActive = 0;
GT_U8 pupId;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
if (pupNum >= octetsPerInterfaceNum)
{
@@ -1225,7 +1225,7 @@
GT_STATUS ddr3TipLoadPhyValues(GT_BOOL bLoad)
{
GT_U32 busCnt = 0, interfaceId, devNum = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
@@ -1268,7 +1268,7 @@
MV_HWS_TrainingIpStatus trainStatus[MAX_INTERFACE_NUM];
GT_U32 *pRes = NULL;
GT_U32 searchState = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
ddr3TipLoadPhyValues(GT_TRUE);
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
index f5b1584..d233ea1 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingLeveling.c
@@ -142,7 +142,7 @@
GT_U8 RLValues[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] ;
PatternInfo *patternTable = ddr3TipGetPatternTable();
GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++)
for(busNum = 0; busNum < MAX_BUS_NUM; busNum++)
@@ -443,7 +443,7 @@
GT_U32 data2Write[MAX_INTERFACE_NUM][MAX_BUS_NUM];
PatternInfo *patternTable = ddr3TipGetPatternTable();
GT_U16 *maskResultsDqRegMap = ddr3TipGetMaskResultsDqReg();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId < MAX_INTERFACE_NUM; interfaceId++)
{
@@ -697,7 +697,7 @@
{
GT_U32 allBusCs = 0, sameBusCs;
GT_U32 busCnt;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
devNum = devNum; /* avoid warnings */
@@ -744,7 +744,7 @@
GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
GT_U32 csMask0[MAX_INTERFACE_NUM]={0};
GT_U32 max_cs = mvHwsDdr3TipMaxCSGet();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
@@ -1014,7 +1014,7 @@
GT_32 adllOffset;
GT_U32 interfaceId, busId, data, dataTmp;
GT_BOOL isIfFail = GT_FALSE;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
{
@@ -1088,7 +1088,7 @@
GT_U32 devNum,
GT_U32 interfaceId,
GT_U32 busId,
- GT_U32 offset,
+ GT_U32 offset,
GT_U32 busIdDelta
)
{
@@ -1141,6 +1141,8 @@
PatternInfo *patternTable = ddr3TipGetPatternTable();
GT_U32 patternTestPatternTable[8];
+ busIdDelta = busIdDelta; /* avoid warnings */
+
for(i = 0; i < 8; i++) {
patternTestPatternTable[i] = patternTableGetWord(devNum, PATTERN_TEST, (GT_U8)i);
}
@@ -1204,8 +1206,11 @@
{
GT_32 phase, adll;
GT_U32 data;
+
DEBUG_LEVELING(DEBUG_LEVEL_TRACE, ("OneClkErrShift\n"));
+ busIdDelta = busIdDelta; /* avoid warnings */
+
CHECK_STATUS(mvHwsDdr3TipBUSRead( devNum, interfaceId, ACCESS_TYPE_UNICAST, busId, DDR_PHY_DATA, WL_PHY_REG, &data));
phase = ((data>>6) & 0x7);
adll = data & 0x1f;
@@ -1245,6 +1250,9 @@
{
GT_32 phase, adll;
GT_U32 data;
+
+ busIdDelta = busIdDelta; /* avoid warnings */
+
/* Shift WL result 1 phase back*/
CHECK_STATUS(mvHwsDdr3TipBUSRead( devNum, interfaceId, ACCESS_TYPE_UNICAST, busId, DDR_PHY_DATA, WL_PHY_REG, &data));
phase = ((data>>6) & 0x7);
@@ -1297,7 +1305,7 @@
GT_U32 busId, dqId;
GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
GT_U16 *maskResultsDqRegMap = ddr3TipGetMaskResultsDqReg();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_SW_2_REG, 0x1, 0x5));
CHECK_STATUS(mvHwsDdr3TipIFWrite(devNum, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_WRITE_LEVELING_REG, 0x50, 0xFF));
@@ -1341,7 +1349,7 @@
GT_U32 busId, dqId;
GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
GT_U16 *maskResultsDqRegMap = ddr3TipGetMaskResultsDqReg();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* mask PBS */
for (dqId=0; dqId<MAX_DQ_NUM; dqId++)
@@ -1373,7 +1381,7 @@
GT_U32 busId, dqId;
GT_U16 *maskResultsPupRegMap = ddr3TipGetMaskResultsPupRegMap();
GT_U16 *maskResultsDqRegMap = ddr3TipGetMaskResultsDqReg();
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* mask PBS */
for (dqId=0; dqId<MAX_DQ_NUM; dqId++)
@@ -1403,7 +1411,7 @@
GT_BOOL ddr3TipPrintWLSuppResult(GT_U32 devNum)
{
GT_U32 busId = 0,interfaceId = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
DEBUG_LEVELING(DEBUG_LEVEL_INFO,("I/F0 PUP0 Result[0 - success, 1-fail] ...\n"));
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
index 48692b4..d5f5dbd 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Driver/ddr3/mvHwsDdr3TrainingPbs.c
@@ -115,7 +115,7 @@
GT_U32 csEnableRegVal[MAX_INTERFACE_NUM];
GT_U16 *maskResultsDqRegMap = ddr3TipGetMaskResultsDqReg();
GT_U8 temp = 0;
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
/* save current cs enable reg val */
for(interfaceId = 0; interfaceId <= MAX_INTERFACE_NUM-1; interfaceId++)
@@ -665,7 +665,7 @@
{
GT_U32 interfaceId, pup, bit;
GT_U32 regAddr = (pbsMode == PBS_RX_MODE) ? (PBS_RX_PHY_REG + effective_cs * 0x10) : (PBS_TX_PHY_REG + effective_cs * 0x10);
- GT_U8 octetsPerInterfaceNum = ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
+ GT_U8 octetsPerInterfaceNum = (GT_U8)ddr3TipDevAttrGet(devNum, MV_ATTR_OCTET_PER_INTERFACE);
for( interfaceId = 0 ; interfaceId <= MAX_INTERFACE_NUM-1 ; interfaceId++)
{
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
index 0023c85..cd6ba7a 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3Bc2.c
@@ -1128,9 +1128,11 @@
/******************************************************************************
* return 1 of core/DUNIT clock ration is 1 for given freq, 0 if clock ratios is 2:1
*/
-GT_U8 ddr3TipClockMode( GT_U32 frequency )
+GT_U8 ddr3TipClockMode(GT_U32 frequency)
{
- return 2;
+ frequency = frequency; /* avoid warnings */
+
+ return 2;
}
