commit 355d7ceaf84c01bed8be5b674a9303608583682e
author Ed James <edjames@google.com> Wed Dec 16 14:03:53 2015 -0800
committer Ed James <edjames@google.com> Wed Dec 16 14:03:53 2015 -0800
tree 1333ed915c83cabbaf26fdaeeb2f252ba7c14011
parent 83f182ce82d726f4cafd0985334ee2a542f9b9c1

gfch100: enable DDR ECC in uboot

Change-Id: I6d674b840e10dc8bdf11e1b0bbb01b929881ea94

tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h

diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h
index 6ac748c..46ed119 100644
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h
@@ -103,7 +103,7 @@
     /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_width  mem_size     frequency  casL casWL      temperature */
 	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1600K, BUS_WIDTH_8 , MEM_2G, DDR_FREQ_400, 0 ,   0 , MV_HWS_TEMP_LOW}},
     5, /* Num Of Bus Per Interface*/
-    BUS_MASK_32BIT  /* Buses mask */
+    BUS_MASK_32BIT_ECC  /* Buses mask */
     }
 };