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/* #define RTC2_DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include "mv_rtc2.h"
#if defined(CONFIG_CMD_DATE)
static int rtc_ready = -1;
/*******************************************************/
void rtc_init(void)
{
/* Update RTC-MBUS bridge timing parameters */
#ifdef ERRATA_FE_3124064
/* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
* Description:
* The device supports CPU write and read access to the RTC Time register.
* However, due to this erratum, Write to RTC TIME register may fail.
* Read from RTC TIME register may fail.
* Workaround:
* Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
* RTC TIME register should be read twice, the second read will return a proper value.
* Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
* Functional Impact After Workaround is applied:
* No functional impact after WA is applied
*/
MV_REG_WRITE(MV_RTC2_SOC_OFFSET, 0xFD4D4FFF);
#else
MV_REG_WRITE(MV_RTC2_SOC_OFFSET, 0xFD4D4CFA);
#endif
rtc_ready = 1;
}
/*******************************************************/
int rtc_get(struct rtc_time *tm)
{
unsigned long time, time_check;
if (rtc_ready != 1)
rtc_init();
time = RTC_READ_REG(RTC_TIME_REG_OFFS);
#ifdef ERRATA_FE_3124064
/* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
* Description:
* The device supports CPU write and read access to the RTC Time register.
* However, due to this erratum, Write to RTC TIME register may fail.
* Read from RTC TIME register may fail.
* Workaround:
* Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
* RTC TIME register should be read twice, the second read will return a proper value.
* Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
* Functional Impact After Workaround is applied:
* No functional impact after WA is applied
*/
time_check = RTC_READ_REG(RTC_TIME_REG_OFFS);
if ((time_check - time) > 1)
time_check = RTC_READ_REG(RTC_TIME_REG_OFFS);
#endif
to_tm(time_check, tm);
return 0;
}
/*******************************************************/
int rtc_set(struct rtc_time *tm)
{
unsigned long time;
if (rtc_ready != 1)
rtc_init();
time = mktime(tm->tm_year, tm->tm_mon,
tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec);
#ifdef ERRATA_FE_3124064
/* Functional Errata Ref #: FE-3124064 - WA for failing time read attempts.
* Description:
* The device supports CPU write and read access to the RTC Time register.
* However, due to this erratum, Write to RTC TIME register may fail.
* Read from RTC TIME register may fail.
* Workaround:
* Before writing to RTC TIME register, issue a dummy write of 0x0 twice to RTC Status register.
* RTC TIME register should be read twice, the second read will return a proper value.
* Configure maximum value (0x3FF) in write clock period in RTC Mbus Bridge Timing Control register.
* Functional Impact After Workaround is applied:
* No functional impact after WA is applied
*/
RTC_WRITE_REG(0, RTC_STATUS_REG_OFFS);
RTC_WRITE_REG(0, RTC_STATUS_REG_OFFS);
#endif
RTC_WRITE_REG(time, RTC_TIME_REG_OFFS);
return 0;
}
/*******************************************************/
void rtc_reset(void)
{
/* Reset Test register */
RTC_WRITE_REG(0, RTC_TEST_CONFIG_REG_OFFS);
mdelay(500); /* Oscillator startup time */
/* Reset time register */
RTC_WRITE_REG(0, RTC_TIME_REG_OFFS);
udelay(62);
/* Reset Status register */
RTC_WRITE_REG((RTC_SZ_STATUS_ALARM1_MASK | RTC_SZ_STATUS_ALARM2_MASK), RTC_STATUS_REG_OFFS);
udelay(62);
/* Turn off Int1 and Int2 sources & clear the Alarm count */
RTC_WRITE_REG(0, RTC_IRQ_1_CONFIG_REG_OFFS);
RTC_WRITE_REG(0, RTC_IRQ_2_CONFIG_REG_OFFS);
RTC_WRITE_REG(0, RTC_ALARM_1_REG_OFFS);
RTC_WRITE_REG(0, RTC_ALARM_2_REG_OFFS);
/* Setup nominal register access timing */
RTC_WRITE_REG(RTC_NOMINAL_TIMING, RTC_CLOCK_CORR_REG_OFFS);
/* Reset time register */
RTC_WRITE_REG(0, RTC_TIME_REG_OFFS);
udelay(10);
/* Reset Status register */
RTC_WRITE_REG((RTC_SZ_STATUS_ALARM1_MASK | RTC_SZ_STATUS_ALARM2_MASK), RTC_STATUS_REG_OFFS);
udelay(50);
}
#endif /* CONFIG_CMD_DATE */