tools/marvell/debugger_scripts/XDB/a375_static.xdb

SET OPTION /MEMORY=LONG

! First descrease size of CS[2] to prevent overlap with 0xD0000000
! Data.Set 0xD00200b0 %LONG 0x000F3B11
SET VAL /SIZE=LONG 0xD00200b0 = 0x000F3B11

! Start DRAM init
! SDRAM_CONFIG_ADDR
! Data.Set 0xD0001400 %LONG 0x7B00C820
SET VAL /SIZE=LONG  0xD0001400 = 0x7B00C820

! SDRAM_DUNIT_CTRL_LOW_ADDR
! Data.Set 0xD0001404 %LONG 0x36301820
SET VAL /SIZE=LONG  0xD0001404 = 0x36301820

! SDRAM_TIMING_LOW_ADDR
! Data.Set 0xD0001408 %LONG 0x33137772
SET VAL /SIZE=LONG  0xD0001408 = 0x33137772

! SDRAM_TIMING_HI_ADDR
! Data.Set 0xD000140C %LONG 0x384019D5
SET VAL /SIZE=LONG  0xD000140C = 0x384019D5

! SDRAM_ADDR_CTRL_ADDR
! Data.Set 0xD0001410 %LONG 0x10000000
! Data.Set 0xD0001414 %LONG 0x00000700
SET VAL /SIZE=LONG  0xD0001410 = 0x10000000
SET VAL /SIZE=LONG  0xD0001414 = 0x00000700

! DDR_CONTROLLER_CTRL_HIGH
! Data.Set 0xD0001424 %LONG 0x0060F3FF
SET VAL /SIZE=LONG  0xD0001424 = 0x0060F3FF

! DDR_CONTROLLER_CTRL_HIGH
! Data.Set 0xD0001428 %LONG 0x000D6720
SET VAL /SIZE=LONG  0xD0001428 = 0x000D6720

! DDR ODT Timing (High) Register
! Data.Set 0xD000147C %LONG 0x0000B571
SET VAL /SIZE=LONG  0xD000147C = 0x0000B571

! SDRAM_SRAM_ODT_CNTL_LOW
! Data.Set 0xD0001494 %LONG 0x00030000
SET VAL /SIZE=LONG  0xD0001494 = 0x00030000

! SDRAM_ODT_CONTROL
! Data.Set 0xD000149C %LONG 0x303
SET VAL /SIZE=LONG  0xD000149C = 0x303

! AXI Control Register
! Data.Set 0xD00014A8 %LONG 0x0
SET VAL /SIZE=LONG  0xD00014A8 = 0x0

! Win 0 Control Register (This value will be writen by the bin header file to register 0x20184)
! Data.Set 0xD0001504 %LONG 0x7FFFFFE1
SET VAL /SIZE=LONG  0xD0001504 = 0x7FFFFFE1

! Win 1 Control Register (This value will be writen by the bin header file to register 0x2018C)
! Data.Set 0xD000150C %LONG 0x7FFFFFE5
SET VAL /SIZE=LONG  0xD000150C = 0x7FFFFFE5

! Win 2 Control Register (This value will be writen by the bin header file to register 0x20194)
! Data.Set 0xD0001514 %LONG 0x0
SET VAL /SIZE=LONG  0xD0001514 = 0x0

! Win 3 Control Register (This value will be writen by the bin header file to register 0x2019C)
! Data.Set 0xD000151C %LONG 0x0
SET VAL /SIZE=LONG  0xD000151C = 0x0

! Read Data Sample Delays Register
! Data.Set 0xD0001538 %LONG 0x707
SET VAL /SIZE=LONG  0xD0001538 = 0x707

! Read Data Ready Delays Register
! Data.Set 0xD000153C %LONG 0x707
SET VAL /SIZE=LONG  0xD000153C = 0x707

! DDR3 MR0 Register
! Data.Set 0xD00015D0 %LONG 0x630
SET VAL /SIZE=LONG  0xD00015D0 = 0x630

! DDR3 MR1 Register
! Data.Set 0xD00015D4 %LONG 0x46
SET VAL /SIZE=LONG  0xD00015D4 = 0x46

! DDR3 MR2 Register
! Data.Set 0xD00015D8 %LONG 0x8
SET VAL /SIZE=LONG  0xD00015D8 = 0x8

! DDR3 MR3 Register
! Data.Set 0xD00015DC %LONG 0x0
SET VAL /SIZE=LONG  0xD00015DC = 0x0

! DDR3 Rank Control Register
! Data.Set 0xD00015E0 %LONG 0x1
SET VAL /SIZE=LONG  0xD00015E0 = 0x1

! ZQC Configuration Register
! Data.Set 0xD00015E4 %LONG 0x203C18
SET VAL /SIZE=LONG  0xD00015E4 = 0x203C18

! DRAM PHY Configuration Register
! Data.Set 0xD00015EC %LONG 0xF8000025
SET VAL /SIZE=LONG  0xD00015EC = 0xF8000025

! DRAM address and Control Driving Strenght
! Data.Set 0xD00014C0 %LONG 0x192434E9
SET VAL /SIZE=LONG  0xD00014C0 = 0x192434E9

! DRAM Data and DQS Driving Strenght
! Data.Set 0xD00014C4 %LONG 0x192434E9
SET VAL /SIZE=LONG  0xD00014C4 = 0x192434E9

! Enable DDR
! Data.Set 0xD0001480 %LONG 0x1
SET VAL /SIZE=LONG  0xD0001480 = 0x1

! Set Dram size 256MB for FPGA (only if using XBAR)
! Data.Set 0xD0008C04 %LONG 0x3FFF0000
SET VAL /SIZE=LONG  0xD0008C04 = 0x3FFF0000

! set ddr_phy width
! Data.Set 0xD00014A8 %LONG 0x00000000
SET VAL /SIZE=LONG  0xD00014A8 = 0x00000000

! FASTPASS - enable Fastpass (set BIT0=1)
! Data.Set 0xD0020184 %LONG 0x1FFFFFE1
SET VAL /SIZE=LONG  0xD0020184 = 0x1FFFFFE1

! FASTPASS- close XBAR window 19 (set BIT0=0 - Disabled DDR window enabled in default)
! Data.Set 0xD00200E8 %LONG 0x0FFF0E00
SET VAL /SIZE=LONG  0xD00200E8 = 0x0FFF0E00

! training
! Data.Set 0xD00015B0 %LONG 0x80100008
SET VAL /SIZE=LONG  0xD00015B0 = 0x80100008

! WAIT 1.s
TCI DELAY 1000

! training
! Data.Set 0xD00015B0 %LONG 0x80100010
SET VAL /SIZE=LONG  0xD00015B0 = 0x80100010

! WAIT 1.s
TCI DELAY 1000

! training
! Data.Set 0xD00015B0 %LONG 0x80100040
SET VAL /SIZE=LONG  0xD00015B0 = 0x80100040

! WAIT 1.s
TCI DELAY 1000

! End DRAM init. The u-boot can be loaded and executed
PRINT "%s" "Done, DRAM is ready!\n"