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| *******************************************************************************/ |
| |
| #ifndef _MV_RTC2_H |
| #define _MV_RTC2_H |
| |
| #include <mvOs.h> |
| |
| #define MV_RTC2_REGS_OFFSET 0xA3800 |
| #define MV_RTC2_SOC_OFFSET 0x184A0 |
| |
| /* The RTC DRS revision 1.2 indicates that firmware should wait 5us after every register write |
| to the RTC hard macro, so that the required update can occur without holding off the system bus |
| */ |
| #define RTC_READ_REG(reg) MV_REG_READ(MV_RTC2_REGS_OFFSET + reg) |
| #define RTC_WRITE_REG(val, reg) { MV_REG_WRITE(MV_RTC2_REGS_OFFSET + reg, val); udelay(5); } |
| |
| #define RTC_0HZ 0x00 |
| #define RTC_1HZ 0x04 |
| #define RTC_2HZ 0x08 |
| #define RTC_4HZ 0x10 |
| #define RTC_8HZ 0x20 |
| |
| #define RTC_NOMINAL_TIMING 0x2000 |
| |
| #define RTC_STATUS_REG_OFFS 0x0 |
| #define RTC_IRQ_1_CONFIG_REG_OFFS 0x4 |
| #define RTC_IRQ_2_CONFIG_REG_OFFS 0x8 |
| #define RTC_TIME_REG_OFFS 0xC |
| #define RTC_ALARM_1_REG_OFFS 0x10 |
| #define RTC_ALARM_2_REG_OFFS 0x14 |
| #define RTC_CLOCK_CORR_REG_OFFS 0x18 |
| #define RTC_TEST_CONFIG_REG_OFFS 0x1C |
| |
| #define RTC_SZ_STATUS_ALARM1_MASK 0x1 |
| #define RTC_SZ_STATUS_ALARM2_MASK 0x2 |
| #define RTC_SZ_TIMING_RESERVED1_MASK 0xFFFF0000 |
| #define RTC_SZ_INTERRUPT1_INT1AE_MASK 0x1 |
| #define RTC_SZ_INTERRUPT1_RESERVED1_MASK 0xFFFFFFC0 |
| #define RTC_SZ_INTERRUPT2_INT2FE_MASK 0x2 |
| #define RTC_SZ_INTERRUPT2_RESERVED1_MASK 0xFFFFFFC0 |
| |
| #endif /* _MV_RTC2_H */ |
