fix: bobk: add dynamic frequency selection for CorePll WA issue
- The WA will take effect when HW SAR "coreclock" is set to bypass mode(7)
in this mode, use a new field "bypass_coreclock" to select the core
frequency in the WA.
- Add 'bypass mode' setting in SatR field "coreclock"
- Add SW SatR filed "bypass_coreclock" to select the frequency in
bypass mode, which located at eeprom reg#6 bits[2:0]
- Add more frequency support in the WA according to SAR setting
Signed-off-by: Terry <bjzhou@marvell.com>
Change-Id: I69d750781f1f04c9e2ddc2138624e8acdf3d36a3
Reviewed-on: http://vgitil04.il.marvell.com:8080/22742
Tested-by: Star_Automation <star@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
index 9cd7b33..9893c0d 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.c
@@ -1725,6 +1725,75 @@
DB(mvOsPrintf("Board: Write core FreqOpt S@R succeeded\n"));
return MV_OK;
}
+
+/*******************************************************************************
+* Read the new SW SatR field "bypass_coreclock" from EEPROM(0x50), reg#6 bits[2:0]
+*******************************************************************************/
+MV_STATUS mvBoardBypassCoreFreqGet(MV_U8 *value)
+{
+ MV_U8 sar0;
+ MV_STATUS rc1;
+ MV_U16 family = mvCtrlDevFamilyIdGet(0);
+
+ if (family != MV_BOBK_DEV_ID) {
+ DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
+ return MV_ERROR;
+ }
+
+ /* The Core Frequency in Bypass mode is taken from the first address-value pair of the EEPROM
+ initialization sequence, In order to support normal TWSI init sequence flow, the first pair
+ of DWORDS on EEPROM should contain an address (bytes 0-3) of some scratch pad register
+ (for instance an UART SCR) and a value (bytes 4-7), which will be partially interpreted
+ as Core Freq in bypass mode (bits[2:0] of byte 6)
+ */
+
+ rc1 = mvBoardTwsiRead(BOARD_DEV_TWSI_INIT_EPROM, 0, 6, &sar0);
+ if (MV_ERROR == rc1)
+ return MV_ERROR;
+
+ *value = (sar0 & 0x7);
+
+ return MV_OK;
+}
+
+/*******************************************************************************
+* Write the new SW SatR field "bypass_coreclock" to EEPROM(0x50), reg#6 bits[2:0]
+*******************************************************************************/
+MV_STATUS mvBoardBypassCoreFreqSet(MV_U8 freqVal)
+{
+ MV_U8 sar0;
+ MV_STATUS rc1;
+ MV_U16 family = mvCtrlDevFamilyIdGet(0);
+
+ if (family != MV_BOBK_DEV_ID) {
+ DB(mvOsPrintf("%s: Controller family (0x%04x) is not supported\n", __func__, family));
+ return MV_ERROR;
+ }
+
+ /* The Core Frequency in Bypass mode is taken from the first address-value pair of the EEPROM
+ initialization sequence, In order to support normal TWSI init sequence flow, the first pair
+ of DWORDS on EEPROM should contain an address (bytes 0-3) of some scratch pad register
+ (for instance an UART SCR) and a value (bytes 4-7), which will be partially interpreted
+ as Core Freq in bypass mode (bits[2:0] of byte 6)
+ */
+
+ rc1 = mvBoardTwsiRead(BOARD_DEV_TWSI_INIT_EPROM, 0, 6, &sar0);
+ if (MV_ERROR == rc1)
+ return MV_ERROR;
+
+ sar0 &= ~0x7;
+ sar0 |= (freqVal & 0x7);
+
+ if (MV_OK != mvBoardTwsiWrite(BOARD_DEV_TWSI_INIT_EPROM, 0, 6, sar0)) {
+ DB(mvOsPrintf("Board: Write Bypass core Freq S@R fail\n"));
+ return MV_ERROR;
+ }
+
+
+ DB(mvOsPrintf("Board: Write Bypss core FreqOpt S@R succeeded\n"));
+ return MV_OK;
+}
+
/*******************************************************************************/
MV_STATUS mvBoardCpuFreqGet(MV_U8 *value)
{
diff --git a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
index 343fbb3..d962a31 100755
--- a/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
+++ b/board/mv_ebu/msys/msys_family/boardEnv/mvBoardEnvLib.h
@@ -349,6 +349,8 @@
MV_STATUS mvBoardDramBusWidthSet(MV_U16 conf);
MV_U16 mvBoardDramBusWidthGet(MV_VOID);
MV_STATUS mvBoardCoreFreqGet(MV_U8 *value);
+MV_STATUS mvBoardBypassCoreFreqGet(MV_U8 *value);
+MV_STATUS mvBoardBypassCoreFreqSet(MV_U8 freqVal);
MV_STATUS mvBoardTmFreqGet(MV_U8 *value);
MV_STATUS mvBoardTmFreqSet(MV_U8 freqVal);
MV_STATUS mvBoardJtagCpuGet(MV_U8 *value);
diff --git a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
index d087b89..bc7c468 100644
--- a/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
+++ b/board/mv_ebu/msys/msys_family/ctrlEnv/mvCtrlEnvRegs.h
@@ -557,6 +557,12 @@
167, 133 \
}
+#define MV_BYPASS_CORE_CLK_TBL_BOBK { \
+ 365, 220, \
+ 250, 200, \
+ 167 \
+ }
+
#define MV_CORE_CLK_TBL_AC3 { \
290, 250, \
222, 167, \
