| /* Generated automatically by the program `genconstants' |
| from the machine description file `md'. */ |
| |
| #ifndef GCC_INSN_CONSTANTS_H |
| #define GCC_INSN_CONSTANTS_H |
| |
| #define R12_REG 12 |
| #define MUL64_OUT_REG 58 |
| #define LP_END 145 |
| #define LP_START 144 |
| #define R2_REG 2 |
| #define R10_REG 10 |
| #define R0_REG 0 |
| #define ILINK2_REGNUM 30 |
| #define R3_REG 3 |
| #define ARCV2_ACC 58 |
| #define SP_REG 28 |
| #define R1_REG 1 |
| #define RETURN_ADDR_REGNUM 31 |
| #define LP_COUNT 60 |
| #define ILINK1_REGNUM 29 |
| #define CC_REG 61 |
| |
| enum vunspec { |
| VUNSPEC_ARC_RTIE = 0, |
| VUNSPEC_ARC_SYNC = 1, |
| VUNSPEC_ARC_BRK = 2, |
| VUNSPEC_ARC_FLAG = 3, |
| VUNSPEC_ARC_SLEEP = 4, |
| VUNSPEC_ARC_SWI = 5, |
| VUNSPEC_ARC_CORE_READ = 6, |
| VUNSPEC_ARC_CORE_WRITE = 7, |
| VUNSPEC_ARC_LR = 8, |
| VUNSPEC_ARC_SR = 9, |
| VUNSPEC_ARC_TRAP_S = 10, |
| VUNSPEC_ARC_UNIMP_S = 11, |
| VUNSPEC_ARC_KFLAG = 12, |
| VUNSPEC_ARC_CLRI = 13, |
| VUNSPEC_ARC_SETI = 14, |
| VUNSPEC_ARC_NOP = 15, |
| VUNSPEC_ARC_STACK_IRQ = 16, |
| VUNSPEC_ARC_DEXCL = 17, |
| VUNSPEC_ARC_DEXCL_NORES = 18, |
| VUNSPEC_ARC_LR_HIGH = 19, |
| VUNSPEC_ARC_EX = 20, |
| VUNSPEC_ARC_CAS = 21, |
| VUNSPEC_ARC_SC = 22, |
| VUNSPEC_ARC_LL = 23 |
| }; |
| #define NUM_VUNSPEC_VALUES 24 |
| extern const char *const vunspec_strings[]; |
| |
| enum unspec { |
| DUMMY_0 = 0, |
| DUMMY_1 = 1, |
| DUMMY_2 = 2, |
| ARC_UNSPEC_PLT = 3, |
| ARC_UNSPEC_GOT = 4, |
| ARC_UNSPEC_GOTOFF = 5, |
| ARC_UNSPEC_GOTOFFPC = 6, |
| UNSPEC_TLS_GD = 7, |
| UNSPEC_TLS_LD = 8, |
| UNSPEC_TLS_IE = 9, |
| UNSPEC_TLS_OFF = 10, |
| UNSPEC_ARC_NORM = 11, |
| UNSPEC_ARC_NORMW = 12, |
| UNSPEC_ARC_SWAP = 13, |
| UNSPEC_ARC_DIVAW = 14, |
| UNSPEC_ARC_DIRECT = 15, |
| UNSPEC_ARC_LP = 16, |
| UNSPEC_ARC_CASESI = 17, |
| UNSPEC_ARC_FFS = 18, |
| UNSPEC_ARC_FLS = 19, |
| UNSPEC_ARC_MEMBAR = 20, |
| UNSPEC_ARC_DMACH = 21, |
| UNSPEC_ARC_DMACHU = 22, |
| UNSPEC_ARC_DMACWH = 23, |
| UNSPEC_ARC_DMACWHU = 24, |
| UNSPEC_ARC_QMACH = 25, |
| UNSPEC_ARC_QMACHU = 26, |
| UNSPEC_ARC_QMPYH = 27, |
| UNSPEC_ARC_QMPYHU = 28, |
| UNSPEC_ARC_VMAC2H = 29, |
| UNSPEC_ARC_VMAC2HU = 30, |
| UNSPEC_ARC_VMPY2H = 31, |
| UNSPEC_ARC_VMPY2HU = 32, |
| UNSPEC_ARC_SIMD_VADDAW = 33, |
| UNSPEC_ARC_SIMD_VADDW = 34, |
| UNSPEC_ARC_SIMD_VAVB = 35, |
| UNSPEC_ARC_SIMD_VAVRB = 36, |
| UNSPEC_ARC_SIMD_VDIFAW = 37, |
| UNSPEC_ARC_SIMD_VDIFW = 38, |
| UNSPEC_ARC_SIMD_VMAXAW = 39, |
| UNSPEC_ARC_SIMD_VMAXW = 40, |
| UNSPEC_ARC_SIMD_VMINAW = 41, |
| UNSPEC_ARC_SIMD_VMINW = 42, |
| UNSPEC_ARC_SIMD_VMULAW = 43, |
| UNSPEC_ARC_SIMD_VMULFAW = 44, |
| UNSPEC_ARC_SIMD_VMULFW = 45, |
| UNSPEC_ARC_SIMD_VMULW = 46, |
| UNSPEC_ARC_SIMD_VSUBAW = 47, |
| UNSPEC_ARC_SIMD_VSUBW = 48, |
| UNSPEC_ARC_SIMD_VSUMMW = 49, |
| UNSPEC_ARC_SIMD_VAND = 50, |
| UNSPEC_ARC_SIMD_VANDAW = 51, |
| UNSPEC_ARC_SIMD_VBIC = 52, |
| UNSPEC_ARC_SIMD_VBICAW = 53, |
| UNSPEC_ARC_SIMD_VOR = 54, |
| UNSPEC_ARC_SIMD_VXOR = 55, |
| UNSPEC_ARC_SIMD_VXORAW = 56, |
| UNSPEC_ARC_SIMD_VEQW = 57, |
| UNSPEC_ARC_SIMD_VLEW = 58, |
| UNSPEC_ARC_SIMD_VLTW = 59, |
| UNSPEC_ARC_SIMD_VNEW = 60, |
| UNSPEC_ARC_SIMD_VMR1AW = 61, |
| UNSPEC_ARC_SIMD_VMR1W = 62, |
| UNSPEC_ARC_SIMD_VMR2AW = 63, |
| UNSPEC_ARC_SIMD_VMR2W = 64, |
| UNSPEC_ARC_SIMD_VMR3AW = 65, |
| UNSPEC_ARC_SIMD_VMR3W = 66, |
| UNSPEC_ARC_SIMD_VMR4AW = 67, |
| UNSPEC_ARC_SIMD_VMR4W = 68, |
| UNSPEC_ARC_SIMD_VMR5AW = 69, |
| UNSPEC_ARC_SIMD_VMR5W = 70, |
| UNSPEC_ARC_SIMD_VMR6AW = 71, |
| UNSPEC_ARC_SIMD_VMR6W = 72, |
| UNSPEC_ARC_SIMD_VMR7AW = 73, |
| UNSPEC_ARC_SIMD_VMR7W = 74, |
| UNSPEC_ARC_SIMD_VMRB = 75, |
| UNSPEC_ARC_SIMD_VH264F = 76, |
| UNSPEC_ARC_SIMD_VH264FT = 77, |
| UNSPEC_ARC_SIMD_VH264FW = 78, |
| UNSPEC_ARC_SIMD_VVC1F = 79, |
| UNSPEC_ARC_SIMD_VVC1FT = 80, |
| UNSPEC_ARC_SIMD_VBADDW = 81, |
| UNSPEC_ARC_SIMD_VBMAXW = 82, |
| UNSPEC_ARC_SIMD_VBMINW = 83, |
| UNSPEC_ARC_SIMD_VBMULAW = 84, |
| UNSPEC_ARC_SIMD_VBMULFW = 85, |
| UNSPEC_ARC_SIMD_VBMULW = 86, |
| UNSPEC_ARC_SIMD_VBRSUBW = 87, |
| UNSPEC_ARC_SIMD_VBSUBW = 88, |
| UNSPEC_ARC_SIMD_VASRW = 89, |
| UNSPEC_ARC_SIMD_VSR8 = 90, |
| UNSPEC_ARC_SIMD_VSR8AW = 91, |
| UNSPEC_ARC_SIMD_VASRRWi = 92, |
| UNSPEC_ARC_SIMD_VASRSRWi = 93, |
| UNSPEC_ARC_SIMD_VASRWi = 94, |
| UNSPEC_ARC_SIMD_VASRPWBi = 95, |
| UNSPEC_ARC_SIMD_VASRRPWBi = 96, |
| UNSPEC_ARC_SIMD_VSR8AWi = 97, |
| UNSPEC_ARC_SIMD_VSR8i = 98, |
| UNSPEC_ARC_SIMD_VMVAW = 99, |
| UNSPEC_ARC_SIMD_VMVW = 100, |
| UNSPEC_ARC_SIMD_VMVZW = 101, |
| UNSPEC_ARC_SIMD_VD6TAPF = 102, |
| UNSPEC_ARC_SIMD_VMOVAW = 103, |
| UNSPEC_ARC_SIMD_VMOVW = 104, |
| UNSPEC_ARC_SIMD_VMOVZW = 105, |
| UNSPEC_ARC_SIMD_VABSAW = 106, |
| UNSPEC_ARC_SIMD_VABSW = 107, |
| UNSPEC_ARC_SIMD_VADDSUW = 108, |
| UNSPEC_ARC_SIMD_VSIGNW = 109, |
| UNSPEC_ARC_SIMD_VEXCH1 = 110, |
| UNSPEC_ARC_SIMD_VEXCH2 = 111, |
| UNSPEC_ARC_SIMD_VEXCH4 = 112, |
| UNSPEC_ARC_SIMD_VUPBAW = 113, |
| UNSPEC_ARC_SIMD_VUPBW = 114, |
| UNSPEC_ARC_SIMD_VUPSBAW = 115, |
| UNSPEC_ARC_SIMD_VUPSBW = 116, |
| UNSPEC_ARC_SIMD_VDIRUN = 117, |
| UNSPEC_ARC_SIMD_VDORUN = 118, |
| UNSPEC_ARC_SIMD_VDIWR = 119, |
| UNSPEC_ARC_SIMD_VDOWR = 120, |
| UNSPEC_ARC_SIMD_VREC = 121, |
| UNSPEC_ARC_SIMD_VRUN = 122, |
| UNSPEC_ARC_SIMD_VRECRUN = 123, |
| UNSPEC_ARC_SIMD_VENDREC = 124, |
| UNSPEC_ARC_SIMD_VCAST = 125, |
| UNSPEC_ARC_SIMD_VINTI = 126 |
| }; |
| #define NUM_UNSPEC_VALUES 127 |
| extern const char *const unspec_strings[]; |
| |
| #endif /* GCC_INSN_CONSTANTS_H */ |
