| /* Generated automatically by the program `genconstants' |
| from the machine description file `md'. */ |
| |
| #ifndef GCC_INSN_CONSTANTS_H |
| #define GCC_INSN_CONSTANTS_H |
| |
| #define CMP_CMP 0 |
| #define DOM_CC_NX_OR_Y 1 |
| #define DOM_CC_X_OR_Y 2 |
| #define NUM_OF_COND_CMP 4 |
| #define CC_REGNUM 100 |
| #define WCGR3 99 |
| #define SP_REGNUM 13 |
| #define R1_REGNUM 1 |
| #define PC_REGNUM 15 |
| #define WCGR0 96 |
| #define VFPCC_REGNUM 101 |
| #define CMP_CMN 2 |
| #define WCGR2 98 |
| #define R0_REGNUM 0 |
| #define WCGR1 97 |
| #define CMN_CMP 1 |
| #define LR_REGNUM 14 |
| #define DOM_CC_X_AND_Y 0 |
| #define CMN_CMN 3 |
| #define IP_REGNUM 12 |
| #define LAST_ARM_REGNUM 15 |
| |
| enum unspec { |
| UNSPEC_PUSH_MULT = 0, |
| UNSPEC_PIC_SYM = 1, |
| UNSPEC_PIC_BASE = 2, |
| UNSPEC_PRLG_STK = 3, |
| UNSPEC_REGISTER_USE = 4, |
| UNSPEC_CHECK_ARCH = 5, |
| UNSPEC_WSHUFH = 6, |
| UNSPEC_WACC = 7, |
| UNSPEC_TMOVMSK = 8, |
| UNSPEC_WSAD = 9, |
| UNSPEC_WSADZ = 10, |
| UNSPEC_WMACS = 11, |
| UNSPEC_WMACU = 12, |
| UNSPEC_WMACSZ = 13, |
| UNSPEC_WMACUZ = 14, |
| UNSPEC_CLRDI = 15, |
| UNSPEC_WALIGNI = 16, |
| UNSPEC_TLS = 17, |
| UNSPEC_PIC_LABEL = 18, |
| UNSPEC_PIC_OFFSET = 19, |
| UNSPEC_GOTSYM_OFF = 20, |
| UNSPEC_THUMB1_CASESI = 21, |
| UNSPEC_RBIT = 22, |
| UNSPEC_SYMBOL_OFFSET = 23, |
| UNSPEC_MEMORY_BARRIER = 24, |
| UNSPEC_UNALIGNED_LOAD = 25, |
| UNSPEC_UNALIGNED_STORE = 26, |
| UNSPEC_PIC_UNIFIED = 27, |
| UNSPEC_LL = 28, |
| UNSPEC_VRINTZ = 29, |
| UNSPEC_VRINTP = 30, |
| UNSPEC_VRINTM = 31, |
| UNSPEC_VRINTR = 32, |
| UNSPEC_VRINTX = 33, |
| UNSPEC_VRINTA = 34, |
| UNSPEC_WADDC = 35, |
| UNSPEC_WABS = 36, |
| UNSPEC_WQMULWMR = 37, |
| UNSPEC_WQMULMR = 38, |
| UNSPEC_WQMULWM = 39, |
| UNSPEC_WQMULM = 40, |
| UNSPEC_WQMIAxyn = 41, |
| UNSPEC_WQMIAxy = 42, |
| UNSPEC_TANDC = 43, |
| UNSPEC_TORC = 44, |
| UNSPEC_TORVSC = 45, |
| UNSPEC_TEXTRC = 46, |
| UNSPEC_ASHIFT_SIGNED = 47, |
| UNSPEC_ASHIFT_UNSIGNED = 48, |
| UNSPEC_CRC32B = 49, |
| UNSPEC_CRC32H = 50, |
| UNSPEC_CRC32W = 51, |
| UNSPEC_CRC32CB = 52, |
| UNSPEC_CRC32CH = 53, |
| UNSPEC_CRC32CW = 54, |
| UNSPEC_AESD = 55, |
| UNSPEC_AESE = 56, |
| UNSPEC_AESIMC = 57, |
| UNSPEC_AESMC = 58, |
| UNSPEC_SHA1C = 59, |
| UNSPEC_SHA1M = 60, |
| UNSPEC_SHA1P = 61, |
| UNSPEC_SHA1H = 62, |
| UNSPEC_SHA1SU0 = 63, |
| UNSPEC_SHA1SU1 = 64, |
| UNSPEC_SHA256H = 65, |
| UNSPEC_SHA256H2 = 66, |
| UNSPEC_SHA256SU0 = 67, |
| UNSPEC_SHA256SU1 = 68, |
| UNSPEC_VMULLP64 = 69, |
| UNSPEC_LOAD_COUNT = 70, |
| UNSPEC_VABD = 71, |
| UNSPEC_VABDL = 72, |
| UNSPEC_VADD = 73, |
| UNSPEC_VADDHN = 74, |
| UNSPEC_VADDL = 75, |
| UNSPEC_VADDW = 76, |
| UNSPEC_VBSL = 77, |
| UNSPEC_VCAGE = 78, |
| UNSPEC_VCAGT = 79, |
| UNSPEC_VCEQ = 80, |
| UNSPEC_VCGE = 81, |
| UNSPEC_VCGEU = 82, |
| UNSPEC_VCGT = 83, |
| UNSPEC_VCGTU = 84, |
| UNSPEC_VCLS = 85, |
| UNSPEC_VCONCAT = 86, |
| UNSPEC_VCVT = 87, |
| UNSPEC_VCVT_N = 88, |
| UNSPEC_VEXT = 89, |
| UNSPEC_VHADD = 90, |
| UNSPEC_VHSUB = 91, |
| UNSPEC_VLD1 = 92, |
| UNSPEC_VLD1_LANE = 93, |
| UNSPEC_VLD2 = 94, |
| UNSPEC_VLD2_DUP = 95, |
| UNSPEC_VLD2_LANE = 96, |
| UNSPEC_VLD3 = 97, |
| UNSPEC_VLD3A = 98, |
| UNSPEC_VLD3B = 99, |
| UNSPEC_VLD3_DUP = 100, |
| UNSPEC_VLD3_LANE = 101, |
| UNSPEC_VLD4 = 102, |
| UNSPEC_VLD4A = 103, |
| UNSPEC_VLD4B = 104, |
| UNSPEC_VLD4_DUP = 105, |
| UNSPEC_VLD4_LANE = 106, |
| UNSPEC_VMAX = 107, |
| UNSPEC_VMIN = 108, |
| UNSPEC_VMLA = 109, |
| UNSPEC_VMLAL = 110, |
| UNSPEC_VMLA_LANE = 111, |
| UNSPEC_VMLAL_LANE = 112, |
| UNSPEC_VMLS = 113, |
| UNSPEC_VMLSL = 114, |
| UNSPEC_VMLS_LANE = 115, |
| UNSPEC_VMLSL_LANE = 116, |
| UNSPEC_VMOVL = 117, |
| UNSPEC_VMOVN = 118, |
| UNSPEC_VMUL = 119, |
| UNSPEC_VMULL = 120, |
| UNSPEC_VMUL_LANE = 121, |
| UNSPEC_VMULL_LANE = 122, |
| UNSPEC_VPADAL = 123, |
| UNSPEC_VPADD = 124, |
| UNSPEC_VPADDL = 125, |
| UNSPEC_VPMAX = 126, |
| UNSPEC_VPMIN = 127, |
| UNSPEC_VPSMAX = 128, |
| UNSPEC_VPSMIN = 129, |
| UNSPEC_VPUMAX = 130, |
| UNSPEC_VPUMIN = 131, |
| UNSPEC_VQABS = 132, |
| UNSPEC_VQADD = 133, |
| UNSPEC_VQDMLAL = 134, |
| UNSPEC_VQDMLAL_LANE = 135, |
| UNSPEC_VQDMLSL = 136, |
| UNSPEC_VQDMLSL_LANE = 137, |
| UNSPEC_VQDMULH = 138, |
| UNSPEC_VQDMULH_LANE = 139, |
| UNSPEC_VQDMULL = 140, |
| UNSPEC_VQDMULL_LANE = 141, |
| UNSPEC_VQMOVN = 142, |
| UNSPEC_VQMOVUN = 143, |
| UNSPEC_VQNEG = 144, |
| UNSPEC_VQSHL = 145, |
| UNSPEC_VQSHL_N = 146, |
| UNSPEC_VQSHLU_N = 147, |
| UNSPEC_VQSHRN_N = 148, |
| UNSPEC_VQSHRUN_N = 149, |
| UNSPEC_VQSUB = 150, |
| UNSPEC_VRECPE = 151, |
| UNSPEC_VRECPS = 152, |
| UNSPEC_VREV16 = 153, |
| UNSPEC_VREV32 = 154, |
| UNSPEC_VREV64 = 155, |
| UNSPEC_VRSQRTE = 156, |
| UNSPEC_VRSQRTS = 157, |
| UNSPEC_VSHL = 158, |
| UNSPEC_VSHLL_N = 159, |
| UNSPEC_VSHL_N = 160, |
| UNSPEC_VSHR_N = 161, |
| UNSPEC_VSHRN_N = 162, |
| UNSPEC_VSLI = 163, |
| UNSPEC_VSRA_N = 164, |
| UNSPEC_VSRI = 165, |
| UNSPEC_VST1 = 166, |
| UNSPEC_VST1_LANE = 167, |
| UNSPEC_VST2 = 168, |
| UNSPEC_VST2_LANE = 169, |
| UNSPEC_VST3 = 170, |
| UNSPEC_VST3A = 171, |
| UNSPEC_VST3B = 172, |
| UNSPEC_VST3_LANE = 173, |
| UNSPEC_VST4 = 174, |
| UNSPEC_VST4A = 175, |
| UNSPEC_VST4B = 176, |
| UNSPEC_VST4_LANE = 177, |
| UNSPEC_VSTRUCTDUMMY = 178, |
| UNSPEC_VSUB = 179, |
| UNSPEC_VSUBHN = 180, |
| UNSPEC_VSUBL = 181, |
| UNSPEC_VSUBW = 182, |
| UNSPEC_VTBL = 183, |
| UNSPEC_VTBX = 184, |
| UNSPEC_VTRN1 = 185, |
| UNSPEC_VTRN2 = 186, |
| UNSPEC_VTST = 187, |
| UNSPEC_VUZP1 = 188, |
| UNSPEC_VUZP2 = 189, |
| UNSPEC_VZIP1 = 190, |
| UNSPEC_VZIP2 = 191, |
| UNSPEC_MISALIGNED_ACCESS = 192, |
| UNSPEC_VCLE = 193, |
| UNSPEC_VCLT = 194, |
| UNSPEC_NVRINTZ = 195, |
| UNSPEC_NVRINTP = 196, |
| UNSPEC_NVRINTM = 197, |
| UNSPEC_NVRINTX = 198, |
| UNSPEC_NVRINTA = 199, |
| UNSPEC_NVRINTN = 200 |
| }; |
| #define NUM_UNSPEC_VALUES 201 |
| extern const char *const unspec_strings[]; |
| |
| enum unspecv { |
| VUNSPEC_BLOCKAGE = 0, |
| VUNSPEC_EPILOGUE = 1, |
| VUNSPEC_THUMB1_INTERWORK = 2, |
| VUNSPEC_ALIGN = 3, |
| VUNSPEC_POOL_END = 4, |
| VUNSPEC_POOL_1 = 5, |
| VUNSPEC_POOL_2 = 6, |
| VUNSPEC_POOL_4 = 7, |
| VUNSPEC_POOL_8 = 8, |
| VUNSPEC_POOL_16 = 9, |
| VUNSPEC_TMRC = 10, |
| VUNSPEC_TMCR = 11, |
| VUNSPEC_ALIGN8 = 12, |
| VUNSPEC_WCMP_EQ = 13, |
| VUNSPEC_WCMP_GTU = 14, |
| VUNSPEC_WCMP_GT = 15, |
| VUNSPEC_EH_RETURN = 16, |
| VUNSPEC_ATOMIC_CAS = 17, |
| VUNSPEC_ATOMIC_XCHG = 18, |
| VUNSPEC_ATOMIC_OP = 19, |
| VUNSPEC_LL = 20, |
| VUNSPEC_SC = 21, |
| VUNSPEC_LAX = 22, |
| VUNSPEC_SLX = 23, |
| VUNSPEC_LDA = 24, |
| VUNSPEC_STL = 25 |
| }; |
| #define NUM_UNSPECV_VALUES 26 |
| extern const char *const unspecv_strings[]; |
| |
| #endif /* GCC_INSN_CONSTANTS_H */ |
